Prosecution Insights
Last updated: August 18, 2026
Application No. 17/554,442

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING RAISED WALL STRUCTURES FOR EPITAXIAL SOURCE OR DRAIN REGION CONFINEMENT

Non-Final OA §103§112
Filed
Dec 17, 2021
Examiner
ADHIKARI DAWADI, BIPANA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
3 (Non-Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
8 granted / 8 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
33 currently pending
Career history
56
Total Applications
across all art units

Statute-Specific Performance

§103
49.5%
+9.5% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
38.5%
-1.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 8 resolved cases

Office Action

§103 §112
DETAILED ACTION This office action is in response to the Request for Continued Examination (RCE) filed on 04/13/2026. Claims 1-20 are pending in the application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/03/2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 6-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 6 recited “…the intervening dielectric structure having a top surface…below a top surface of the neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures…”. The specification describes recessing wall-extending dielectric material (e.g., dielectric material 426) relative to sacrificial epitaxial structures (e.g., 424), stating that the dielectric material is recessed to a level below a top surface of the sacrificial epitaxial structures (see e.g., fig. 4E and corresponding description). The specification further describes that the sacrificial epitaxial structures are subsequently removed, leaving cavities. Although the specification indicated that subsequent processing may include epitaxial growth in the cavities, the specification and figures do not clearly describe that the epitaxial source/drain structures ultimately formed have a top surface above the top surface of the intervening dielectric structure as now claimed. Claim 6 further recites “…the intervening structure having a bottommost surface below a bottommost surface of the first epitaxial source or drain structures and the second epitaxial source or drain structures…”. The specification describes dielectric structures 422/426A positioned between neighboring source or drain cavities 430. The specification further states that subsequent processing may include forming epitaxial source or drain structures in cavities 430. However, neither the specification not the drawings describe the bottommost surface of the subsequently formed epitaxial source or drain structures relative to the bottommost surface of dielectric structure 422/426A. In particular, Fig. 4F shows cavities 430 before the final epitaxial source or drain structures are formed and therefore does not establish the final lower boundaries of those structures. The disclosure does not state that the subsequently formed epitaxial source or drain structures necessarily terminate above the bottommost surface of dielectric structure 122/426A. Claims 7-10 are rejected under 35 U.S.C. 112(a) for their dependency of claim 6. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites the limitation "…a gate stack over the first and second vertical arrangements of nanowires…" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this examination, claim 6 will be interpreted as “…a gate stack over a first and second vertical arrangements of nanowires…”. For the purpose of examination, the limitation is interpretated as “…a gate stack over the first and second fins…”. Claim 6 further recites the limitation “…the intervening structure having a bottommost surface…”. It is unclear if the “the intervening structure” is the same “intervening dielectric structure” recited earlier in claim 6, or a different “intervening structure”. For the purpose of examination, the limitation is interpretated as “…intervening dielectric structure having a bottommost surface…”. Claims 7-10 are rejected under 35 U.S.C. 112(b) for their dependency of claim 6. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kobrinsky (US 20200075770 A1) in view of Kim (US 20160293697 A1) further in view of Huang (US 20170069621 A1) and further in view of Xie (US 20230038116 A1). Re: Independent Claim 6 (currently amended), Kobrinsky discloses an integrated circuit structure, comprising: a first fin (Kobrinsky, Fig 1J, first #104A', also see fig 3, first #304) and a second fin (Kobrinsky, Fig 1J, second #104B', also see fig 3, second #304); a gate stack (Kobrinsky, Fig 1J and ¶ [0045]) over the first and second vertical arrangements of nanowires (Fig 1J, [0051], #104A and 104B "may be nanowire channels") (See also fig. 3 gate stack #308 over first nanowires #304A and second nanowires #304B); first epitaxial source or drain structures (Kobrinsky, Fig1J, #120) at ends of the first fin; second epitaxial source or drain structures (Kobrinsky, Fig1J, #112) at ends of the second fin; and an intervening dielectric structure (Kobrinsky, Fig 1J, #124) between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures, the intervening dielectric structure having a top surface (Kobrinsky, Fig 1J, top surface of #124) above a top surface (Kobrinsky, Fig 1J, top surface of 104A' and 104B') of the first and second fins. Kobrinsky is silent regarding: and the intervening dielectric structure having a width at the top surface of the intervening dielectric structure less than a width below the top surface of the intervening dielectric structure. However, Kim teaches the intervening dielectric structure having a width at the top surface of the intervening dielectric structure (Kim, Fig 5, width of top insulating layer #300/240) less than a width below the top surface of the intervening dielectric structure (Kim, Fig 5, width below the top of insulating layer #300/240). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use Kim disclosed intervening dielectric structure having a width at the top surface of the intervening dielectric structure less than a width below the top surface of the intervening dielectric structure in the structure of Kobrinsky in order to provide dielectric separation between closely spaced neighboring source or drain structures while conforming to the shape and spacing of the adjacent epitaxial source or drain regions. Both Kobrinsky and Kim are silent regarding the amended limitation: “the intervening dielectric structure having a top surface below a top surface of the neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures”. However, Huang the intervening dielectric structure having a top surface below a top surface of the neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures (Huang teaches, in Fig. 6, ¶ [0026], forming dielectric fin/sidewall structures (260) whose height is set/tuned to adjust epitaxy profile of epitaxy structures (272 and 276), and teaches that epitaxy structures (276) protrude from the recesses and have top portions of 272 and 276 presented above the dielectric structure 260). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kobrinsky’s intervening dielectric structure (124) (e.g., by etch-back/height tuning of the dielectric wall between neighboring source/drain regions) so that its top surface is below the top surface of the neighboring epitaxial Source/drain structures, as taught by Huang, in order to control the epitaxial S/D growth/profile and maintain separation/isolation between neighboring S/D regions (Huang, ¶ [0026]). Kobrinsky, Kim and Huang are silent regarding the intervening structure having a bottommost surface below a bottommost surface of the first epitaxial source or drain structures and the second epitaxial source or drain structures. However, Xie teaches, in Fig. 10C, a forksheet nanosheet semiconductor device having first and second stacks of channel nanosheets separated by a dielectric pillar 130, first and second epitaxial source or drain regions 180 and 182 disposed on opposite sides of and directly adjacent the dielectric pillar, and a gate structure associated with the nanosheet stacks. Xie teaches, in ¶¶ [0075] – [0078], that dielectric pillar 130 is formed in a pillar trench extending to substrate 110 and physically and electrically separates the neighboring nanosheet transistor structures. Xie teaches, in Fig. 10C, that the dielectric pillar has a bottom surface below a bottom surface of a source or drain region. Xie’s shared dielectric pillar extends downward between the neighboring first and second source or drain regions 180 and 182 to the substrate, thereby providing a bottommost surface below the bottommost surfaces of the neighboring source or drain regions. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to extend Kobrinsky’s intervening dielectric structure 124 downward below the bottommost surfaces of the neighboring epitaxial source or drain structures, as taught by Xie, in order to provide improved physical and electrical isolation between closely spaced neighboring nanosheet transistor structures. Xie explains that its dielectric pillar physically isolates the p-type and n-type sides and permits tighter spacing between the neighboring devices. Extending Kobrinsky’s dielectric structure downward in the manner taught by Xie would have constituted the predictable use of a known deep dielectric isolation pillar in a similar neighboring nanosheet transistor arrangement. Re: Claim 8 (original), Kobrinsky, Kim, Huang and Xie disclose all the limitations of claim 6 on which this claim depends. Kim further discloses: wherein the intervening dielectric structure comprises an upper dielectric material (Kim, Fig 5, #300) on a lower dielectric material (Kim, Fig 5, #240). Re: Claim 9 (original), Kobrinsky, Kim, Huang and Xie disclose all the limitations of claim 6 on which this claim depends. Kobrinsky further discloses: wherein the first epitaxial source or drain structures and the second epitaxial source or drain structures are each non-discrete epitaxial source or drain structures (Kobrinsky, ¶ [0139]). Re: Claim 10 (original), Kobrinsky, Kim, Huang and Xie disclose all the limitations of claim 6 on which this claim depends. Kobrinsky further discloses: wherein the first fin is over a first sub-fin (Fig 3, first fin 304 is above first sub-fin 305), and the second fin is over a second sub-fin (second fin 304 is above sub-fin 305). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kobrinsky (US 20200075770 A1) in view of Kim (US 20160293697 A1) further in view of Huang (US 20170069621 A1) and further in view of Xie (US 20230038116 A1) and further in view of Lu (US 11139247 B2) . Re: Claim 7 (original), Kobrinsky, Kim and Huang disclose all the limitations of claim 6 on which this claim depends. Kobrinsky, Kim, Huang and Xie are silent regarding: wherein the intervening dielectric structure comprises a pair of notches at the top surface of the intervening dielectric structure. However, Lu teaches intervening dielectric structure (fig 1B, dielectric structure 20) comprises a pair of notches at the top surface of the intervening dielectric structure (Fig 1B, recess #R1 formed by a discontinuity between surface 201 and 202 connected by surface 203 define a notch like recess within the top surface of the dielectric). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use Lu disclosed intervening dielectric structure comprises a pair of notches at the top surface of the intervening dielectric structure in the structure of Kobrinsky in order to achieve topographical and structural interface control between layers. Response to Arguments Regarding claims 6-10 rejected under 35 U.S.C. 112(b), applicant’s amendment has been fully considered. However, the amendment does not resolve the indefiniteness identified in the prior office action. The 35 U.S.C. 112(b) rejection is therefore maintained. Regarding claim 6-10 rejected under U.S.C. 112(a), applicant’s amendment has been fully considered. However, the amendment does not resolve the new matter issue, which introduces subject matter that lacks written description support in the originally filed disclosure. Applicant’s amendment further introduces new subject matter that lacks written description support in the originally filed disclosure. Hence, claims 6-10 are still rejected on new grounds under 35 U.S.C. 112(a). Applicant's arguments with respect to claim 6 have been considered but are moot because the arguments do not apply to the new ground(s) of rejection presented in this Office action, necessitated by the applicant's amendment. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 9:30am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
Read full office action

Prosecution Timeline

Show 1 earlier event
Nov 02, 2022
Response after Non-Final Action
Aug 14, 2025
Non-Final Rejection mailed — §103, §112
Nov 11, 2025
Response Filed
Jan 13, 2026
Final Rejection mailed — §103, §112
Mar 03, 2026
Response after Non-Final Action
Apr 13, 2026
Request for Continued Examination
Apr 20, 2026
Response after Non-Final Action
Jul 27, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 4 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 8 resolved cases by this examiner. Grant probability derived from career allowance rate.

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