Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1 and 6 in the Applicant’s response dated 8 June 2026. The claim amendments and the Applicant’s accompanying comments have been addressed below.
The Examiner acknowledges the amendments to withdrawn claims 11 and 16 in the Applicant’s response dated 8 June 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Guillaume Bouche (US 2019/0206795 A1; hereinafter “Bouche”) in view of Charles H. Wallace et al. (US 2019/0206728 A1; hereinafter “Wallace”) and in further view of Jhon-Jhy Liaw (US 2013/0272056 A1; hereinafter “Liaw”).
Regarding Claim 1, Bouche teaches an integrated circuit structure, comprising:
an interlayer dielectric layer (110, Fig. 10A, para [0028] describes a dielectric layer in an integrated circuit structure); and
a plurality of parallel conductive lines in the interlayer dielectric layer (160, 161 and 165, Fig. 10A, para [0028] describes metal lines formed of conductive material), the plurality of parallel conductive lines comprising a first conductive line and a second conductive line (161 and 160, Fig. 10A, para [0028] describes metal lines 160 and 161 wherein the first conductive line can be seen as line 161 at the top of Fig. 10A and the second conductive line 161 can be seen at the bottom of Fig. 10A (see annotated Fig. 10A (I))), the first conductive line comprising breaks therein with first and second dielectric plugs separating portions of the first conductive line (Fig. 10A, para [0028] describes wherein the metal lines 161 are formed in trenches of the dielectric layer 110 wherein the gaps between the first conductive line therefore comprise first and second dielectric plugs IP as shown in annotated Fig. 10A (II)), wherein one of the portions of the first conductive line is between the first dielectric plug and the second dielectric plug and has a first dimension (annotated Fig. 10A (II) depicts wherein a middle portion of the first conductive line is between the first and second dielectric plugs IP), and the second conductive line comprising first and second conductive line portions separated by an intervening conductive via structure (160 and 165, Fig. 10A, para [0028] describes a metal island 165 in between two conductive line portions 160, wherein the metal island is a portion of the metal via 184 and 182 as depicted in Fig. 13), the conductive via structure separated from the first and second conductive line portions (160 and 165, Fig. 10A, para [0028] describes a metal island in between two conductive lines that is electrically isolated from the metal lines by the dielectric layer), and the conductive via structure having a second dimension parallel with the first dimension (Lm, Fig. 10A, para [0028] describes a length of the metal island in a direction parallel with the first dimension (see annotated Fig. 10A (II) below)).
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Bouche fails to explicitly disclose wherein the second dimension is less than the first dimension.
However, Bouche teaches in the disclosure of their invention, wherein the metal island, which acts as part of a “super via” (para [0030]) and comprises a second dimension (Lm), is the result of a unique process for decreasing the size of metal lines to overcome existing fabrication limitations, wherein the resulting metal island is 15 nm or less (Bouche, para [0028]). The first metal line 161 is not a result of the unique fabrication process, resulting in a metal line that is larger than 15 nm. The disclosure further displays different metal lines 161 of varying length in comparison to one another in Fig. 10A.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first metal lines 161, and further reduce the size of the metal island via 165 below 15 nm, resulting in a second dimension that is less than the first dimension, in order to provide the advantage of overcoming limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features (Bouche, para [0002]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Bouche fails to explicitly disclose wherein the first and second dielectric plugs comprise a material different than the interlayer dielectric layer.
However, Wallace teaches a similar integrated circuit structure, wherein the first and second dielectric plugs comprise a material different than the interlayer dielectric layer (130, Fig. 1, para [0022] describes dielectric plugs 130 comprised between conductive lines 103 wherein dielectric plugs 130 are of a different material composition that is distinct from that of dielectric lines 110, wherein para [0019] describes dielectric lines 110 are comprised of a same composition as an interlayer dielectric layer 105).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bouche and Wallace to further disclose an integrated circuit structure wherein first and second dielectric plugs are comprised of a material different than the interlayer dielectric layer to provide the well-known advantage of enabling the plug material and trench material to be comprised of materials having different etch selectivity so that subsequent processing steps can be selective to either the plug material or the interlayer dielectric layer material.
The combination of Bouche and Wallace fail to explicitly disclose wherein the one of the portions of the first conductive line that is between the first dielectric plug and the second dielectric plug is overlapping with the conductive via structure along a horizontal axis, the horizontal axis orthogonal to the plurality of parallel conductive lines.
However, Liaw teaches a similar integrated circuit structure, wherein the one of the portions of the first conductive line (FCL3, Fig. 7, para [0061] describes landing pads 722, 724 and 726 of a first interconnect layer M1 forming a first conductive line FCL3) that is between the first dielectric plug and the second dielectric plug (405 and MPD, Fig. 4 and annotated Fig. 7 depict a middle portion MPD of the first conductive line FCL3 between breaks in the conductive line wherein a dielectric material as shown by 405 in Fig. 4 would be formed resulting in a first and second dielectric plug on a left and right side of the middle portion MPD) is overlapping with the conductive via structure along a horizontal axis (VS and Via1, annotated Fig. 7, para [0062] describes a via structure S formed on top of the first interconnect layer M1 and overlapping the middle portion MPD in a horizontal direction HD along the horizontal axis), the horizontal axis orthogonal to the plurality of parallel conductive lines (HD, annotated Fig. 7 depicts wherein the horizontal direction HD of the horizontal axis is orthogonal to the plurality of parallel conductive lines M1).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bouche and Wallace with Liaw to further disclose an integrated circuit structure wherein a conductive via structure overlaps a portion of a first parallel conductive line between a first dielectric plug and a second dielectric plug so as to provide the well-known advantage of enabling parallel conductive lines in a same interconnect layer to be coupled to a same power source line of an overlying interconnect layer while also maintaining electrical isolation from adjacent lines which are not connected to a power source line, enabling a high integration of device components and simplifying the manufacturing process.
Regarding Claim 2, the combination of Bouche, Wallace and Liaw discloses all the limitations of claim 1.
Bouche, Wallace and Liaw fail to explicitly disclose the integrated circuit structure of claim 1, wherein the first dimension is more than 50% greater than the second dimension.
However, Bouche teaches in the disclosure of their invention, wherein the metal island, which acts as part of a “super via” (Bouche, para [0030]), is the result of a unique process for decreasing the size of metal lines to overcome existing fabrication limitations, wherein the resulting metal island is 15 nm or less (Bouche, para [0028]). The first metal line 161 is not a result of the unique fabrication process, resulting in a metal line that is larger than 15 nm. The disclosure further displays different metal lines 161 of varying length in comparison to one another in Fig. 10A.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first metal lines 161, and further reduce the size of the metal island via 165 below 15 nm, resulting in a first dimension that is more than 50% greater than the second dimension, in order to provide the advantage of overcoming limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features (Bouche, para [0002]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Regarding Claim 3, the combination of Bouche, Wallace and Liaw discloses all the limitations of claim 1.
Bouche, Wallace and Liaw fail to explicitly disclose the integrated circuit structure of claim 1, wherein the first dimension is at least twice the second dimension.
However, Bouche teaches in the disclosure of their invention, wherein the metal island, which acts as part of a “super via” (Bouche, para [0030]), is the result of a unique process for decreasing the size of metal lines to overcome existing fabrication limitations, wherein the resulting metal island is 15 nm or less (Bouche, para [0028]). The first metal line 161 is not a result of the unique fabrication process, resulting in a metal line that is larger than 15 nm. The disclosure further displays different metal lines 161 of varying length in comparison to one another in Fig. 10A.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first metal lines 161, and further reduce the size of the metal island via 165 below 15 nm, resulting in a first dimension that is at least twice the second dimension, in order to provide the advantage of overcoming limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features (Bouche, para [0002]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Regarding Claim 4, the combination of Bouche, Wallace and Liaw teaches the integrated circuit structure of claim 1, wherein the conductive via structure is separated from the first and second conductive line portions by third and fourth dielectric plugs, respectively (Bouche, IP2, annotated Fig. 10A (III) below, wherein there exists breaks between the metal line 160 and the metal island via 165 that is filled with dielectric material creating third and fourth dielectric plugs IP2).
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Regarding Claim 5, the combination of Bouche, Wallace and Liaw teaches the integrated circuit structure of claim 1, wherein the conductive via structure is a pass through structure and is coupled to an underlying diffusion region in a substrate (Liaw, Via1, VCC and 406, Fig. 4 and annotated Fig. 7, para [0059] describes wherein the power source contact, coupled to the via structure, is coupled to the source region of a transistor wherein the conductive via structure including Via1 passes through intervening dielectric layers as shown in Fig. 4).
Regarding Claim 6, Bouche discloses an integrated circuit structure, comprising:
an interlayer dielectric layer (110, Fig. 10A, para [0028] describes a dielectric layer in an integrated circuit structure); and
a plurality of parallel conductive lines in the interlayer dielectric layer (161, Fig. 10A, para [0028] describes metal lines formed of conductive material), the plurality of parallel conductive lines comprising:
a first conductive line (161, Fig. 10A, para [0028] describes metal line 161 wherein the first conductive line can be seen as line 161 at the top of Fig. 10A (see annotated Fig. 10A (I) above)) comprising breaks therein with first and second dielectric plugs separating portions of the first conductive line, and wherein one of the portions of the first conductive line is between the first dielectric plug and the second dielectric plug and has a first dimension (IP from annotated Fig. 10A (I), Fig. 10A, para [0028] describes wherein the meal lines 161 are formed in trenches of the dielectric layer 110 wherein the gaps between the first conductive line therefore comprise dielectric plugs and there being a first dimension of the first conductive line between the first dielectric plug and the second dielectric plug (see annotated Fig. 10A (I) above));
a second conductive line (161, Fig. 10A, para [0028] a second conductive line below the first conductive line (see annotated Fig. 10A (IV) below))
a third conductive line comprising first and second conductive line portions separated by an intervening conductive via structure (160 and 165, Fig. 10A, para [0028] describes a metal island 165 in between two conductive line portions 160, wherein the metal island is a portion of the metal via 184 and 182 as depicted in Fig. 13 further forming a “super via” in combination as described in para [0030]), the conductive via structure separated from the first and second conductive line portions (160 and 165, Fig. 10A, para [0028] describes a metal island in between two conductive lines that is electrically isolated from the metal lines by the dielectric layer), and the conductive via structure having a second dimension parallel with the first dimension (Lm, Fig. 10A, para [0028] describes a length of the metal island in a direction parallel with the first dimension (see annotated Fig. 10A (II) above)).
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Bouche fails to explicitly disclose wherein the second dimension is less than the first dimension.
However, Bouche teaches in the disclosure of their invention, wherein the metal island, which acts as part of a “super via” (para [0030]) and comprises a second dimension (Lm), is the result of a unique process for decreasing the size of metal lines to overcome existing fabrication limitations, wherein the resulting metal island is 15 nm or less (Bouche, para [0028]). The first metal line 161 is not a result of the unique fabrication process, resulting in a metal line that is larger than 15 nm. The disclosure further displays different metal lines 161 of varying length in comparison to one another in Fig. 10A.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first metal lines 161, and further reduce the size of the metal island via 165 below 15 nm, resulting in a second dimension that is less than the first dimension, in order to provide the advantage of overcoming limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features (Bouche, para [0002]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Bouche fails to disclose wherein the first and second dielectric plugs comprise a material different than the interlayer dielectric layer, a fourth conductive line continuous along the third conductive line; and a fifth conductive line comprising breaks therein with third and fourth dielectric plugs separating portions of the fifth conductive line, wherein the third and fourth dielectric plugs comprise a material different than the interlayer dielectric layer, one of the portions between the third dielectric plug and the fourth dielectric plug and having the first dimension.
However, Wallace teaches a similar integrated circuit structure, wherein the first and second dielectric plugs comprise a material different than the interlayer dielectric layer (130, Fig. 1, para [0022] describes dielectric plugs 130 comprised between conductive lines 103 wherein dielectric plugs 130 are of a different material composition that is distinct from that of dielectric lines 110, wherein para [0019] describes dielectric lines 110 are comprised of a same composition as an interlayer dielectric layer 105),
a fourth conductive line (FCL, annotated Fig. 1 below) continuous along the third conductive line; and
a fifth conductive line (HCL, annotated Fig. 1 below) comprising breaks therein with third (130A, Fig. 1, para [0020] describes a dielectric plug 130A) and fourth dielectric plugs (130, Fig. 1, para [0020] describes a dielectric plug 130) separating portions of the fifth conductive line, wherein the third and fourth dielectric plugs comprise a material different than the interlayer dielectric layer (para [0022] describes dielectric plugs 130 comprised between conductive lines 103 wherein dielectric plugs 130 are of a different material composition that is distinct from that of dielectric lines 110, wherein para [0019] describes dielectric lines 110 are comprised of a same composition as an interlayer dielectric layer 105), one of the portions between the third dielectric plug and the fourth dielectric plug and having the first dimension (FD, annotated Fig. 1 below).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bouche and Wallace to further disclose an integrated circuit structure wherein first and second dielectric plugs are comprised of a material different than the interlayer dielectric layer to provide the well-known advantage of enabling the plug material and trench material to be comprised of materials having different etch selectivity so that subsequent processing steps can be selective to either the plug material or the trench material and to further disclose a fourth and fifth conductive line to provide the advantage of enabling the device to couple additional active devices to the integrated circuit (Wallace, para [0019]).
The combination of Bouche and Wallace fail to explicitly disclose wherein the second conductive line is continuous along the first conductive line; and wherein the one of the portions of the first conductive line that is between the first dielectric plug and the second dielectric plug is overlapping with the conductive via structure along a horizontal axis, the horizontal axis orthogonal to the plurality of parallel conductive lines.
However, Liaw teaches a similar integrated circuit structure, wherein the second conductive line is continuous along the first conductive line (712, annotated Fig. 7 depicts wherein a second conductive line 712 is continuous along the first conductive line FCL3); and
wherein the one of the portions of the first conductive line (FCL3, Fig. 7, para [0061] describes landing pads 722, 724 and 726 of a first interconnect layer M1 forming a first conductive line FCL3) that is between the first dielectric plug and the second dielectric plug (405 and MPD, Fig. 4 and annotated Fig. 7 depict a middle portion MPD of the first conductive line FCL3 between breaks in the conductive line wherein a dielectric material as shown by 405 in Fig. 4 would be formed resulting in a first and second dielectric plug on a left and right side of the middle portion MPD) is overlapping with the conductive via structure along a horizontal axis (VS and Via1, annotated Fig. 7, para [0062] describes a via structure S formed on top of the first interconnect layer M1 and overlapping the middle portion MPD in a horizontal direction HD along the horizontal axis), the horizontal axis orthogonal to the plurality of parallel conductive lines (HD, annotated Fig. 7 depicts wherein the horizontal direction HD of the horizontal axis is orthogonal to the plurality of parallel conductive lines M1).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bouche and Wallace with Liaw to further disclose an integrated circuit structure wherein a conductive via structure overlaps a portion of a first parallel conductive line between a first dielectric plug and a second dielectric plug so as to provide the well-known advantage of enabling parallel conductive lines in a same interconnect layer to be coupled to a same power source line of an overlying interconnect layer while also maintaining electrical isolation from adjacent lines which are not connected to a power source line, enabling a high integration of device components and simplifying the manufacturing process.
Regarding Claim 7, the combination of Bouche, Wallace and Liaw discloses all the limitations of claim 6.
Bouche, Wallace and Liaw fail to explicitly disclose the integrated circuit structure of claim 6, wherein the first dimension is more than 50% greater than the second dimension.
However, Bouche teaches in the disclosure of their invention, wherein the metal island, which acts as part of a “super via” (Bouche, para [0030]), is the result of a unique process for decreasing the size of metal lines to overcome existing fabrication limitations, wherein the resulting metal island is 15 nm or less. The first metal line 161 is not a result of the unique fabrication process, resulting in a metal line that is larger than 15 nm. The disclosure further displays different metal lines 161 of varying length in comparison to one another in Fig. 10A.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first metal lines 161, and further reduce the size of the metal island via 165 below 15 nm, resulting in a first dimension that is more than 50% greater than the second dimension, in order to provide the advantage of overcoming limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features (Bouche, para [0002]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Regarding Claim 8, the combination of Bouche, Wallace and Liaw discloses all the limitations of claim 6.
Bouche, Wallace and Liaw fail to explicitly disclose the integrated circuit structure of claim 6, wherein the first dimension is at least twice the second dimension.
However, Bouche teaches in the disclosure of their invention, wherein the metal island, which acts as part of a “super via” (Bouche, para [0030]), is the result of a unique process for decreasing the size of metal lines to overcome existing fabrication limitations, wherein the resulting metal island is 15 nm or less. The first metal line 161 is not a result of the unique fabrication process, resulting in a metal line that is larger than 15 nm. The disclosure further displays different metal lines 161 of varying length in comparison to one another in Fig. 10A.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first metal lines 161, and further reduce the size of the metal island via 165 below 15 nm, resulting in a first dimension that is at least twice the second dimension, in order to provide the advantage of overcoming limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features (Bouche, para [0002]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Regarding Claim 9, the combination of Bouche, Wallace and Liaw teaches the integrated circuit structure of claim 6, wherein the conductive via structure is separated from the first and second conductive line portions by fifth and sixth dielectric plugs, respectively (Bouche, IP2, annotated Fig. 10A (III) above, wherein there exists breaks between the metal line 160 and the metal island via 165 that is filled with dielectric material creating fifth and sixth dielectric plugs IP2).
Regarding Claim 10, the combination of Bouche, Wallace and Liaw teaches the integrated circuit structure of claim 6, wherein the conductive via structure is a pass through structure and is coupled to an underlying diffusion region in a substrate (Liaw, Via1, VCC and 406, Fig. 4 and annotated Fig. 7, para [0059] describes wherein the power source contact, coupled to the via structure, is coupled to the source region of a transistor wherein the conductive via structure including Via1 passes through intervening dielectric layers as shown in Fig. 4).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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