CTFR 17/555,401 CTFR 100312 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment An amendment filed on 05/19/2026 in response to the Office Action mailed on 02/27/2026 is being acknowledged and entered into the record. The present Final Rejection is made by taking into fully consideration all the amendments. Response to Arguments On page 6 of the remarks filed on 05/19/2026, with respect to independent claims 1, 11 and 18, Applicant argues that substituting Wu's layered conductive via's 407, 411 for Elsherbini's tall pillars would require (a) completely changing the build sequence and (b) violating the planarity and thin-film nature of Wu's RDL build-up and thus is not an obvious modification that would result in a reasonable likelihood of success, especially while preserving Wu's asymmetric dual- mold structure and reliability features. These arguments are fully considered but are not persuasive. A skilled artisan would have recognized that conductive pillars and conductive vias are functionally analogous interconnect structures and their integration sequence can be adapted using known semiconductor packaging techniques widely implemented in the RDL and package fabrication technology without changing the fundamental operation of the microelectronic assembly. As for the argument regarding violating the planarity and thin-film nature of Wu's RDL, obviousness does not require that the modified device of Wu preserve every manufacturing feature but rather whether or not a POSITA would have found it technically feasible to replace Wu’s conductive vias with Elsherbini’s pillars to obtain predictable results of establishing electrical connection with lower resistance. In fact, modifying Wu in view of Elsherbini represents a predictable variation yielding expected results. Therefore, the rejection of claim 1, 11 and 17 in view of Wu/Elsherbini is maintained. Furthermore, Claims 1 and 11 are directed to a product and not a process. According to MPEP § 2113 (I), the patentability of a product does not depend on its method of production and if the product is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). As such, the claimed product is similar to the product of Wu/Elsherbini regardless of the different manufacturing process as detailed below in the rejection. Therefore, the rejection of claims 1 and 11 in view of Wu/Elsherbini is maintained. On page 6 of the remarks filed on 05/19/2026, with respect to independent claims 1, 11 and 18, Applicant argues that the tall pillars of Elsherbini would interfere with (a) uniform dielectric deposition and planarization, (b) photo-lithography/etching steps across layers, and (c) CTE matching with molding compounds of Wu. These arguments are fully considered but are not persuasive. The existence of the above process challenges are typically considered engineering trade-offs and these alone do not render the modified microelectronic assembly of Wu inoperable. A modification is obvious if it yields predictable results and does not change the fundamental mode of operation of the microelectronic assembly of Wu. In fact, modifying Wu in view of Elsherbini represents a predictable variation yielding expected results. Therefore, the rejection of claims 1, 11 and 18 in view of Wu/Elsherbini is maintained. On page 7 of the remarks filed on 05/19/2026, with respect to independent claims 1, 11 and 18, Applicant argues that Wu already provides low-resistance vertical paths via the TIVs 107 and there is no need to add spanning pillars inside the RDL to lower the resistance. This argument is fully considered but is not persuasive. Even if the resistance of the vias of Wu is already acceptable, a POSITA would have recognized that the conductive pillars of Elsherbini provide larger conductive paths and would predictably further reduce interconnect resistance relative to conventional vias, thereby improving electrical performance. Therefore, the rejection of claims 1, 11 and 18 in view of Wu/Elsherbini is maintained. On page 7 of the remarks filed on 05/19/2026, with respect to independent claims 1, 11 and 18, Applicant argues that that Wu chose a multi- layer RDL for its specific benefits (redistribution, fan-out, mechanical integrity) and a POSITA would understand that modifying it as proposed would sacrifice those benefits for a marginal resistance gain and ultimately would not make the proposed modification. This argument is fully considered but is not persuasive. Any localized resistance gain arising from replacing multi-level vias in the RDL of Wu with the conductive pillars of Elsherbini would have been recognized by a POSITA as minor and outweighed by the predictable reduction in overall vertical interconnect resistance and would not affect the operability of the microelectronic assembly of Wu. Therefore, the rejection of claims 1, 11 and 18 in view of Wu/Elsherbini is maintained. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-5, 10, 11-13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1) . Regarding Claim 1 , Wu et al. discloses a microelectronic assembly, comprising: a first die 109 , having a first surface (see annotated Fig. 5 of Wu et al.: 109, paragraph 0022) and an opposing second surface with second conductive contacts 126 , in a first layer (see annotated Fig. 5 of Wu et al.: 126, first layer, paragraph 0021); a first material layer 405 on the first surface of the first die 109 (see annotated Fig. 5 of Wu et al.: 405, 109, paragraphs 0028, 0029), the first material layer 405 including silicon and nitrogen (paragraph 0029); a second material layer 409 on the first material layer 405 (see annotated Fig. 5 of Wu et al.: 405, 409, paragraphs 0028, 0031), the second material layer 409 including a photoimageable dielectric (paragraphs 0029, 0031); conductive vias 407 , 411 through the first and second material layers 405 , 409 , wherein each conductive via of the conductive vias 407 , 411 extends completely through the first and second material layers 405 , 409 and passes through said layers, wherein respective ones of the conductive vias 407 , 411 are electrically coupled to respective ones of the second conductive contacts 126 on the first die 109 (see annotated Fig. 5 of Wu et al.: 407, 411, 126, 109, paragraphs 0030, 0032); and a second die 501 , 503 in a second layer, wherein the second layer on the first layer, and wherein the second die 501 , 503 is electrically coupled to the second conductive contacts 126 on the first die 109 by the conductive vias 407 , 411 (see annotated Fig. 5 of Wu et al.: 501, 503, 407, 411, 126, 109, paragraph 0045). Wu et al. fails to explicitly teach the first surface of the first die 109 has first conductive contacts, wherein each conductive via of the conductive vias 407 , 411 passes through the said layers without passing through an intervening metallization layer. However, Elsherbini et al. teaches a microelectronic assembly, comprising a first die 114-1 , having a first surface with first conductive contacts 122 (Fig. 1A: 114-1, 122, paragraph 0024). Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have a first die having a first surface with first conductive contacts. Doing so would both mechanically and electrically couple the conductive contacts at the bottom surface of the first die to the conductive contacts at the top surface of the package substrate, as recognized by Elsherbini et al. (paragraph 0024). Elsherbini et al. further teaches conductive vias 152 passing through a first material layer 104-1 and second material layer 104-2 , wherein each conductive via 152 of the conductive vias 152 passes through the said layers 104-1, 104-2 without passing through an intervening metallization layer (see Fig. 1A: 152, 104-1, 104-2, paragraph 0024). Note that the left most conductive vias 152 in Fig. 1A pass through both the first material layer 104-1 and second material layer 104-2 and hence are interpreted as the conductive vias. Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have each conductive via of the conductive vias pass through the said layers without passing through an intervening metallization layer. Doing so would reduce interfacial contact resistance occurring due to intervening metal layers. PNG media_image1.png 721 1430 media_image1.png Greyscale Annotated Fig. 5 of Wu et al. (US 20210391317 A1) Regarding Claim 2 , Wu et al. fails to explicitly teach the microelectronic assembly of claim 1, wherein a thickness of the first material layer 405 is between 100 nanometers and 200 nanometers. However, Wu et al. does disclose that a thickness Th2 of the first material layer 405 is between 4000 nanometers and 12000 nanometers and that any suitable value for the thickness can be chosen (paragraph 0029). Furthermore, according to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Since the applicant has not provided any experimental evidence to demonstrate that the claimed range of thickness renders unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the thickness of the first material layer of Wu et al. through routine optimization to be between 100 nanometers and 200 nanometers. Note that the specification contains no disclosure of either the criticality of the claimed thickness range or any unexpected results arising from them. According to MPEP § 716.02 (d), to establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960). Regarding Claim 3 , Wu et al. teaches the microelectronic assembly of claim 1, wherein a thickness of the second material layer 409 is between 5 microns and 10 microns (paragraphs 0029, 0031). Note that Wu et al. teaches wherein a thickness of the second material layer is between 4 microns and 12 microns (paragraphs 0029, 0031). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Regarding Claim 4 , Wu et al. teaches the microelectronic assembly of claim 1, further comprising: a redistribution layer (RDL) 413 , 417 between the second material layer 409 and the second layer (see annotated Fig. 5 of Wu et al.: 413, 417, 409, paragraph 0028). Regarding Claim 5 , Wu et al. teaches the microelectronic assembly of claim 1, further comprising: a conductive pillar 107 in the first layer, wherein the conductive pillar 107 is electrically coupled to a respective one of the conductive vias 407 , 411 and to the second die 501 , 503 by the conductive via 407 , 411 (see annotated Fig. 5 of Wu et al.: 107, 407, 411, 501, 503, paragraph 0019). Regarding Claim 10 , Wu et al. fails to teach the microelectronic assembly of claim 1, wherein a pitch of the second conductive contacts 126 of the first die 109 is between 20 microns and 40 microns. Elsherbini et al., in a different embodiment, teaches wherein a pitch of the second conductive contacts 1636 of the first die 1600 is between 5 microns and 100 microns (paragraph 0143). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that according to paragraph 0143, the interconnect structure in layer 1610 right below the second conductive contacts 1636 of Fig. 9 has a pitch of between 5 microns and 100 microns. Further from Fig. 9, it is evident that the second conductive contacts 1636 have a similar pitch to that of the interconnect structure below it, and therefore a person of ordinary skill in the art would have recognized that the second conductive contacts 1636 would also have a pitch of between 5 microns and 100 microns. Regarding Claim 11 , Wu et al. discloses a microelectronic assembly, comprising: a first die 109 , having a first surface (see annotated Fig. 5 of Wu et al.: 109, paragraph 0022) and an opposing second surface with second conductive contacts 126 , in a first layer (see annotated Fig. 5 of Wu et al.: 126, first layer, paragraph 0021); a first material layer 405 on the first surface of the first die 109 (see annotated Fig. 5 of Wu et al.: 405, 109, paragraphs 0028, 0029), the first material layer 405 including silicon and nitrogen (paragraph 0029); a second material layer 409 on the first material layer 405 (see annotated Fig. 5 of Wu et al.: 405, 409, paragraphs 0028, 0031), the second material layer 405 including a dielectric (paragraphs 0029, 0031); conductive vias 407 , 411 through the first and second material layers 405 , 409 , wherein each conductive via of the conductive vias 407 , 411 extends completely through the first and second material layers 405 , 409 and passes through said layers 405, 409 , wherein respective ones of the conductive vias 407 , 411 are electrically coupled to respective ones of the second conductive contacts 126 on the first die 109 (see annotated Fig. 5 of Wu et al.: 407, 411, 126, 109, paragraphs 0030, 0032); and a second die 501 , 503 in a second layer, wherein the second layer is on the first layer, and wherein the second die 501 , 503 is electrically coupled to the second conductive contacts 126 on the first die 109 by the conductive vias 407 , 411 (see annotated Fig. 5 of Wu et al.: 501, 503, 407, 411, 126, 109, paragraph 0045). Wu et al. fails to teach: the first surface of the first die 109 has first conductive contacts wherein each conductive via of the conductive vias 407 , 411 passes through the said layers without passing through an intervening metallization layer a liner between the first and second material layers and the conductive vias However, Elsherbini et al. teaches a microelectronic assembly, comprising a first die 114-1 , having a first surface with first conductive contacts 122 (Fig. 1A: 114-1, 122, paragraph 0024). Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have a first die having a first surface with first conductive contacts. Doing so would both mechanically and electrically couple the conductive contacts at the bottom surface of the first die to the conductive contacts at the top surface of the package substrate, as recognized by Elsherbini et al. (paragraph 0024). Elsherbini et al. further teaches a liner bordering the conductive vias 152 (Fig. 1A, paragraph 0044). Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al. and Elsherbini et al. to form a liner bordering the conductive vias of Wu et al. Doing so would enable the liners to serve as adhesion liners or barrier liners as recognized by Elsherbini et al. (paragraph 0044). Further, a person of ordinary skill in the art would have recognized that when the liner of Elsherbini et al. is disposed to border the conductive vias of Wu et al., the liner will be between the first and second material layers and the conductive vias. Elsherbini et al. further teaches conductive vias 152 passing through a first material layer 104-1 and second material layer 104-2 , wherein each conductive via 152 of the conductive vias 152 passes through the said layers 104-1, 104-2 without passing through an intervening metallization layer (see Fig. 1A: 152, 104-1, 104-2, paragraph 0024). Note that the left most conductive vias 152 in Fig. 1A pass through both the first material layer 104-1 and second material layer 104-2 and hence are interpreted as the conductive vias. Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have each conductive via of the conductive vias pass through the said layers without passing through an intervening metallization layer. Doing so would reduce interfacial contact resistance occurring due to intervening metal layers. Regarding Claim 12 , Wu et al. fails to explicitly teach the microelectronic assembly of claim 11, wherein a thickness of the first material layer 405 is between 100 nanometers and 200 nanometers. However, Wu et al. does disclose that a thickness Th2 of the first material layer 405 is between 4000 nanometers and 12000 nanometers and that any suitable value for the thickness can be chosen (paragraph 0029). Furthermore, according to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Since the applicant has not provided any experimental evidence to demonstrate that the claimed range of thickness renders unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the thickness of the first material layer of Wu et al. through routine optimization to be between 100 nanometers and 200 nanometers. Note that the specification contains no disclosure of either the criticality of the claimed thickness range or any unexpected results arising from them. According to MPEP § 716.02 (d), to establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960). Regarding Claim 13 , Wu et al. teaches the microelectronic assembly of claim 11, wherein a thickness of the second material layer 409 is between 5 microns and 10 microns (paragraphs 0029, 0031). Note that Wu et al. teaches wherein a thickness of the second material layer is between 4 microns and 12 microns (paragraphs 0029, 0031). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Regarding Claim 17 , Wu et al. teaches the microelectronic assembly of claim 11, wherein the first die 109 includes memory, a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, a bridge die, or a security encryptor and the second die 501 , 503 includes a processing die (paragraphs 0020, 0045). Regarding Claim 18 , Wu et al. teaches a method of manufacturing a microelectronic assembly, comprising: attaching a first die 109 to a carrier 101 (Fig. 2: 109, 101, paragraphs 005, 0020), wherein the first die 109 includes a first surface and an opposing second surface with second conductive contacts 126 , forming a conductive pillar 107 on the carrier 101 (Fig. 1: 107, 101, paragraph 0019); forming an insulating material 301 around the first die 109 and the conductive pillar 107 (Fig. 3: 301, 109, 107, paragraph 0027); forming a first material layer 405 on the insulating material 301 , wherein the first material layer 405 includes silicon and nitrogen (Fig. 4A: 405, 301, paragraph 0029); forming a second material layer 409 on the first material layer 405 , wherein the second material layer includes a dielectric material (Fig. 4A: 405, 409, paragraph 0029, 0031); forming conductive vias 407 , 411 through the first and second material layers 405, 409 , wherein each conductive via of the conductive vias 407 , 411 extends completely through the first and second material layers 405 , 409 , and electrically coupling respective ones of the conductive vias 407 , 411 to respective ones of the second conductive contacts 126 and the conductive pillar 107 (Fig. 4A: 405, 407, 409, 411, annotated Fig. 5 of Wu et al.:126, paragraphs 0030, 0032); and electrically coupling a second die 501 , 503 to the second conductive contacts 126 at the second surface of the first die 109 and to the conductive pillar 107 through the conductive vias 407 , 411 (see annotated Fig. 5 of Wu et al.: 501, 503, 126, 109, 107, 407, 411, paragraph 0045). Wu et al. fails to explicitly teach wherein the first die 109 includes a first surface with first conductive contacts and wherein the first die 109 is attached to the carrier 101 with the first conductive contacts facing the carrier 101 wherein each conductive via of the conductive vias 407 , 411 extends completely through the first and second material layers 405 , 409 without passing through an intervening metallization layer However, Elsherbini et al. teaches a method of manufacturing a microelectronic assembly, wherein the first die 114-1 includes a first surface with first conductive contacts 122 and wherein the first die 114-1 is attached to the carrier 102 with the first conductive contacts 122 facing the carrier 101 . Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to come up with the claimed invention as claimed in Claim 18. Doing so would both mechanically and electrically couple the conductive contacts at the bottom surface of the first die to the conductive contacts at the top surface of the package substrate, as recognized by Elsherbini et al. (paragraph 0024). Elsherbini et al. further teaches conductive vias 152 passing through a first material layer 104-1 and second material layer 104-2 , wherein each conductive via 152 of the conductive vias 152 extends completely through the first and second material layers 104-1, 104-2 without passing through an intervening metallization layer (see Fig. 1A: 152, 104-1, 104-2, paragraph 0024). Note that the left most conductive vias 152 in Fig. 1A pass through both the first material layer 104-1 and second material layer 104-2 and hence are interpreted as the conductive vias. Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have each conductive via of the conductive vias extend completely through the first and second material layers without passing through an intervening metallization layer. Doing so would reduce interfacial contact resistance occurring due to the presence of intervening metal layers . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 1 above, further in view of Zhang et al. (US 20210159248 A1) . Regarding Claim 8 , Wu et al. fails to teach the microelectronic assembly of claim 1, further comprising: a liner between the first and second material layers and the conductive vias, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. While Elsherbini et al. fails to explicitly teach a liner between the first and second material layers and the conductive vias, it does teach that the conductive vias 152 maybe bordered by liner materials (Fig. 1A, paragraph 0044). Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al. and Elsherbini et al. to form a liner bordering the conductive vias of Wu et al. Doing so would enable the liner to serve as adhesion layers or diffusion barriers as recognized by Elsherbini et al. (paragraph 0044). Further, a person of ordinary skill in the art would have recognized that when the liner of Elsherbini et al. is disposed to border the conductive vias of Wu et al., the liner will be between the first and second material layers and the conductive vias. The combination of Wu et al. and Elsherbini et al. fails to teach wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. However, Zhang et al. discloses a microelectronic assembly, comprising a liner formed in the conductive vias 79 , wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium (Fig. 12: 79, paragraph 0093). Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Zhang et al. to have the liner include titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. Doing so would enable the liner to serve as diffusion barriers as recognized by Elsherbini et al. (paragraph 0044) and Zhang et al. (paragraph 0093) . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 8 above, further in view of Zhang et al. (US 20210159248 A1) . Regarding Claim 9 , the combination of Wu et al., Elsherbini et al., and Zhang et al. fails to explicitly teach the microelectronic assembly of claim 8, wherein a thickness of the liner is between 25 nanometers and 75 nanometers. However, Zhang et al. discloses a microelectronic assembly, comprising a liner formed in the conductive vias 79 , wherein a thickness of the liner is between 1 nanometers and 5 nanometers and that a greater thickness may also be employed (paragraph 0093). Furthermore, according to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Since the applicant has not provided any experimental evidence to demonstrate that the claimed range of thickness renders unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the thickness of the liner through routine optimization to be between 25 nanometers and 75 nanometers. Note that the specification contains no disclosure of either the criticality of the claimed thickness range or any unexpected results arising from them. According to MPEP § 716.02 (d), to establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960) . 07-21-aia AIA Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 11 above, further in view of Zhang et al. (US 20210159248 A1) . Regarding Claim 16, the combination of Wu et al. and Elsherbini et al. fails to teach the microelectronic assembly of claim 11, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. However, Zhang et al. discloses a microelectronic assembly, comprising a liner formed in the conductive vias 79 , wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium (Fig. 12: 79, paragraph 0093). Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Zhang et al. to have the liner include titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. Doing so would enable the liner to serve as diffusion barriers as recognized by Elsherbini et al. (paragraph 0044) and Zhang et al. (paragraph 0093) . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 18 above, further in view of Zhang et al. (US 20210159248 A1) . Regarding Claim 19, the combination of Wu et al. and Elsherbini et al. fails to teach the method of claim 18, further comprising: forming a liner between the first and second material layers and the conductive vias, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. While Elsherbini et al. fails to explicitly teach forming a liner between the first and second material layers and the conductive vias, it does teach that the conductive vias 152 maybe bordered by liner materials (Fig. 1A, paragraph 0044). Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al. and Elsherbini et al. to form a liner bordering the conductive vias of Wu et al. Doing so would enable the liner to serve as adhesion layers or diffusion barriers as recognized by Elsherbini et al. (paragraph 0044). Further, a person of ordinary skill in the art would have recognized that when the liner of Elsherbini et al. is disposed to border the conductive vias of Wu et al., the liner will be formed between the first and second material layers and the conductive vias. The combination of Wu et al. and Elsherbini et al. fails to teach wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. However, Zhang et al. discloses a method of manufacturing a microelectronic assembly, comprising forming a liner in the conductive vias 79 , wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium (Fig. 12: 79, paragraph 0093). Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Zhang et al. to have the liner include titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. Doing so would enable the liner to serve as diffusion barriers as recognized by Elsherbini et al. (paragraph 0044) and Zhang et al. (paragraph 0093) . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 18 above, further in view of Darmawikarta et al. (US 20190371621 A1) . The combination of Wu et al. and Elsherbini et al. fails to teach the method of claim 18, wherein a diameter of an individual conductive via is between 1 micron and 10 microns. However, Darmawikarta et al. teaches a method of manufacturing a microelectronic assembly comprising conductive vias, wherein a diameter of an individual conductive via is less than 20 microns (abstract). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Darmawikarta et al. to have a diameter of an individual conductive via between 1 micron and 10 microns. Doing so would yield microelectronic assemblies with high interconnect density without significantly impacting the mechanical and electrical properties, as recognized by Darmawikarta et al. (paragraph 0016). Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is (571) 272-1587 . The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 05/29/2026 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 Application/Control Number: 17/555,401 Page 2 Art Unit: 2817 Application/Control Number: 17/555,401 Page 3 Art Unit: 2817
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