DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/1 has been entered.
Response to Amendment
An amendment filed on 11/17/2025 in response to the Office Action mailed on 09/30/2025 is being acknowledged and entered into the record. The present Non-Final Rejection is made by taking into fully consideration all the amendments.
Response to Arguments
With regards to amended claims 1, 11 and 18, on page 6 of the remarks filed on 11/17/2025, Applicant argues that Wu's stacked conductive vias 407 and 411 pass through a metallization layer (i.e., the metallization layer between first material layer 405 and second material layer 409) and therefore are not the claimed conductive vias. This argument is fully considered but is not persuasive. The previously applied prior art reference Elsherbini teaches the above limitation. i.e., conductive vias 152 passing through a first material layer 104-1 and second material layer 104-2, wherein each conductive via 152 of the conductive vias 152 passes through the said layers 104-1, 104-2 without passing through an intervening metallization layer (see Fig. 1A: 152, 104-1, 104-2, paragraph 0024). Thus, the rejection of independent claims 1, 11 and 18 in view of Wu/Elsherbini is maintained. The rejection of the dependent claims are also maintained and the previously withdrawn claims remain withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10, 11-13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1).
Regarding Claim 1, Wu et al. discloses a microelectronic assembly, comprising:
a first die 109, having a first surface (see annotated Fig. 5 of Wu et al.: 109, paragraph 0022)
and an opposing second surface with second conductive contacts 126, in a first layer (see annotated Fig. 5 of Wu et al.: 126, first layer, paragraph 0021);
a first material layer 405 on the first surface of the first die 109 (see annotated Fig. 5 of Wu et al.: 405, 109, paragraphs 0028, 0029),
the first material layer 405 including silicon and nitrogen (paragraph 0029);
a second material layer 409 on the first material layer 405 (see annotated Fig. 5 of Wu et al.: 405, 409, paragraphs 0028, 0031),
the second material layer 409 including a photoimageable dielectric (paragraphs 0029, 0031);
conductive vias 407, 411 through the first and second material layers 405, 409, wherein each conductive via of the conductive vias 407, 411 extends completely through the first and second material layers 405, 409 and passes through said layers, wherein respective ones of the conductive vias 407, 411 are electrically coupled to respective ones of the second conductive contacts 126 on the first die 109 (see annotated Fig. 5 of Wu et al.: 407, 411, 126, 109, paragraphs 0030, 0032);
and a second die 501, 503 in a second layer, wherein the second layer on the first layer, and wherein the second die 501, 503 is electrically coupled to the second conductive contacts 126 on the first die 109 by the conductive vias 407, 411 (see annotated Fig. 5 of Wu et al.: 501, 503, 407, 411, 126, 109, paragraph 0045).
Wu et al. fails to explicitly teach the first surface of the first die 109 has first conductive contacts, wherein each conductive via of the conductive vias 407, 411 passes through the said layers without passing through an intervening metallization layer.
However, Elsherbini et al. teaches a microelectronic assembly, comprising a first die 114-1, having a first surface with first conductive contacts 122 (Fig. 1A: 114-1, 122, paragraph 0024).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have a first die having a first surface with first conductive contacts. Doing so would both mechanically and electrically couple the conductive contacts at the bottom surface of the first die to the conductive contacts at the top surface of the package substrate, as recognized by Elsherbini et al. (paragraph 0024).
Elsherbini et al. further teaches conductive vias 152 passing through a first material layer 104-1 and second material layer 104-2, wherein each conductive via 152 of the conductive vias 152 passes through the said layers 104-1, 104-2 without passing through an intervening metallization layer (see Fig. 1A: 152, 104-1, 104-2, paragraph 0024). Note that the left most conductive vias 152 in Fig. 1A pass through both the first material layer 104-1 and second material layer 104-2 and hence are interpreted as the conductive vias.
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have each conductive via of the conductive vias pass through the said layers without passing through an intervening metallization layer. Doing so would reduce interfacial contact resistance occurring due to intervening metal layers.
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Annotated Fig. 5 of Wu et al. (US 20210391317 A1)
Regarding Claim 2, Wu et al. fails to explicitly teach the microelectronic assembly of claim 1, wherein a thickness of the first material layer 405 is between 100 nanometers and 200 nanometers.
However, Wu et al. does disclose that a thickness Th2 of the first material layer 405 is between 4000 nanometers and 12000 nanometers and that any suitable value for the thickness can be chosen (paragraph 0029). Furthermore, according to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Since the applicant has not provided any experimental evidence to demonstrate that the claimed range of thickness renders unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the thickness of the first material layer of Wu et al. through routine optimization to be between 100 nanometers and 200 nanometers.
Note that the specification contains no disclosure of either the criticality of the claimed thickness range or any unexpected results arising from them. According to MPEP § 716.02 (d), to establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960).
Regarding Claim 3, Wu et al. teaches the microelectronic assembly of claim 1, wherein a thickness of the second material layer 409 is between 5 microns and 10 microns (paragraphs 0029, 0031).
Note that Wu et al. teaches wherein a thickness of the second material layer is between 4 microns and 12 microns (paragraphs 0029, 0031). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding Claim 4, Wu et al. teaches the microelectronic assembly of claim 1, further comprising: a redistribution layer (RDL) 413, 417 between the second material layer 409 and the second layer (see annotated Fig. 5 of Wu et al.: 413, 417, 409, paragraph 0028).
Regarding Claim 5, Wu et al. teaches the microelectronic assembly of claim 1, further comprising: a conductive pillar 107 in the first layer, wherein the conductive pillar 107 is electrically coupled to a respective one of the conductive vias 407, 411 and to the second die 501, 503 by the conductive via 407, 411 (see annotated Fig. 5 of Wu et al.: 107, 407, 411, 501, 503, paragraph 0019).
Regarding Claim 10, Wu et al. fails to teach the microelectronic assembly of claim 1, wherein a pitch of the second conductive contacts 126 of the first die 109 is between 20 microns and 40 microns.
Elsherbini et al., in a different embodiment, teaches wherein a pitch of the second conductive contacts 1636 of the first die 1600 is between 5 microns and 100 microns (paragraph 0143). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Note that according to paragraph 0143, the interconnect structure in layer 1610 right below the second conductive contacts 1636 of Fig. 9 has a pitch of between 5 microns and 100 microns. Further from Fig. 9, it is evident that the second conductive contacts 1636 have a similar pitch to that of the interconnect structure below it, and therefore a person of ordinary skill in the art would have recognized that the second conductive contacts 1636 would also have a pitch of between 5 microns and 100 microns.
Regarding Claim 11, Wu et al. discloses a microelectronic assembly, comprising:
a first die 109, having a first surface (see annotated Fig. 5 of Wu et al.: 109, paragraph 0022)
and an opposing second surface with second conductive contacts 126, in a first layer (see annotated Fig. 5 of Wu et al.: 126, first layer, paragraph 0021);
a first material layer 405 on the first surface of the first die 109 (see annotated Fig. 5 of Wu et al.: 405, 109, paragraphs 0028, 0029),
the first material layer 405 including silicon and nitrogen (paragraph 0029);
a second material layer 409 on the first material layer 405 (see annotated Fig. 5 of Wu et al.: 405, 409, paragraphs 0028, 0031),
the second material layer 405 including a dielectric (paragraphs 0029, 0031);
conductive vias 407, 411 through the first and second material layers 405, 409, wherein each conductive via of the conductive vias 407, 411 extends completely through the first and second material layers 405, 409 and passes through said layers 405, 409, wherein respective ones of the conductive vias 407, 411 are electrically coupled to respective ones of the second conductive contacts 126 on the first die 109 (see annotated Fig. 5 of Wu et al.: 407, 411, 126, 109, paragraphs 0030, 0032);
and a second die 501, 503 in a second layer, wherein the second layer is on the first layer, and wherein the second die 501, 503 is electrically coupled to the second conductive contacts 126 on the first die 109 by the conductive vias 407, 411 (see annotated Fig. 5 of Wu et al.: 501, 503, 407, 411, 126, 109, paragraph 0045).
Wu et al. fails to teach:
the first surface of the first die 109 has first conductive contacts
wherein each conductive via of the conductive vias 407, 411 passes through the said layers without passing through an intervening metallization layer
a liner between the first and second material layers and the conductive vias
However, Elsherbini et al. teaches a microelectronic assembly, comprising a first die 114-1, having a first surface with first conductive contacts 122 (Fig. 1A: 114-1, 122, paragraph 0024).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have a first die having a first surface with first conductive contacts. Doing so would both mechanically and electrically couple the conductive contacts at the bottom surface of the first die to the conductive contacts at the top surface of the package substrate, as recognized by Elsherbini et al. (paragraph 0024).
Elsherbini et al. further teaches a liner bordering the conductive vias 152 (Fig. 1A, paragraph 0044).
Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al. and Elsherbini et al. to form a liner bordering the conductive vias of Wu et al. Doing so would enable the liners to serve as adhesion liners or barrier liners as recognized by Elsherbini et al. (paragraph 0044). Further, a person of ordinary skill in the art would have recognized that when the liner of Elsherbini et al. is disposed to border the conductive vias of Wu et al., the liner will be between the first and second material layers and the conductive vias.
Elsherbini et al. further teaches conductive vias 152 passing through a first material layer 104-1 and second material layer 104-2, wherein each conductive via 152 of the conductive vias 152 passes through the said layers 104-1, 104-2 without passing through an intervening metallization layer (see Fig. 1A: 152, 104-1, 104-2, paragraph 0024). Note that the left most conductive vias 152 in Fig. 1A pass through both the first material layer 104-1 and second material layer 104-2 and hence are interpreted as the conductive vias.
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have each conductive via of the conductive vias pass through the said layers without passing through an intervening metallization layer. Doing so would reduce interfacial contact resistance occurring due to intervening metal layers.
Regarding Claim 12, Wu et al. fails to explicitly teach the microelectronic assembly of claim 11, wherein a thickness of the first material layer 405 is between 100 nanometers and 200 nanometers.
However, Wu et al. does disclose that a thickness Th2 of the first material layer 405 is between 4000 nanometers and 12000 nanometers and that any suitable value for the thickness can be chosen (paragraph 0029). Furthermore, according to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Since the applicant has not provided any experimental evidence to demonstrate that the claimed range of thickness renders unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the thickness of the first material layer of Wu et al. through routine optimization to be between 100 nanometers and 200 nanometers.
Note that the specification contains no disclosure of either the criticality of the claimed thickness range or any unexpected results arising from them. According to MPEP § 716.02 (d), to establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960).
Regarding Claim 13, Wu et al. teaches the microelectronic assembly of claim 11, wherein a thickness of the second material layer 409 is between 5 microns and 10 microns (paragraphs 0029, 0031).
Note that Wu et al. teaches wherein a thickness of the second material layer is between 4 microns and 12 microns (paragraphs 0029, 0031). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding Claim 17, Wu et al. teaches the microelectronic assembly of claim 11, wherein the first die 109 includes memory, a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, a bridge die, or a security encryptor and the second die 501, 503 includes a processing die (paragraphs 0020, 0045).
Regarding Claim 18, Wu et al. teaches a method of manufacturing a microelectronic assembly, comprising:
attaching a first die 109 to a carrier 101 (Fig. 2: 109, 101, paragraphs 005, 0020),
wherein the first die 109 includes a first surface and an opposing second surface with second conductive contacts 126,
forming a conductive pillar 107 on the carrier 101 (Fig. 1: 107, 101, paragraph 0019);
forming an insulating material 301 around the first die 109 and the conductive pillar 107 (Fig. 3: 301, 109, 107, paragraph 0027);
forming a first material layer 405 on the insulating material 301, wherein the first material layer 405 includes silicon and nitrogen (Fig. 4A: 405, 301, paragraph 0029);
forming a second material layer 409 on the first material layer 405, wherein the second material layer includes a dielectric material (Fig. 4A: 405, 409, paragraph 0029, 0031);
forming conductive vias 407, 411 through the first and second material layers 405, 409, wherein each conductive via of the conductive vias 407, 411 extends completely through the first and second material layers 405, 409, and electrically coupling respective ones of the conductive vias 407, 411 to respective ones of the second conductive contacts 126 and the conductive pillar 107 (Fig. 4A: 405, 407, 409, 411, annotated Fig. 5 of Wu et al.:126, paragraphs 0030, 0032);
and electrically coupling a second die 501, 503 to the second conductive contacts 126 at the second surface of the first die 109 and to the conductive pillar 107 through the conductive vias 407, 411 (see annotated Fig. 5 of Wu et al.: 501, 503, 126, 109, 107, 407, 411, paragraph 0045).
Wu et al. fails to explicitly teach
wherein the first die 109 includes a first surface with first conductive contacts and wherein the first die 109 is attached to the carrier 101 with the first conductive contacts facing the carrier 101
wherein each conductive via of the conductive vias 407, 411 extends completely through the first and second material layers 405, 409 without passing through an intervening metallization layer
However, Elsherbini et al. teaches a method of manufacturing a microelectronic assembly, wherein the first die 114-1 includes a first surface with first conductive contacts 122 and wherein the first die 114-1 is attached to the carrier 102 with the first conductive contacts 122 facing the carrier 101.
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to come up with the claimed invention as claimed in Claim 18. Doing so would both mechanically and electrically couple the conductive contacts at the bottom surface of the first die to the conductive contacts at the top surface of the package substrate, as recognized by Elsherbini et al. (paragraph 0024).
Elsherbini et al. further teaches conductive vias 152 passing through a first material layer 104-1 and second material layer 104-2, wherein each conductive via 152 of the conductive vias 152 extends completely through the first and second material layers 104-1, 104-2 without passing through an intervening metallization layer (see Fig. 1A: 152, 104-1, 104-2, paragraph 0024). Note that the left most conductive vias 152 in Fig. 1A pass through both the first material layer 104-1 and second material layer 104-2 and hence are interpreted as the conductive vias.
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Wu et al. with the teachings of Elsherbini et al. to have each conductive via of the conductive vias extend completely through the first and second material layers without passing through an intervening metallization layer. Doing so would reduce interfacial contact resistance occurring due to the presence of intervening metal layers.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 1 above, further in view of Zhang et al. (US 20210159248 A1).
Regarding Claim 8, Wu et al. fails to teach the microelectronic assembly of claim 1, further comprising: a liner between the first and second material layers and the conductive vias, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium.
While Elsherbini et al. fails to explicitly teach a liner between the first and second material layers and the conductive vias, it does teach that the conductive vias 152 maybe bordered by liner materials (Fig. 1A, paragraph 0044).
Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al. and Elsherbini et al. to form a liner bordering the conductive vias of Wu et al. Doing so would enable the liner to serve as adhesion layers or diffusion barriers as recognized by Elsherbini et al. (paragraph 0044). Further, a person of ordinary skill in the art would have recognized that when the liner of Elsherbini et al. is disposed to border the conductive vias of Wu et al., the liner will be between the first and second material layers and the conductive vias.
The combination of Wu et al. and Elsherbini et al. fails to teach wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium.
However, Zhang et al. discloses a microelectronic assembly, comprising a liner formed in the conductive vias 79, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium (Fig. 12: 79, paragraph 0093).
Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Zhang et al. to have the liner include titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. Doing so would enable the liner to serve as diffusion barriers as recognized by Elsherbini et al. (paragraph 0044) and Zhang et al. (paragraph 0093).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 8 above, further in view of Zhang et al. (US 20210159248 A1).
Regarding Claim 9, the combination of Wu et al., Elsherbini et al., and Zhang et al. fails to explicitly teach the microelectronic assembly of claim 8, wherein a thickness of the liner is between 25 nanometers and 75 nanometers.
However, Zhang et al. discloses a microelectronic assembly, comprising a liner formed in the conductive vias 79, wherein a thickness of the liner is between 1 nanometers and 5 nanometers and that a greater thickness may also be employed (paragraph 0093). Furthermore, according to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Since the applicant has not provided any experimental evidence to demonstrate that the claimed range of thickness renders unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the thickness of the liner through routine optimization to be between 25 nanometers and 75 nanometers.
Note that the specification contains no disclosure of either the criticality of the claimed thickness range or any unexpected results arising from them. According to MPEP § 716.02 (d), to establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 11 above, further in view of Zhang et al. (US 20210159248 A1).
Regarding Claim 16, the combination of Wu et al. and Elsherbini et al. fails to teach the microelectronic assembly of claim 11, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium.
However, Zhang et al. discloses a microelectronic assembly, comprising a liner formed in the conductive vias 79, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium (Fig. 12: 79, paragraph 0093).
Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Zhang et al. to have the liner include titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. Doing so would enable the liner to serve as diffusion barriers as recognized by Elsherbini et al. (paragraph 0044) and Zhang et al. (paragraph 0093).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 18 above, further in view of Zhang et al. (US 20210159248 A1).
Regarding Claim 19, the combination of Wu et al. and Elsherbini et al. fails to teach the method of claim 18, further comprising: forming a liner between the first and second material layers and the conductive vias, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium.
While Elsherbini et al. fails to explicitly teach forming a liner between the first and second material layers and the conductive vias, it does teach that the conductive vias 152 maybe bordered by liner materials (Fig. 1A, paragraph 0044).
Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al. and Elsherbini et al. to form a liner bordering the conductive vias of Wu et al. Doing so would enable the liner to serve as adhesion layers or diffusion barriers as recognized by Elsherbini et al. (paragraph 0044). Further, a person of ordinary skill in the art would have recognized that when the liner of Elsherbini et al. is disposed to border the conductive vias of Wu et al., the liner will be formed between the first and second material layers and the conductive vias.
The combination of Wu et al. and Elsherbini et al. fails to teach wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium.
However, Zhang et al. discloses a method of manufacturing a microelectronic assembly, comprising forming a liner in the conductive vias 79, wherein the liner includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium (Fig. 12: 79, paragraph 0093).
Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Zhang et al. to have the liner include titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, or ruthenium. Doing so would enable the liner to serve as diffusion barriers as recognized by Elsherbini et al. (paragraph 0044) and Zhang et al. (paragraph 0093).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210391317 A1), in view of Elsherbini et al. (US 20190385977 A1), as applied to Claim 18 above, further in view of Darmawikarta et al. (US 20190371621 A1).
The combination of Wu et al. and Elsherbini et al. fails to teach the method of claim 18, wherein a diameter of an individual conductive via is between 1 micron and 10 microns.
However, Darmawikarta et al. teaches a method of manufacturing a microelectronic assembly comprising conductive vias, wherein a diameter of an individual conductive via is less than 20 microns (abstract). According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, a person of ordinary skill in the art would have combined the teachings of Wu et al., Elsherbini et al., and Darmawikarta et al. to have a diameter of an individual conductive via between 1 micron and 10 microns. Doing so would yield microelectronic assemblies with high interconnect density without significantly impacting the mechanical and electrical properties, as recognized by Darmawikarta et al. (paragraph 0016).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is (571) 272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 02/19/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 25, 2026