DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 10/29/2025, responding to the Office action mailed
on 10/21/2025, has been entered into the record. The present Office action is made
with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Claim Objections
Claims 1, 13, 18 is objected to because of the following informalities:
Claims 1, 13, 18 have confusing wording in strings, “…are collectively a continuous and monolithic body of…”
For compact prosecution, the examiner interprets the strings to read in claims 1, 13, and 18 to read, “…are a collectively a continuous and monolithic body of…”
Claim 15 is objected to because of the following informalities:
Claim 15 is dependent on claim 13 and references “the continuous conformal layer” which is not introduced until claim 14.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8-9, 13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sugisaki (US 20200098776 A1) in view of Chen et al. (TW I679743 B).
Re Claim 1 Sugisaki teaches an integrated circuit device comprising:
a device layer (30) including a plurality of transistors (FIG. 3, 32 and 33) [0092];
a first interconnect feature (31) [0047] vertically extending through the device layer; and
an interconnect structure (100) below the device layer, the interconnect structure including at least a second interconnect feature (47, CP3, 46B, CP4, 49) [0050,0053,0054] that is conjoined with the first interconnect feature.
Sugisaki does not teach the first and second interconnect features are collectively a continuous and monolithic body of conductive material.
Chen teaches the first (106b) and second (106a) interconnect features are collectively a continuous and monolithic body of conductive material (page 8 par 1, “In some embodiments, the conductive structures 106a and 106b are part of the same overall structure.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen into the structure of Sugisaki since Chen teaches a device layer (104 and 108, page 9 par 3 states, “The one or more device regions 131 are located in the front side 104…”) with a first interconnect feature (106b) vertically extending through the device layer (108) connected to a second interconnect feature (106a) which is embedded in an interconnect structure (110, page 11 par 2) below the device layer (104 and 108, FIG. 1A).
The ordinary artisan would have been motivated to modify Chen in combination with Sugisaki in the above manner for the motivation of making the interconnect features between layers a continuous and monolithic body of conductive material to optimally integrate the conductive lines in an optimal manner to optimize space in the integrated circuit device. Page 3 par 4, “The semiconductor industry continues to increase the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area .”
Re Claim 5 Sugisaki in view of Chen teaches the integrated circuit structure of claim 1, wherein the conductive material comprises copper (Chen, page 8 par 1 states, “…the conductive structure 106a, the conductive structure 106b, or the contact plug (not shown)is made of a conductive material (such as copper…).
Re Claim 6 Sugisaki in view of Chen teaches the integrated circuit structure of claim 1, further comprising:
a first plurality of interconnect features (Sugisaki, 31) (FIG. 3) vertically extending through the device layer (30), the first plurality of interconnect features including the first interconnect feature (31),
wherein one or more of the first plurality of interconnect features (31) are conductive vias that couple the interconnect structure to corresponding one or more transistors (Sugisaki, 32B is source/drain region for transistor 32) [0060] of the plurality of transistors through one or more conductors of the device layer (30).
Re Claim 8 Sugisaki in view of Chen teaches the integrated circuit structure of claim 1, further comprising:
a first plurality of interconnect features (Sugisaki, 31) vertically extending through the device layer (30), the first plurality of interconnect features including the first interconnect feature (31),
wherein the interconnect structure (100) is a first interconnect structure that includes one or more first interconnect layers (47), the one or more first interconnect layers including a second plurality of interconnect features including the second interconnect feature (47,CP3, 46B, CP4, 49); and
a second interconnect structure (200) [0056] above the device layer and including one or more second interconnect layers (CP5B), the one or more second interconnect layers including a third plurality of interconnect features including a third interconnect feature (37, CP6, 35, CP5B) (FIG. 3).
Re Claim 9 Sugisaki in view of Chen teaches the integrated circuit structure of claim 8, wherein the first interconnect feature (Sugisaki, 31) is a conductive via coupling the second interconnect feature (47, top part of second interconnect feature) of the first interconnect structure and a third interconnect feature (CP5B, bottom part of third interconnect feature) of the second interconnect structure (200, FIG. 3).
Re Claim 13 Sugisaki teaches an integrated circuit device comprising:
a first interconnect feature (31) tapered towards the bottom, such that a first width of the first interconnect feature measured at or near a top surface of the first interconnect feature is at least 5% greater than a second width of the first interconnect feature measured at or near a bottom surface of the first interconnect feature (Fig. 3); and
a second interconnect feature (CP3) [0053] tapered towards the top, such that a third width of the second interconnect feature measured at or near a top surface of the second interconnect feature is at least 5% less than a fourth width of the second interconnect feature measured at or near a bottom surface of the second interconnect feature, wherein the first, second, third, and fourth widths are measured in a horizontal direction that is perpendicular to an imaginary line passing through the first and second interconnect features, and
wherein the first and second interconnect features collectively form a continuous body of conductive material (47 connects 31 and CP3, 47 is a “conductive pad” [0058].
Sugisaki teaches a contact/via with a top width greater than a bottom width, but does not explicitly teach the top width is greater than the bottom width by at least 5%.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the top width of the contact/via of Sugisaki as a means to provide a larger top surface area and improve process margin for alignment of subsequent elements.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, Sugisaki teaches the general condition of providing a contact/via with a larger top width than a bottom width, and discovering the optimum or working range of a top width "greater than 5%" of a bottom width would involve only routine skill.
Sugisaki does not teach the first and second interconnect features are collectively a continuous and monolithic body of conductive material.
Chen teaches the first (106b) and second (106a) interconnect features are collectively a continuous and monolithic body of conductive material (page 8 par 1, “In some embodiments, the conductive structures 106a and 106b are part of the same overall structure.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen into the structure of Sugisaki since Chen teaches a device layer (104 and 108, page 9 par 3 states, “The one or more device regions 131 are located in the front side 104…”) with a first interconnect feature (106b) vertically extending through the device layer (108) connected to a second interconnect feature (106a) which is embedded in an interconnect structure (110, page 11 par 2) below the device layer (104 and 108, FIG. 1A).
The ordinary artisan would have been motivated to modify Chen in combination with Sugisaki in the above manner for the motivation of making the interconnect features between layers a continuous and monolithic body of conductive material to optimally integrate the conductive lines in an optimal manner to optimize space in the integrated circuit device. Page 3 par 4, “The semiconductor industry continues to increase the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area .”
Re Claim 16 Sugisaki in view of Chen teaches the integrated circuit of claim 13, further comprising:
a device layer comprising a plurality of transistors (Sugisaki, 32 and 33) [0059],
wherein the first interconnect feature (31) at least in part extends through the device layer (FIG. 3).
Re Claim 17 Sugisaki in view of Chen teaches the integrated circuit of claim 16, further comprising:
a backside interconnect structure (Sugisaki, 100) (FIG. 3) below the device layer, the backside interconnect structure including one or more interconnect layers, the one or more interconnect layers including a plurality of interconnect features (47,CP3, 46B, CP4, 49) including the second interconnect feature (CP3).
Re claim 18 Sugisaki teaches a microelctronic device comprising:
a device layer (30) comprising a plurality of transistors (FIG. 3, 32 and 33);
a backside interconnect structure (100) below the device layer (30) and on a backside of the plurality of transistors, the backside interconnect structure comprising a plurality of backside interconnect features (47, CP3, 46B, CP4, 49) [0050,0053,0054] including a first backside interconnect feature (47);
a front side interconnect structure (200 [0045], the structure including CP5A, 35, CP6, etc.) above the device layer (30) and on a front side of the plurality of transistors (32 and 33), the front side interconnect structure (200) comprising a plurality of front side interconnect features (37, CP6, 35, CP5B) [0059, 0060] including a first front side interconnect feature (CP5B); and
an intermediate interconnect feature (31) between the backside interconnect structure (100) and the front side interconnect structure (200) and extending at least in part through the device layer (30), the intermediate interconnect feature (31) coupling the first backside interconnect feature (47) and the first front side interconnect feature (CP5B, FIG. 3).
Sugisaki does not teach the intermediate interconnect feature and the first backside interconnect feature are collectively a continuous and monolithic body of conductive material.
Chen teaches the intermediate interconnect feature (106b, FIG. 1A) and the first backside interconnect feature (106a) are collectively a continuous and monolithic body of conductive material (page 8 par 1, “In some embodiments, the conductive structures 106a and 106b are part of the same overall structure.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen into the structure of Sugisaki since Chen teaches a device layer (104 and 108, page 9 par 3 states, “The one or more device regions 131 are located in the front side 104…”) with an intermediate interconnect feature (106a) vertically extending through the device layer (108) connected to a second interconnect feature (106b) which is embedded in an interconnect structure (110, page 11 par 2) below the device layer (104 and 108, FIG. 1A).
The ordinary artisan would have been motivated to modify Chen in combination with Sugisaki in the above manner for the motivation of making the interconnect features between layers a continuous and monolithic body of conductive material to optimally integrate the conductive lines in an optimal manner to optimize space in the integrated circuit device. Page 3 par 4, “The semiconductor industry continues to increase the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area .”
Claims 2-4, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sugisaki (US 20200098776 A1) in view of Chen et al. (TW I679743 B) and further in view of Lin et al. (US 20210375723 A1, IDS).
Re Claim 2 Sugisaki in view of Chen teaches the integrated circuit of claim 1, but does not teach:
a continuous conformal layer on walls of the first and second interconnect features.
Lin teaches a continuous conformal layer (108A) [0032] on walls of the first (108B) [0032] and second interconnect features (124B) [0035].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Sugisaki in view of Chen since Lin teaches a device layer (102 and 114F&B contain semiconductor device 104F, [0022]) with a first interconnect feature (108B) vertically extending through the device layer (102 and 114F&B) connected to a second interconnect feature (124B) which is embedded in an interconnect structure (106B) [0022] below the device layer (102 and 114F&B, FIG. 1).
The ordinary artisan would have been motivated to modify Lin in combination with Sugisaki in view of Chen in the above manner for the motivation of forming a continuous conformal layer on walls of the first and second interconnect features to prevent the diffusion of surrounding layers [0032] states, “In addition, liner 108A can prevent the diffusion of materials from conductive plug 108B to adjacent structures (e.g., ESLs 120, IMD layers 122, substrate 102, or ILD layers 114F-114B) and/or the diffusion of materials from the adjacent structures to conductive plug 108B.”
Re Claim 3 Sugisaki in view of Chen and Lin teaches the integrated circuit of claim 2, wherein the continuous conformal layer comprises a barrier layer (Lin, Fig. 2) (108A) [0032] separating the body of conductive material (108B) from adjacent dielectric material (120) [0027].
Re Claim 4 Sugisaki in view of Chen and Lin teaches the integrated circuit structure of claim 2, wherein the continuous conformal layer (Lin, 108A) comprises one or more of cobalt, nickel, ruthenium, molybdenum, manganese, titanium, tungsten, tantalum, nitrogen, silicon ([0032 states, “In some embodiments, liner 108A can include a conductive material, such as Ta, Ti, Co, W, Ru, alloys of Ta, Ti, Co, W, Ru, and combinations thereof.”]).
Re Claim 14 Sugisaki in view of Chen teaches the integrated circuit of claim 13, but does not teach:
a continuous conformal layer on the walls of the first and second interconnect features.
Lin teaches a continuous conformal layer (Lin, 108A) [0032] on walls of the first (108B) [0032] and second interconnect features (124B) [0035].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Sugisaki in view of Chen since Lin teaches a device layer (102 and 114F&B contain semiconductor device 104F, [0022]) with a first interconnect feature (108B) vertically extending through the device layer (102 and 114F&B) connected to a second interconnect feature (124B) which is embedded in an interconnect structure (106B) [0022] below the device layer (102 and 114F&B, FIG. 1).
The ordinary artisan would have been motivated to modify Lin in combination with Sugisaki in view of Chen in the above manner for the motivation of forming a continuous conformal layer on walls of the first and second interconnect features to prevent the diffusion of surrounding layers [0032] states, “In addition, liner 108A can prevent the diffusion of materials from conductive plug 108B to adjacent structures (e.g., ESLs 120, IMD layers 122, substrate 102, or ILD layers 114F-114B) and/or the diffusion of materials from the adjacent structures to conductive plug 108B.”
Re Claim 19 Sugisaki in view of Chen teaches the microelectronic device of claim 18, further comprising:
Sugisaki in view of Chen teaches the barrier layer is absent between the conductive materials of the intermediate interconnect feature (Sugisaki , FIG. 3, 31) and the first backside interconnect feature (47) [0047].
Sugisaki in view of Chen does not teach a barrier layer on walls of the intermediate interconnect feature and the first backside interconnect feature.
Lin teaches a barrier layer (108A) [0032] on walls of the intermediate interconnect feature (108B) [0032] and the first backside interconnect feature (124B) [0035].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Sugisaki in view of Chen since Lin teaches a device layer (102 and 114F&B contain semiconductor device 104F, [0022]) with a first interconnect feature (108B) vertically extending through the device layer (102 and 114F&B) connected to a second interconnect feature (124B) which is embedded in an interconnect structure (106B) [0022] below the device layer (102 and 114F&B, FIG. 1).
The ordinary artisan would have been motivated to modify Lin in combination with Sugisaki in view of Chen in the above manner for the motivation of forming a continuous conformal layer on walls of the first and second interconnect features to prevent the diffusion of surrounding layers [0032] states, “In addition, liner 108A can prevent the diffusion of materials from conductive plug 108B to adjacent structures (e.g., ESLs 120, IMD layers 122, substrate 102, or ILD layers 114F-114B) and/or the diffusion of materials from the adjacent structures to conductive plug 108B.”
Claims 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sugisaki (US 20200098776 A1) in view of Chen et al. (TW I679743 B) and further in view of Wu et al. (US 20210358848 A1).
Re Claim 7 Sugisaki in view of Chen teaches the integrated circuit structure of claim 1, but does not teach the second interconnect feature of the interconnect structure below the device layer is a buried or backside power rail (BPR) that is to supply power, through the first interconnect feature, to a corresponding transistor of the plurality of transistors.
Wu teaches the second interconnect feature of the interconnect structure below the device layer (201) [0097] is a buried or backside power rail (BPR) (Wu, FIG. 2B) (202) that is to supply power, through the first interconnect feature (208) [0060], to a corresponding transistor (206b) [0100] of the plurality of transistors (FIG. 2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Sugisaki in view of Chen since Wu teaches a device layer over an interconnect structure.
The ordinary artisan would have been motivated to modify Wu in combination with Sugisaki in view of Chen in the above manner for the motivation of integrating a BPR into an integrated circuit to reduce the device size making dimensions smaller. Wu [0002] states, “The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power yet provide more functionality at higher speeds.”
Claims 10-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sugisaki (US 20200098776 A1) in view of Chen et al. (TW I679743 B) and further in view of et al. Chang (US 20210375761 A1).
Re Claim 10 Sugisaki in view of Chen teaches the integrated circuit structure of claim 8, but does not teach:
a plurality of input/output pins below the first interconnect structure, the plurality of input/output pins coupling the integrated circuit structure to a printed circuit board.
Chang teaches a plurality of input/output pins (148) below the first interconnect structure (120) [0067], the plurality of input/output pins (FIG. 28A) coupling the integrated circuit structure to a printed circuit board [0093].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chang into the structure of Sugisaki in view of Chen since Chang teaches a device layer over an interconnect structure.
The ordinary artisan would have been motivated to modify Wu in combination with Sugisaki in view of Chen in the above manner for the motivation of integrating a plurality of input/output pins to be able to send and receive signals from a second device. [0093] states, “…148 may be used to provide input/output connections to other electrical components, such as, other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like.”
The plurality of input/output pins are not below the interconnect structure, but it does not matter where on attaches the output pins as they will function the same if above or below another structure. One of ordinary skills in the art can rearrange the pins on the device where physically needed. It has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Re Claim 11 Sugisaki in view of Chen and Chang teaches the integrated circuit device of claim 10, wherein:
one or more of the second plurality of interconnect features (Sugisaki, 47,CP3, 46B, CP4, 49) route signals (i) between the plurality of transistors (32 and 33) and (ii) from or to one or more input or output pins (use Chang, 148, taught in claim 10) [0093]; and
one or more of the third plurality of interconnect features (Sugisaki, 37, CP6, 35, CP5B) route signals between the plurality of transistors (32 and 33, FIG. 15).
Re Claim 12 Sugisaki in view of Chen and Chang teaches the integrated circuit device of claim 10, wherein one or more of the second plurality of interconnect features (Sugisaki, 47,CP3, 46B, CP4, 49) route power to the plurality of transistors (32 and 33, FIG. 15).
Re Claim 20 Sugisaki in view of Chen teaches the microelectronic device of claim 18, further comprising:
a plurality of input/output (I/O) pins below the backside interconnect structure, to couple the microelectronic device to a printed circuit board.
Chang teaches a plurality of input/output pins (148) below the backside structure (120) [0067], to couple the microelectronic device to a printed circuit board (FIG. 28A) [0093].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chang into the structure of Sugisaki in view of Chen since Chang teaches a device layer over an interconnect structure.
The ordinary artisan would have been motivated to modify Wu in combination with Sugisaki in view of Chen in the above manner for the motivation of integrating a plurality of input/output pins to be able to send and receive signals from a second device. [0093] states, “…148 may be used to provide input/output connections to other electrical components, such as, other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like.”
The plurality of input/output pins are not below the interconnect structure, but it does not matter where on attaches the output pins as they will function the same if above or below another structure. One of ordinary skills in the art can rearrange the pins on the device where physically needed. It has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sugisaki (US 20200098776 A1) in view of Chen et al. (TW I679743 B) and further in view of Tsai et al. (US 20200135871 A1).
Re Claim 15 Sugisaki in view of Chen teaches the integrated circuit of claim 14, but does not teach the continuous conformal layer on the walls of the first and second interconnect features is absent between at least a section of a junction between the first and second interconnect features.
Tsai teaches the continuous conformal layer (902 and 1602) [0065] on the walls of the first and second interconnect features (1002 and 1606) [0066] is absent between at least a section of a junction (top part of 1002 in direct contact with 1402) between the first and second interconnect features (FIG. 16).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Tsai into the structure of Sugisaki in view of Chen since Tsai teaches a device layer over an interconnect structure.
The ordinary artisan would have been motivated to modify Tsai in combination with Sugisaki in view of Chen in the above manner for the motivation of having a section of the liner being absent over the interconnect features’ junction to help the device function in an optimal manner as functional density continues to increase while size decreases. [0002] states, “The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.”
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 2/19/26