Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant elected with traverse Species 1 (interposer) in the reply filed on 21 April 2025.
The requirement was deemed proper and was therefore made FINAL.
Claims 11-13 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 21 April 2025.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed August 15, 2025. Claim 15 is amended. Claims 3, 17, and 22 are cancelled. Claims 11-13 remain withdrawn. The Examiner notes that claims 1, 2, 4-10, 14-16, 21, and 23-26 are examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4-6, 9, 10, 14-16, 21, and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over CN-1111769076-A by Chen (hereinafter CHEN), in view of Han, et al., “Metal-assisted chemical etching of silicon and nanotechnology applications”, Nano Today 9(3), 2014, pp.271-304 (hereinafter HAN).
Claim 1. CHEN discloses an apparatus (Fig. 15) comprising:
a first layer comprising silicon (Fig. 15/200, [0054] line 5);
a conductive feature extending within the silicon of the first layer (Fig. 15/209 copper, [0054] line 2) the conductive feature comprising (i) conductive material extending throughout the length of the conductive feature (209 extends throughout the vertical length of 200), (ii) a barrier layer between the conductive material and the silicon of the first layer (Fig. 15/208 TaN barrier layer, [0053] lines 7-8), and (iii) a second layer comprising dielectric material between the barrier layer and the silicon of the first layer (Fig. 15/207 SiO2 insulating layer, [0053] lines 1-2).
CHEN does not disclose one or more monolayers of metal between sections of the dielectric material and the silicon of the first layer.
HAN teaches one or more monolayers of metal may exist on the sidewalls of the silicon, which would locate said monolayers between sections of the dielectric material and the silicon of the first layer (metal-assisted chemical etch – MACE – can be used to controllably fabricate silicon structures, page 272, column 1, lines 37-41, and includes the use of metal catalyst particles, page 272, column 2, lines 4-6; atoms from the catalyst, in this case Ag which must be at least one monolayer, end up on the sidewall of the etched silicon, page 276, column 1, lines 35-39).
There is a motivation in via creation to have a simple, cost-efficient and versatile etch method (page 271, column 2, lines 5-9). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the monolayers of material of HAN into the TSV of CHEN to have good manufacturability.
Claim 2. CHEN/HAN further disclose the apparatus of claim 1, wherein the one or more monolayers of metal are discontinuous (silver particles which are by definition discontinuous on the sidewalls, HAN p. 276, column 1, lines 39-41), such that the one or more monolayers are between some sections of the dielectric material and the silicon of the first layer, and not between other sections of the dielectric material and the silicon of the first layer (CHEN Fig. 15/207 dielectric deposited over sidewall of silicon 200 will necessarily have silver particles between itself and the silicon in some sections but not in others).
Claim 4. CHEN discloses the apparatus of claim 1, wherein the metal comprises one or more of gold, silver, platinum, palladium, or nickel (Fig. 5/206 Ag etch catalyst, [0052] line 25).
Claim 5. CHEN discloses the apparatus of claim 1, wherein the metal is a first metal (Fig 5/206 Ag), wherein the barrier layer comprises a second metal different from the first metal (Fig. 15/208 comprises Ta, [0053] line 7), and wherein the conductive material comprises a third metal different from each of the first and second metals (Fig. 15/209 copper, [0054] line 2).
Claim 6. CHEN discloses the apparatus of claim 1, wherein the conductive material comprises one or more of copper, ruthenium, molybdenum, tungsten, antimony, aluminum, or bismuth (Fig. 15/209 copper, [0054] line 2).
Claim 9. CHEN discloses the apparatus of claim 1, wherein:
a first end of the conductive material is coupled to a first bump comprising another conductive material (Fig. 15/212 micro-bump – [0055] line 12 – is comprised of Cu and Sn – [0054] lines 17-18 – and is coupled to 209 through 211), the first bump to couple the apparatus to an integrated circuit chip (this limitation is a statement of intended purpose for the first bump; since the structure and materials of CHEN are the same as in the instant application, it creates a prima facie case for obviousness that the structure can be applied to the same purpose; see MPEP § 2144) ; and
a second end of the conductive material is coupled to a second bump comprising another conductive material (Fig. 15/215 C4 bump – [0055] line 20 – is comprised of Cu and Sn – [0054] lines 30-31 – and is coupled to 209 through 211), the second bump to couple the apparatus to a printed circuit board (this limitation is a statement of intended purpose for the second bump; since the structure and materials of CHEN are the same as in the instant application, it creates a prima facie case for obviousness that the structure can be applied to the same purpose; see MPEP § 2144).
Claim 10. CHEN discloses the apparatus of claim 1, wherein the conductive feature is a first conductive feature (Fig. 15/209 on the left), and wherein the apparatus comprises:
a plurality of conductive features, including the first conductive feature, extending within the silicon of the first layer (Fig. 15/209 left and right).
Claim 14. CHEN discloses the apparatus of claim 1, wherein:
the conductive feature is formed within a recess extending through the silicon of the first layer (Fig. 15/209 extends through silicon 200).
CHEN does not disclose wherein the one or more monolayers of metal are on sidewalls of the recess; and
the one or more monolayers of metal are remnants of metal used to etch the recess within the silicon of the layer using a metal assisted etch process.
HAN teaches wherein the one or more monolayers of metal are on sidewalls of the recess (metal-assisted chemical etch – MACE – can be used to controllably fabricate silicon structures, page 272, column 1, lines 37-39, and includes the use of metal catalyst particles, page 272, column 2, lines 4-6; atoms from the catalyst, in this case Ag which must be at least one monolayer, end up on the sidewall of the etched silicon, page 276, column 1, lines 35-39); and
the one or more monolayers of metal are remnants of metal used to etch the recess within the silicon of the layer using a metal assisted etch process (see above clause of this rejection).
There is a motivation in via creation to have a simple, cost-efficient and versatile etch method (page 271, column 2, lines 5-9). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the monolayers of material resulting from etching of HAN into the apparatus of CHEN to have good manufacturability.
Claim 15. CHEN/HAN disclose microelectronics device comprising:
a layer comprising semiconductor material (Fig. 15/200 silicon);
a recess extending within the semiconductor material of the layer (Fig. 6/recesses formed by etch, [0052] line 27-30);
one or more monolayers of metal on walls of the recess (metal-assisted chemical etch – MACE – can be used to controllably fabricate silicon structures, page 272, column 1, lines 37-39, and includes the use of metal catalyst particles, page 272, column 2, lines 4-6; atoms from the catalyst, in this case Ag particles which must be at least one monolayer, end up on the sidewall of the etched silicon, page 276, column 1, lines 35-41),
a dielectric material at least in part on walls of the recess, such that the one or more monolayers of metal is between some sections of the dielectric material and the walls of the recess, and not between other sections of the dielectric material and the walls of the recess (CHEN Fig. 15/207 dielectric deposited over sidewall of silicon 200 will necessarily have silver particles between itself and the silicon in some sections but not in others); and
conductive material within the recess (Fig. 15/209 copper, [0054] line 2).
Claim 16. CHEN discloses the microelectronics device of claim 15, further comprising:
a barrier layer between the conductive material and the dielectric material ((Fig. 15/208 TaN barrier layer between 209 and 207, [0053] lines 7-8)).
Claim 21. CHEN discloses an apparatus comprising:
a first layer comprising a semiconductor material (Fig. 15/200 silicon, [0054] line 5);
a conductive structure extending along a first direction through an entire thickness of the first layer (Fig. 15/207+208+209 extend vertically through the entire thickness of 200), the conductive structure comprising
a conductive layer (Fig. 15/209 copper, [0054] line 2), a barrier layer between the conductive layer and the first layer along a second direction orthogonal to the first direction (Fig. 15/208 TaN barrier layer whose thickness extends horizontally, [0053] lines 7-8), and
a second layer comprising dielectric material between the barrier layer and the first layer along the second direction (Fig. 15/207 SiO2 insulating layer whose thickness extends horizontally, [0053] lines 1-2).
CHEN does not disclose one or more discontinuous monolayers of metal at an interface between the second layer and the first layer.
HAN teaches one or more discontinuous monolayers of metal at an interface between the second layer and the first layer (metal-assisted chemical etch – MACE – can be used to controllably fabricate silicon structures, page 272, column 1, lines 37-41, and includes the use of metal catalyst particles, page 272, column 2, lines 4-6; atoms from the catalyst, in this case Ag particles which must be at least one monolayer and, being particles, are discontinuous as a layer, end up on the sidewall of the etched silicon, page 276, column 1, lines 35-39).
There is a motivation in via creation to have a simple, cost-efficient and versatile etch method (page 271, column 2, lines 5-9). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the discontinuous monolayers of m of HAN into the apparatus of CHEN to have good manufacturability.
Claim 23. CHEN discloses the apparatus of claim 21, wherein the metal comprises one or more of gold, silver, platinum, palladium, or nickel (Fig. 5/206 Ag etch catalyst, [0052] line 25).
Claim 24. CHEN discloses the apparatus of claim 15, wherein the metal comprises one or more of gold, silver, platinum, palladium, or nickel (Fig. 5/206 Ag etch catalyst, [0052] line 25).
Claim 25. CHEN discloses the microelectronics device of claim 15, wherein:
a first end of the conductive material is coupled to a first bump comprising another conductive material (Fig. 15/212 micro-bump – [0055] line 12 – is comprised of Cu and Sn – [0054] lines 17-18 – and is coupled to 209 through 211); and
a second end of the conductive material is coupled to a second bump comprising another conductive material (Fig. 15/215 C4 bump – [0055] line 20 – is comprised of Cu and Sn – [0054] lines 30-31 – and is coupled to 209 through 211).
Claim 26. CHEN discloses the apparatus of claim 21, wherein the metal is a first metal (Fig 5/206 Ag), wherein the barrier layer comprises a second metal different from the first metal (Fig. 15/208 comprises Ta, [0053] line 7), and wherein the conductive layer comprises a third metal different from each of the first and second metals (Fig. 15/209 copper, [0054] line 2).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of HAN as applied to claim 1 above, and further in view of Huang et al., “Metal‐Assisted Chemical Etching of Silicon: A Review”, Advanced Materials 23 (2010), pp. 285-308 (hereinafter HUANG).
CHEN/HAN discloses the apparatus of claim 1.
CHEN/HAN does not disclose wherein the conductive feature has a height-to-width aspect ratio of at least 8:1.
HUANG teaches wherein the conductive feature has a height-to-width aspect ratio of at least 8:1 (Fig. 5b created by metal-assisted chemical etching – page 290, section 3.2, lines 1-3 – wherein the bottom of the hole has a diameter of approximately 0.5 µm, according to the inset scale bar, while the depth is greater than 10 µm, according to the larger scale bar, therefore disclosing an aspect ratio greater than 20. It is prima facie obvious that a height-to-width aspect ratio greater than 20 is also greater than 8; see MPEP § 2144.05).
There is a motivation to control parameters of nanostructures formed by etching, and metal-assisted chemical etching can provide this (page 285, column 2, lines 3-9). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the etching of HUANG into the apparatus of CHEN/HAN to control feature morphology.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of HAN as applied to claim 1 above, and further in view of US-20210183773-A1 by Rubin (hereinafter RUBIN).
CHEN discloses the apparatus of claim 1. CHEN further discloses that the apparatus relates to a TSV adapter plate for 2.5D packaging ([0002]).
CHEN does not disclose the details wherein a first end of the conductive material is coupled to an interconnect feature of an integrated circuit chip, and wherein a second end of the conductive material is coupled to another interconnect feature coupling the apparatus to a printed circuit board.
RUBIN teaches that 2.5D packaging solutions utilize silicon interposers (TSV adapter plate of CHEN), wherein a first end of the conductive material (TSV) is coupled to an interconnect feature of an integrated circuit chip (interposer coupled to chip interconnects, [0003] lines 5-13), and wherein a second end of the conductive material is coupled to another interconnect feature coupling the apparatus to a printed circuit board (modules mounted to a printed circuit board using connection features for I/O connections ( [0002] lines 7-10).
There is a motivation to increase the density of integrated chip modules ([0002], lines 1-3). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the chip coupling of RUBIN into the apparatus of CHEN/HAN to obtain higher performance packages.
Response to Arguments
Claim rejections under 35 USC §112 are withdrawn in view of amendment to claim 15 and cancellation of claims 3, 17, and 22.
Applicant's arguments filed August 15, 2025 have been fully considered but they are not persuasive. Applicant argues that the teachings of Han are not applicable to the teachings of Chen because Han teaches that nucleation occurs in doped silicon around defects caused by doping. Applicant alleges that the silicon wafer of Chen is undoped, however Chen does not specify whether the silicon wafer is doped or undoped.
Han recites “these Ag+ ions may start to nucleate on the sidewall of previously formed Si structure near certain weak defective sites (e.g., around dopants).” The phrase “e.g. around dopants” merely recites dopants as an example of a defect site that may cause Ag to nucleate that is easy to control. The ordinary artisan would understand that silicon may also include intrinsic defects that may lead to Ag nucleation. Further, the instant application recites in para. [0029] of the specification that the silicon layer 104 may be doped or undoped. Chen modified by the etching method of Han teaches a substantially identical process of etching using metal assisted chemical etching of a silicon substrate. “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).” Therefore, it would be obvious over Chen in view of Han that the metal monolayers would form regardless of whether the substrate of Chen is doped or undoped.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights