Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06 April 2026 has been entered.
Response to Arguments
Applicant's arguments filed on 04/16/2026 have been fully considered but they are not persuasive.
Applicant argues Do fails to disclose the amended limitations of claim 1 that “the via structure is horizontally overlapping with the source or drain structure along a horizontal axis”. However, underside of via 10 of via structure 30/10 extends horizontally in X and Y direction and overlaps the source/drain structure 26_L2 long a horizontal axis, as shown in Fig. 2B of Do. Accordingly, the rejection of amended claim 1 is maintained.
Applicant further argues Do fails to disclose the amended limitations of claim 8 that “the via structure is horizontally overlapping with the gate structure along a horizontal axis”. However, underside of via 32 of via structure 30/32 extends in X and Y direction and is overlapping with an upper surface of gate structure 24 in horizontal axis, as shown in Fig. 2A of Do. Accordingly, the rejection of amended claim 8 is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6, 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Do (US 20210384106 A1).
Re: Independent Claim 1 (Currently Amended), Do discloses an integrated circuit structure, comprising:
a device layer (Fig 2A-2B, layer with active regions 22_U/22_L,) within a cell boundary (Fig 5A, the transistors 22_U/22_L features belong to a standard cell enclosed by the cell boundary CB),
the device layer having a front side (Fig 2A-2B, side with active devices 22_U/22_L) and a backside (Fig 2A-2B side with powerlines P1/P2), and the device layer comprising a source or drain structure (Fig 2B, active regions 26_L1/26_L2 on 22_L, and 26_U1/26_U2 on 22_U);
a source or drain trench contact structure (Fig 2B, contact structure 28 and 34_2) on the front side of the device layer, the source or drain trench contact structure over and coupled to the source or drain structure (Fig 2B, 34_2 is over source/drain structure 26_U1; 28 and 34_2 are electrically coupled to source/drain structure 26_U1);
a metal layer on the backside of the device layer (Fig 2B, backside power lines P1 and P2 is metal layer);
and a via structure coupling the metal layer to the source or drain trench contact structure (Fig 2B, via structure 30/10 electrically couple P1 and P2 source/drain trench contact structure #28 and #34_2),
the via structure spaced apart from and extending along a side of the source or drain structure such that the via structure is horizontally overlapping with the source or drain structure along a horizontal axis, and the via structure overlapping and parallel with a cell row boundary of the cell boundary (Fig 4, via 30 of via structure 30/10 is spaced apart from 26_U1; and via 30 is positioned adjacent to a side/edge region of the source/drain structure and runs alongside in the vertical direction, and it overlaps the row interface cell boundary between first and second rows and is aligned along the direction of row, hence parallel with the cell-row boundary. Also, underside of via 10 of via structure 30/10 extends horizontally in X and Y direction and overlaps the source/drain structure 26_L2 long a horizontal axis, as shown in Fig. 2B).
Re: Claim 2 (Original), Do discloses all the limitations of claim 1 on which this claim depends. Do further discloses,
wherein the via structure includes a break (Fig 2A/2B and Fig 4, gap between via 30 and via 10 along CB) along the cell row boundary.
Re: Claim 6 (Original), Do discloses all the limitations of claim 1 on which this claim depends. Do further discloses,
wherein the via structure is further coupled to a second source or drain trench contact structure (Fig 5C, via 10 is couple to 27_L2), the second source or drain trench contact structure on the front side of the device layer (Fig 5C, 27_L2 is formed on the surface of the active area which is on the front side of the device layer).
Re: Claim 7 (Original), Do discloses all the limitations of claim 1 on which this claim depends. Do further discloses,
wherein the device layer comprises a channel structure (Fig 2B, column 4, lines 28-39, active regions 22U and 22L are channels) selected from the group consisting of a fin, a nanowire, and a nanoribbon (Fig 2B, column 4, lines 65-67 and column 4, lines 1-4, TR_L and TR_U are Multi Bridge channel Field Effect Transistor with multiple nanosheets).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Do (US 20210384106 A1).
Re: Claim 3 (Original), Do discloses all the limitations of claim 2 on which this claim depends. Do further discloses,
wherein a gate structure of the device layer (Fig 2A, gate structure 24).
Do does not explicitly disclose gate structure of the device layer passes through the break.
However, Do teaches in Fig 2A, gate structure 24 lies between the first source/drain 26_U1 and the second source/drain 26_U2; and fig 2B identifies the Source/Drain path served by the two boundary vias 30 and 10, confirming that the gate 24 lies across the same Y region separating 30 from 10. Do further describes the gate 24 as stacked on the surface of the active region. Also, at the boundary, Fig 5B (B-B') is a CB cross section without a via at that cut, illustrating a break segment where the gate appears.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to route the gate structure 24 through the via-free span(break) so that the gate lies between the first and second S/D in order to achieve basic FET operability (column 5, lines 24-28).
Re: Claim 4 (Original), Do discloses all the limitations of claim 2 on which this claim depends. Do further discloses,
wherein a second source or drain trench contact structure (Fig 5C, 27_U2/27_L2 couples the second S/Ds 26_U2/26_L2to the output via 10). Do does not explicitly disclose the second source or drain trench contact structure passes through the break.
However, Do teaches in Fig 2B, via 10 and 30 and the Source/Drain nodes they serve. Because via 10 is positioned along the CB and via 30 is spaced from it along the boundary, the routing contact 27_U2/27_L2 necessarily extends from the second Source/Drain to the boundary-placed via 10, thereby traversing the via-free span (break) between 30 and 10 along the CB to complete connectivity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to be implementing the second Source/Drain trench contact structure pass through the break, as the disclosed placement of Do, in order to eliminate extra isolation space and allow a narrower powerline at the boundary (Do, column 7, lines 5-18).
Re: Claim 5 (Original), Do discloses all the limitations of claim 4 on which this claim depends. Do further discloses,
wherein the second source or drain trench contact structure is not coupled to the backside of the device layer (Fig 5C, 27_U2 is coupling the second Source/Drain to via 10 in front side of the device, not to power lines which is in the backside of the device layer).
Re: Independent Claim 8 (Currently Amended), Do discloses: An integrated circuit structure, comprising:
a device layer (Fig 2A-2B, layer with active regions 22_U/22_L) within a cell boundary (Fig 4, cell boundary CB),
the device layer having a front side (Fig 2A, side with active devices TR_U/ TR_L) and a backside (Fig 2A, side with metal layer 36_1),
and the device layer comprising a gate structure (Fig 2A, gate 24);
a metal layer (Fig 2A, 36_1 is metal layer) on the backside of the device layer;
and a via structure (via 30/via 32) coupling the metal layer to the gate structure (Fig 2A, 32 coupling metal layer 36_1 to gate structure 24), spaced apart from and extending along a side of the gate structure, and the via structure such that the via structure is horizontally overlapping with the gate structure along a horizontal axis, (via 30 of via structure 30/32 is spaced apart from gate structure 24, and is positioned adjacent to gate structure 24 and runs alongside in the vertical direction, and underside of via 32 of via structure 30/32 extends in X and Y direction and is overlapping with an upper surface of gate structure 24 in horizontal axis, as shown in Fig. 2A).
Do does not explicitly disclose the via structure overlapping and parallel with a cell row boundary of the cell boundary. However, Do teaches that Figs 5A-5C are cross-sections taken along the line A-A'/B-B'/C-C' of Fig. 4 (column 6, lines 29-32), and Fig. 4 identifies the interface between adjacent rows as the cell boundary CB and that the rows extend in the first (row) direction. In the CB section B-B', Do describes (column 9, lines 3-5) "a first metal via 34_1...connected to the gate structure 24", and also explains (column 5, lines 42-50) that the gate structure 24 is couples to the metal line 36_1 through the gate-contact stack (lower via 32, first meal via 34_1). In the view of these teachings, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to place the gate-contact via at the CB location in plan (so it overlaps the CB) and to repeat that placement along the row/first direction (i.e., parallel to the CB) across the standard-cell row in order to avoid the requirement of extra isolation space at the boundary so that boundary width can be reduced, thereby avoiding increased cell height (column 3, lines 7-27).
Re: Claim 9 (Currently Amended), Do discloses all the limitations of claim 8 on which this claim depends. Do does not explicitly disclose,
wherein the via structure is further coupled to a second gate structure.
However, Do teaches in Fig 2A, the gate structure 24 formed on the active region positioned between the first and second Source/Drain regions of upper and lower transistor. Do also teaches that via 10 contacts the second Source/Drain (26_U2/26_L2) in Figure 2B. It would have been obvious to person of ordinary skill in the art before the effective filing date of the claimed invention to implement the same gate placement of Fig 2A in the Fig 2B layout and to route the cell's output at via 10 through the interconnect network to drive the input (i.e., a second gate structure 24 of the subsequent cell), so the via 10 will be further coupled to a second gate structure, for the gate structure to electrically connect to an input node and receive signal from interconnect to drive the transistor (column 5, lines 42-44).
Re: Claim 10 (Currently Amended), Do discloses all the limitations of claim 8 on which this claim depends. Do further discloses,
wherein the device layer comprises a channel structure (Fig 2B, column 4, lines 28-39, active regions 22U and 22L are channels) selected from the group consisting of a fin, a nanowire, and a nanoribbon (Fig 2B, column 4, lines 65-67 and column 4, lines 1-4, TR_L and TR_U are Multi Bridge channel Field Effect Transistor with multiple nanosheets).
Conclusion
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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