DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/2025 has been entered.
Response to Arguments
Applicant’s response has been fully considered.
Applicant’s amendments to claim 33 overcomes the rejection under 35 U.S.C. 112.
Applicant’s amendments and the accompanying arguments with respect to the second metal post and the first base die and the second base die being laterally between the first metal post and the second metal post have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Woychik et al. (US 2016/0049383) (cited on the IDS of 04/11/2022).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Shen et al. (US 2015/0327367), Yeh et al. (US 2017/0125376), Koide et al. (US 2011/0089579), and Woychik et al. (US 2016/0049383).
In reference to claim 1, Hung et al. (US 2015/0171006), hereafter “Hung,” discloses a chip package, with reference to Figure 35B, comprising:
a first base die 100 in a molding material 34, the first base die comprising interconnections 104, paragraph 12;
a first metal post 32 (at left) in the molding material, the first metal post laterally adjacent to the first base die,
a second metal post 32 (at right) in the molding material, paragraph 16;
a first chip 200 electrically coupled to the first base die;
a second chip 200 electrically coupled to the first base die, paragraph 25; and
a dielectric material 56 between and in contact with the first chip and the second chip, paragraph 26.
Hung does not disclose the first base die comprising die-to-die interconnections,
a second base die in the molding material, the second base die comprising die-to-die interconnections, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die,
the second metal post laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post,
the second chip electrically coupled to the first chip by the die-to-die interconnections in the first base die,
wherein one of the first chip or the second chip has first terminations and second terminations, wherein the second terminations have a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the first base die,
the dielectric material having an upper surface co-planar with an upper surface of the first chip,
the dielectric material in contact with the molding material, or
the dielectric material in contact with the metal post.
Shen et al. (US 2015/0327367), hereafter “Shen,” discloses a semiconductor chip package including a first base die, ITP 120 in Figure 1, and a second base die, ITP 120, in the molding material (not pictured), the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die, paragraph 4.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second base die to be in the molding material, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, to duplicate the base die of Hung within a single semiconductor device package to expand the number of dies incorporated in the device and, thereby naturally result in the molding material 34 of Hung being located laterally between the second base die and the first base die.
Shen further teaches a first base die ATP 120 comprising die-to-die interconnections 120I, a second base die ATP 120 comprising die-to-die interconnections 120I, and a second chip 110 in Figure 1, electrically coupled to the first chip 110 by the die-to-die interconnections 120I in the first base die, paragraph 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise die-to-die interconnections, the second base die to comprise die-to-die interconnections, and the second chip to be electrically coupled to the first chip by the die-to-die interconnections in the first base die. One would have been motivated to do so in order to provide an additional interconnect level to supplement other electrical connections, paragraph 5.
Woychik et al. (US 2016/0049383), hereafter “Woychik,” disclose a semiconductor device package including teaching a first metal post, 140 (at left) in Figure 1, in the molding material 150, the first metal post laterally adjacent to the first base die, a second metal post 140 (at right) in the molding material, the second metal post laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post, paragraph 25, see also annotated Figure 1 below.
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[AltContent: textbox (1st base die)][AltContent: textbox (2nd base die)][AltContent: textbox (1st metal post)][AltContent: textbox (2nd metal post)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (1st base die)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second metal post to be laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post. One would have been motivated to do so in order to interconnect and distribute power throughout the package, paragraph 26.
Koide et al. (US 2011/0089579), hereafter “Koide,” discloses a semiconductor device package including teaching wherein one of the first chip or the second chip, 30A in Figure 1, has first terminations 32b and second terminations 32a, the second terminations 32a having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the base die, Figure 2 and paragraphs 17,20, and 22. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second terminations to have a pitch less than a pitch of the first terminations, wherein the second terminations are coupled to the die-to-die interconnections of the first base die. One would have been motivated to do so in order to form wiring between chips that is the same as wiring within the chip in order to suppress a decrease in transmission efficiency between chips, paragraphs 27 and 30.
Yeh et al. (US 2017/0125376), hereafter “Yeh,” discloses a chip package including teaching a dielectric material, 120 in Figure 6, having an upper surface co-planar with an upper surface of the first chip 102B, paragraph 35. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric material to have an upper surface co-planar with an upper surface of the first chip. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case substituting one dielectric layer configuration for another as suggested by Yeh, paragraph 35.
In reference to claim 3, Hung does not disclose the first base die comprises a plurality of through interconnections.
Shen teaches a first base die, 120 in Figure 1, comprising through interconnections 120I, paragraph 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise through interconnections. One would have been motivated to do so in order to allow communication between the chip package with outside devices, paragraph 4.
In reference to claim 5, Hung discloses the first base die is an active die, paragraph 12.
In reference to claim 7, Yeh discloses the upper surface of the dielectric material 120 is co-planar with an upper surface of the second chip 102C, Figure 6.
In reference to claim 8, Hung discloses the first chip and the second chip are entirely within a footprint of the first base die, Figure 35A.
In reference to claim 9, Hung discloses the first chip is a first node chip, and the second chip is a second node chip, paragraph 22, the chips of Hung inherently being of a node.
In reference to claim 10, Hung discloses a plurality of conductive interconnections beneath the first base die, paragraph 29.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Shen et al. (US 2015/0327367), Yeh et al. (US 2017/0125376), Koide et al. (US 2011/0089579), and Woychik et al. (US 2016/0049383), as applied to claim 1 above and further in view of Huang et al. (US 2017/0250139).
In reference to claim 2, Hung does not disclose the first metal post is a first fiducial and the second metal post is a second fiducial.
Huang et al. (US 2017/0250139), hereafter “Huang,” discloses a chip package including teaching a first metal post, 32A in Figures 4A, 4B, and 5, is a first fiducial, and a second metal post 32A, see especially Figure 4B, is a second fiducial, paragraphs 18, 19, and 25. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first metal post to be a first fiducial and the second metal post to be a second fiducial. One would have been motivated to do so in order to have an alignment mark for aligning the placement of dies in the chip package, paragraph 25.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Shen et al. (US 2015/0327367), Yeh et al. (US 2017/0125376), Koide et al. (US 2011/0089579) and Woychik et al. (US 2016/0049383), as applied to claim 1 above and further in view of Brothers et al. (US 2013/0141442).
In reference to claim 4, Hung does not disclose the first base die is a passive die.
Brothers et al. (US 2013/0141442), hereafter “Brothers,” teaches a base die, 30 in Figure 3, that is a passive die, paragraphs 24 and 25 (“interposer” as opposed to an “integrated circuit”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to be a passive die. To do so would merely be to apply a variation of known work in a related field to achieve predictable results based on design incentives, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case to mount, connect, and route signals in order to satisfy the communication requirements between dies.
Claims 11, 13, 15, 19-22, 25, 29-34, 37, and 41-44 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Shen et al. (US 2015/0327367), Koide et al. (US 2011/0089579), and Woychik et al. (US 2016/0049383).
In reference to claim 11, Hung discloses a chip package, with reference to Figure 35B, comprising:
a first base die 100 in a molding material 34, the first base die comprising interconnections, paragraph 12;
a first metal post 32 (on left) in the molding material, the metal post laterally adjacent to the first base die,
a second metal post 32 (on right) in the molding material, paragraph 16;
a first chip 200 electrically coupled to the first base die;
a second chip 200 electrically coupled to the first base die, paragraph 25;
an underfill material 54 between the first chip and the first base die and between the second chip and the first base die; and
a dielectric material 56 laterally adjacent to the first chip and the second chip, paragraph 26.
Hung does not disclose the first base die comprising die-to-die interconnections,
a second base die in the molding material, the second base die comprising die-to-die interconnections, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die,
the second metal post laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post,
the second chip electrically coupled to the first chip by the die-to-die interconnections in the first base die,
wherein one of the first chip or the second chip has first terminations and second terminations, wherein the second terminations have a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the first base die,
the dielectric material in contact with the molding material, or
the dielectric material in contact with the metal post.
Shen discloses a semiconductor chip package including a first base die, ITP 120 in Figure 1, and a second base die, ITP 120, in the molding material (not pictured), the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die, paragraph 4.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second base die to be in the molding material, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, to duplicate the base die of Hung within a single semiconductor device package to expand the number of dies incorporated in the device and, thereby naturally result in the molding material 34 of Hung being located laterally between the second base die and the first base die.
Shen further teaches a first base die ATP 120 comprising die-to-die interconnections 120I, a second base die ATP 120 comprising die-to-die interconnections 120I, and a second chip 110 in Figure 1, electrically coupled to the first chip 110 by the die-to-die interconnections 120I in the first base die, paragraph 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise die-to-die interconnections, the second base die to comprise die-to-die interconnections, and the second chip to be electrically coupled to the first chip by the die-to-die interconnections in the first base die. One would have been motivated to do so in order to provide an additional interconnect level to supplement other electrical connections, paragraph 5.
Woychik disclose a semiconductor device package including teaching a first metal post, 140 (at left) in Figure 1, in the molding material 150, the first metal post laterally adjacent to the first base die, a second metal post 140 (at right) in the molding material, the second metal post laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post, paragraph 25, see also annotated
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[AltContent: textbox (1st base die)][AltContent: textbox (2nd base die)][AltContent: textbox (1st metal post)][AltContent: textbox (2nd metal post)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]Figure 1 below.
[AltContent: textbox (1st base die)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second metal post to be laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post. One would have been motivated to do so in order to interconnect and distribute power throughout the package, paragraph 26.
Koide discloses a semiconductor device package including teaching wherein one of the first chip or the second chip, 30A in Figure 1, has first terminations 32b and second terminations 32a, the second terminations 32a having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the base die, Figure 2 and paragraphs 17,20, and 22. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second terminations to have a pitch less than a pitch of the first terminations, wherein the second terminations are coupled to the die-to-die interconnections of the first base die. One would have been motivated to do so in order to form wiring between chips that is the same as wiring within the chip in order to suppress a decrease in transmission efficiency between chips, paragraphs 27 and 30.
In reference to claim 13, Hung does not disclose the first base die comprises a plurality of through interconnections.
Shen teaches a first base die, 120 in Figure 1, comprising through interconnections 120I, paragraph 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise through interconnections. One would have been motivated to do so in order to allow communication between the chip package with outside devices, paragraph 4.
In reference to claim 15, Hung discloses the first base die is an active die, paragraph 12.
In reference to claim 19, Hung discloses the first chip and the second chip are entirely within a footprint of the first base die, Figure 35A.
In reference to claim 20, Hung discloses the first chip is a first node chip, and the second chip is a second node chip, paragraph 22, the chips of Hung inherently being of a node.
In reference to claim 21, Hung discloses a plurality of conductive interconnections beneath the first base die, paragraph 29.
In reference to claim 22, Hung discloses a multi-chip package, with reference to claim 35B comprising:
a first base die 100 in and contacting a molding material 34, the first base die comprising interconnections, and the first base die comprising active components, paragraph 12;
a first metal post 32 (at left) in and contacting the molding material, the metal post laterally adjacent to the first base die,
a second metal post 32 (at right) in the molding material, paragraph 16;
a first chip 200 electrically coupled to the first base die;
a second chip 200 electrically coupled to the first base die, paragraph 25; and
a dielectric material 56 between and in contact with the first chip and the second chip, paragraph 26.
Hung does not disclose the first base die comprising die-to-die interconnections, the first base die comprising through interconnections,
a second base die in the molding material, the second base die comprising die-to-die interconnections, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die,
the second metal post laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post
the second chip electrically coupled to the first chip by the die-to-die interconnections in the first base die,
wherein one of the first chip or the second chip has first terminations and second terminations, wherein the second terminations have a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the first base die,
the dielectric material in contact with the molding material, or
the dielectric material in contact with the metal post.
Shen discloses a semiconductor chip package including a first base die, ITP 120 in Figure 1, and a second base die, ITP 120, in the molding material (not pictured), the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die, paragraph 4.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second base die to be in the molding material, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, to duplicate the base die of Hung within a single semiconductor device package to expand the number of dies incorporated in the device and, thereby naturally result in the molding material 34 of Hung being located laterally between the second base die and the first base die.
Shen further teaches a first base die ATP 120 comprising die-to-die interconnections 120I, and through interconnections 120I, paragraph 4, a second base die ATP 120 comprising die-to-die interconnections 120I, and a second chip 110 in Figure 1, electrically coupled to the first chip 110 by the die-to-die interconnections 120I in the first base die, paragraph 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise die-to-die interconnections, the first base die to comprise through interconnections, the second base die to comprise die-to-die interconnections, and the second chip to be electrically coupled to the first chip by the die-to-die interconnections in the first base die. One would have been motivated to do so in order to provide an additional interconnect level to supplement other electrical connections, paragraph 5.
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[AltContent: textbox (1st base die)][AltContent: textbox (2nd base die)][AltContent: textbox (1st metal post)][AltContent: textbox (2nd metal post)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]Woychik disclose a semiconductor device package including teaching a first metal post, 140 (at left) in Figure 1, in the molding material 150, the first metal post laterally adjacent to the first base die, a second metal post 140 (at right) in the molding material, the second metal post laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post, paragraph 25, see also annotated Figure 1 below.
[AltContent: textbox (1st base die)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second metal post to be laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post. One would have been motivated to do so in order to interconnect and distribute power throughout the package, paragraph 26.
Koide discloses a semiconductor device package including teaching wherein one of the first chip or the second chip, 30A in Figure 1, has first terminations 32b and second terminations 32a, the second terminations 32a having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the base die, Figure 2 and paragraphs 17,20, and 22. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second terminations to have a pitch less than a pitch of the first terminations, wherein the second terminations are coupled to the die-to-die interconnections of the first base die. One would have been motivated to do so in order to form wiring between chips that is the same as wiring within the chip in order to suppress a decrease in transmission efficiency between chips, paragraphs 27 and 30.
In reference to claim 25, Hung discloses the dielectric material 56 is further along outermost sides of the first chip and the second chip, Figure 35B.
In reference to claims 29 and 30, Hung discloses the first chip and the second chip are entirely within a footprint of the base die, Figure 35A.
In reference to claim 31, Hung discloses the first chip is a first node chip, and the second chip is a second node chip, paragraph 22, the chips of Hung inherently being of a node.
In reference to claim 32, Hung discloses a plurality of conductive interconnections beneath the first base die, paragraph 29.
In reference to claim 33, Hung discloses a multi-chip package, with reference to Figure 35B, comprising:
a first base die 100 having a top surface, a bottom surface, a first side and a second side, the second side opposite the first side, the first base die comprising interconnections, paragraph 12;
a molding material 34 laterally adjacent to the first base die, the molding material in direct contact with the first side and the second side of the first base die;
a first metal post 32 (at left) in and in direct contact with the molding material, the first metal post laterally spaced apart from the first side of the first base die,
a second metal post 32 (at right) in and in direct contact with the molding material, paragraph 16;
a first chip 200 electrically coupled to the first base die;
a second chip 200 electrically coupled to the first base die, paragraph 25; and
a dielectric material 56 between and in contact with the first chip and the second chip, paragraph 26.
Hung does not disclose the first base die comprising die-to-die interconnections, the first base die comprising through interconnections,
a second base die laterally spaced apart from the first base die, the second base die comprising die-to-die interconnections,
the molding material laterally adjacent to the first base die and the second base die, and in direct contact with the second base die, wherein the molding material is laterally between the second base die and the first base die,
the second metal post laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post,
the second chip electrically coupled to the first chip by the die-to-die interconnections in the base die,
wherein one of the first chip or the second chip has first terminations and second terminations, wherein the second terminations have a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the base die,
the dielectric material in contact with the molding material, or
the dielectric material in contact with the metal post.
Shen discloses a semiconductor chip package including a first base die, ITP 120 in Figure 1, and a second base die, ITP 120, in the molding material (not pictured), the second base die laterally spaced apart from the second side of the first base die, and the molding material is laterally adjacent to the first base die and the second base die, the molding material in direct contact with the second base die, wherein the molding material is laterally between the second base die and the first base die, paragraph 4.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second base die to be in the molding material, the second base die laterally spaced apart from the second side of the first base die, and the molding material to be laterally adjacent to the first base die and the second base die, the molding material in direct contact with the second base die, wherein the molding material is laterally between the second base die and the first base die. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, to duplicate the base die of Hung within a single semiconductor device package to expand the number of dies incorporated in the device and, thereby naturally result in the molding material 34 of Hung being in direct contact with the second base die and located laterally between the second base die and the first base die.
Shen further teaches a first base die ATP 120 comprising die-to-die interconnections 120I, and through interconnections 120I, paragraph 4, a second base die ATP 120 comprising die-to-die interconnections 120I, and a second chip 110 in Figure 1, electrically coupled to the first chip 110 by the die-to-die interconnections 120I in the first base die, paragraph 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise die-to-die interconnections, the first base die to comprise through interconnections, the second base die to comprise die-to-die interconnections, and the second chip to be electrically coupled to the first chip by the die-to-die interconnections in the first base die. One would have been motivated to do so in order to provide an additional interconnect level to supplement other electrical connections, paragraph 5.
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[AltContent: textbox (1st base die)][AltContent: textbox (2nd base die)][AltContent: textbox (1st metal post)][AltContent: textbox (2nd metal post)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]Woychik disclose a semiconductor device package including teaching a first metal post, 140 (at left) in Figure 1, in the molding material 150, the first metal post laterally adjacent to the first base die, a second metal post 140 (at right) in the molding material, the second metal post laterally spaced apart from the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post, paragraph 25, see also annotated Figure 1 below.
[AltContent: textbox (1st base die)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second metal post to be laterally spaced apart from the second base die, wherein the first base die and the second base die are laterally between the first metal post and the second metal post. One would have been motivated to do so in order to interconnect and distribute power throughout the package, paragraph 26.
Koide discloses a semiconductor device package including teaching wherein one of the first chip or the second chip, 30A in Figure 1, has first terminations 32b and second terminations 32a, the second terminations 32a having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the base die, Figure 2 and paragraphs 17,20, and 22. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second terminations to have a pitch less than a pitch of the first terminations, wherein the second terminations are coupled to the die-to-die interconnections of the first base die. One would have been motivated to do so in order to form wiring between chips that is the same as wiring within the chip in order to suppress a decrease in transmission efficiency between chips, paragraphs 27 and 30.
In reference to claim 34, Hung discloses the first base die comprises active components, paragraph 12.
In reference to claim 37, Hung discloses the dielectric material 56 is further along outermost sides of the first chip and the second chip, Figure 35B.
In reference to claims 41 and 42, Hung discloses the first chip and the second chip are entirely within a footprint of the first base die, Figure 35A.
In reference to claim 43, Hung discloses the first chip is a first node chip, and the second chip is a second node chip, paragraph 22, the chips of Hung inherently being of a node.
In reference to claim 44, Hung discloses a plurality of conductive interconnections beneath the first base die, paragraph 29.
Claim 12, 26, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Shen et al. (US 2015/0327367), Koide et al. (US 2011/0089579) and Woychik et al. (US 2016/0049383), as applied to claims 11, 22, and 33 above and further in view of Huang et al. (US 2017/0250139).
In reference to claims 12, 26, and 38, Hung does not disclose the first metal post is a first fiducial and the second metal post is a second fiducial.
Huang discloses a chip package including teaching a first metal post, 32A in Figures 4A, 4B, and 5, is a first fiducial, and a second metal post 32A, see especially Figure 4B, is a second fiducial, paragraphs 18, 19, and 25. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first metal post to be a first fiducial and the second metal post to be a second fiducial. One would have been motivated to do so in order to have an alignment mark for aligning the placement of dies in the chip package, paragraph 25.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Shen et al. (US 2015/0327367), Koide et al. (US 2011/0089579), and Woychik et al. (US 2016/0049383) as applied to claim 11 above and further in view of Brothers et al. (US 2013/0141442).
In reference to claim 14, Hung does not disclose the first base die is a passive die.
Brothers teaches a base die, 30 in Figure 3 that is a passive die, paragraphs 24 and 25 (“interposer” as opposed to an “integrated circuit”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to be a passive die. To do so would merely be to apply a variation of known work in a related field to achieve predictable results based on design incentives, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case to mount, connect, and route signals in order to satisfy the communication requirements between dies.
Claims 17, 18, 23, 24, 35, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Shen et al. (US 2015/0327367), Koide et al. (US 2011/0089579), and Woychik et al. (US 2016/0049383), as applied to claims 11, 22, and 33 above and further in view of Yeh et al. (US 2017/0125376).
In reference to claims 17 and 18, Hung does not disclose the dielectric material has an upper surface co-planar with an upper surface of the first chip or the upper surface of the dielectric material is co-planar with an upper surface of the second chip.
Yeh discloses a chip package including teaching a dielectric material, 120 in Figure 6, having an upper surface co-planar with an upper surface of the first chip 102B and an upper surface of the second chip. 102C, paragraph 35. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric material to have an upper surface co-planar with an upper surface of the first chip and the upper surface of the dielectric material to be co-planar with an upper surface of the second chip. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case substituting one dielectric layer configuration for another as suggested by Yeh, paragraph 35.
In reference to claims 23 and 24, Hung does not disclose the dielectric material has an upper surface co-planar with an upper surface of the first chip or the upper surface of the dielectric material is co-planar with an upper surface of the second chip.
Yeh discloses a chip package including teaching a dielectric material, 120 in Figure 6, having an upper surface co-planar with an upper surface of the first chip 102B and an upper surface of the second chip. 102C, paragraph 35. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric material to have an upper surface co-planar with an upper surface of the first chip and the dielectric material to be co-planar with an upper surface of the second chip. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case substituting one dielectric layer configuration for another as suggested by Yeh, paragraph 35.
In reference to claims 35 and 36, Hung does not disclose the dielectric material has an upper surface co-planar with an upper surface of the first chip or the upper surface of the dielectric material is co-planar with an upper surface of the second chip.
Yeh discloses a chip package including teaching a dielectric material, 120 in Figure 6, having an upper surface co-planar with an upper surface of the first chip 102B and an upper surface of the second chip. 102C, paragraph 35. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric material to have an upper surface co-planar with an upper surface of the first chip and the dielectric material to be co-planar with an upper surface of the second chip. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case substituting one dielectric layer configuration for another as suggested by Yeh, paragraph 35.
Conclusion
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897