Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 5-9, 11, 13, 14, and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 4-9, and 11-13 of U.S. Patent No. 20230197777 A1. Although the claims at issue are not identical, they are not patentably distinct from each other because they recite the same.
The Instant Application
US 20230197777 A1
1. An integrated circuit comprising:
a first semiconductor device having one or more first semiconductor bodies extending in a first direction between a first source or drain region and a second source or drain region;
a second semiconductor device having one or more second semiconductor bodies extending in the first direction between a third source or drain region and a fourth source or drain region, the one or more first semiconductor bodies spaced vertically from the one or more second semiconductor bodies in a second direction different from the first direction, the third source or drain region spaced vertically from the first source or drain region in the second direction;
a first insulator
[[and]] a second insulator layer contacting a top surface of the third source or drain region;
And
a conductive contact extending through an entire thickness of the third source or drain region and at least a portion of a thickness of the first source or drain region,
If the conductive contact passes through an insulator layer, it must touch the first source or drain region.
wherein the conductive contact has a same material composition present throughout an entire body of the conductive contact, and wherein the conductive contact directly contacts a portion of the third source or drain region and a portion of the first source or drain region,
It is obvious to one of ordinary skill in the art to have a conductive contact that has a same material composition throughout. Further, if the conductive contact passes through a third source or drain region, one of ordinary skill in the art would reasonably expect the conductive contact to touch the third source or drain region.
and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer.
1. An integrated circuit, comprising:
a first semiconductor device having one or more first semiconductor nanoribbons extending in a first direction between a first source or drain region and a second source or drain region;
a second semiconductor device having one or more second semiconductor nanoribbons extending in the first direction between a third source or drain region and a fourth source or drain region, wherein the one or more second semiconductor nanoribbons are spaced vertically from the one or more first semiconductor nanoribbons in a second direction different from the first direction, and the third source or drain region is spaced vertically from the first source or drain region in the second direction;
an insulator layer between the first source or drain region and the third source or drain region;
a conductive fill comprising a metal and contacting at least a portion of the first source or drain region and at least a portion of the insulator layer;
(See rejection below)
and a conductive contact that extends through a thickness of the third source or drain region and contacts a portion of the conductive fill.
5. The integrated circuit of claim 1, wherein the conductive contact extends through an entire thickness of the insulator layer.
(See rejection below)
3. (Original) The integrated circuit of claim 1, wherein the conductive contact comprises any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co).
4. The integrated circuit of claim 1, wherein the conductive contact comprises any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co).
5. (Original) The integrated circuit of claim 1, wherein the third source or drain region includes one or more first regions that contact corresponding second semiconductor bodies and a second region that contacts each of the one or more first regions, wherein the second region has a higher dopant concentration than each of the one or more first regions.
6. The integrated circuit of claim 1, wherein the third source or drain region includes one or more first regions that contact corresponding second semiconductor nanoribbons and a second region that contacts each of the one or more first regions, wherein the second region has a higher dopant concentration than each of the one or more first regions.
6. (Currently Amended) The integrated circuit of claim 5, wherein the conductive contact does not contact any of the one or more first regions
7. The integrated circuit of claim 6, wherein the conductive contact does not contact any of the one or more first regions.
8. (Original) A printed circuit board comprising the integrated circuit of claim 1.
8. A printed circuit board comprising the integrated circuit of claim 1.
9. (Original) An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having one or more first semiconductor nanoribbons extending in a first direction between a first source or drain region and a second source or drain region;
a second semiconductor device having one or more second semiconductor nanoribbons extending in the first direction between a third source or drain region and a fourth source or drain region, the one or more first semiconductor nanoribbons spaced vertically from the one or more second semiconductor nanoribbons in a second direction different from the first direction, the third source or drain region spaced vertically from the first source or drain region in the second direction;
a first insulator
[[and]] a second insulator layer contacting a top surface of the third source or drain region; and
a conductive contact extending through an entire thickness of the third source or drain region and at least a portion of a thickness of the first source or drain region,
If the conductive contact passes through an insulator layer, it must touch the first source or drain region.
wherein the conductive contact has a same material composition present throughout an entire body of the conductive contact, and wherein the conductive contact directly contacts a portion of the third source or drain region and a portion of the first source or drain region,
It is obvious to one of ordinary skill in the art to have a conductive contact that has a same material composition throughout. Further, if the conductive contact passes through a third source or drain region, one of ordinary skill in the art would reasonably expect the conductive contact to touch the third source or drain region
and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer.
9. An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having one or more first semiconductor nanoribbons extending in a first direction between a first source or drain region and a second source or drain region;
a second semiconductor device having one or more second semiconductor nanoribbons extending in the first direction between a third source or drain region and a fourth source or drain region, wherein the one or more second semiconductor nanoribbons are spaced vertically from the one or more first semiconductor nanoribbons in a second direction different from the first direction, and the third source or drain region is spaced vertically from the first source or drain region in the second direction;
an insulator layer between the first source or drain region and the third source or drain region;
a conductive fill comprising a metal and contacting at least a portion of the first source or drain region and at least a portion of the insulator layer;
(See rejection below)
and a conductive contact that extends through a thickness of the third source or drain region and contacts a portion of the conductive fill.
12. The electronic device of claim 9, wherein the conductive contact extends through an entire thickness of the insulator layer.
(See rejection below)
11. (Currently Amended) The electronic device of claim 9, wherein the conductive contact comprises any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co).
The listed metals are refractory metals
11. The electronic device of claim 9, wherein the conductive contact comprises a refractory metal.
13. (Currently Amended) The electronic device of claim 9, wherein the third source or drain region includes one or more first regions that contact corresponding second semiconductor nanoribbons and a second region that contacts each of the one or more first regions, wherein the second region has a higher dopant concentration than each of the one or more first regions.
13. The electronic device of claim 9, wherein the third source or drain region includes one or more first regions that contact corresponding second semiconductor nanoribbons and a second region that contacts each of the one or more first regions, wherein the second region has a higher dopant concentration than each of the one or more first regions.
14. (Currently Amended) The electronic device of claim 13, wherein the conductive contact does not contact any of the one or more first regions.
14. The electronic device of claim 13, wherein the conductive contact does not contact any of the one or more first regions.
16. (Currently Amended) The electronic device of claim 9, further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.
15. The electronic device of claim 9, further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.
17. An integrated circuit comprising:
a first semiconductor device having one or more first semiconductor bodies extending in a first direction between a first source or drain region and a second source or drain region;
a second semiconductor device having one or more second semiconductor bodies extending in the first direction between a third source or drain region and a fourth source or drain region,
the one or more first semiconductor bodies spaced vertically from the one or more second semiconductor bodies in a second direction different from the first direction, the third source or drain region spaced vertically from the first source or drain region in the second direction;
an insulator layer between the first source or drain region and the third source or drain region; and
a conductive contact extending through an entire thickness of the third source or drain region
and at least a portion of a thickness of the first source or drain region,
If the conductive contact passes through an insulator layer, it must touch the first source or drain region.
wherein the conductive contact comprises a conductive layer directly contacting a portion of the third source or drain region and a portion of the first source or drain region, and
a conductive material on the conductive layer, each of the conductive layer and the conductive material consisting of
1. An integrated circuit, comprising:
a first semiconductor device having one or more first semiconductor nanoribbons extending in a first direction between a first source or drain region and a second source or drain region;
a second semiconductor device having one or more second semiconductor nanoribbons extending in the first direction between a third source or drain region and a fourth source or drain region,
wherein the one or more second semiconductor nanoribbons are spaced vertically from the one or more first semiconductor nanoribbons in a second direction different from the first direction, and the third source or drain region is spaced vertically from the first source or drain region in the second direction;
an insulator layer between the first source or drain region and the third source or drain region;
a conductive fill comprising a metal and contacting at least a portion of the first source or drain region and at least a portion of the insulator layer;
and a conductive contact that extends through a thickness of the third source or drain region and contacts a portion of the conductive fill.
5. The integrated circuit of claim 1, wherein the conductive contact extends through an entire thickness of the insulator layer.
(See rejection below)
18. (Currently Amended) The integrated circuit of claim 17, wherein the refractory metal is any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co).
4. The integrated circuit of claim 1, wherein the conductive contact comprises any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co).
Regarding Claim 1,
US 20230197777 A1 does not explicitly teach:
““[[and]] a second insulator layer contacting a top surface of the third source or drain region, and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer”
However, US 20230197777 A1/Pillarisetty et al (US 20140035041 A1) together teach,
““[[and]] a second insulator layer (Pillarisetty: second ILD layer 170, [0117], FIG. 3: 170 has been planarized. 170 electrically isolates and physically protects the contacts 119,11, 117 and 125.) contacting a top surface of the third source or drain region (US 20230197777 A1/Pillarisetty: One of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38.) and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer (Pillarisetty: [0117], FIG. 3: The contacts are formed in trenches formed in 170. Since 170 is planarized, the top of the contacts share this planarized surface with 170.).”
It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of US 20230197777 A1 is modifiable in view of Pillarisetty et al.
This is because One of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38. Further, the planarized ILD layer 170, after etching, acts as a mold for the formation of the contacts. One of ordinary skill in the art would recognize that such molds allow for the contacts to be formed according to precise dimensions while isolating the contacts at the same time. This is beneficial because forming contacts with similar intended dimensions reduces manufacturing errors which may render the semiconductor device faulty.
Regarding Claim 9,
US 20230197777 A1 does not explicitly teach:
“a second insulator layer contacting a top surface of the third source or drain region; and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer).”
However, US 20230197777 A1/Pillarisetty et al teaches,
“a second insulator layer (Pillarisetty: second ILD layer 170, [0117], FIG. 3: 170 has been planarized. 170 electrically isolates and physically protects the contacts 119, 115, 117 and 125.) contacting a top surface of the third source or drain region (US 20230197777 A1 /Pillarisetty: One of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38.); and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer (Pillarisetty: [0117], FIG. 3: The contacts are formed in trenches formed in 170. Since 170 is planarized, the top of the contacts share this planarized surface with 170.).”
It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of US 20230197777 A1 is modifiable in view of Pillarisetty et al.
This is because One of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38. Further, the planarized ILD layer 170, after etching, acts as a mold for the formation of the contacts. One of ordinary skill in the art would recognize that such molds allow for the contacts to be formed according to precise dimensions while isolating the contacts at the same time. This is beneficial because forming contacts with similar intended dimensions reduces manufacturing errors which may render the semiconductor device faulty.
Regarding Claim 17,
US 20230197777 A1 does not explicitly teach:
“each of the conductive layer and the conductive material consisting of
However, Wu et al (US 20200043858 A1) teaches,
“each of the conductive layer and the conductive material consisting of (Wu: [0041], [0045], FIG. 14: The conductive contact and the barrier layer may both consist of cobalt.)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of US 20230197777 A1 is modifiable in view of Wu.
US 20230197777 A1 is modifiable in view of Wu because one of ordinary skill in the art would recognize that the barrier layer of Wu would improve the invention of US 20230197777 A1 as the material of barrier layer 760 helps to prevent leakage or diffusion, and enhances electrical conductivity. Therefore, one of ordinary skill in the art would consider it obvious to have a conductive layer and a conductive material both made of cobalt.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, and 7 are rejected under 35 U.S.C. 103 as being anticipated by Zhang et al (US 20190131396 A1) in view of Pillarisetty et al (US 20140035041). Zhang et al and Pillarisetty et al will be referenced to as Zhang and Pillarisetty respectively henceforth.
Regarding Claim 1,
Zhang teaches:
“An integrated circuit comprising: a first semiconductor device (pFET S/D device region, [0076], FIG. 14) having one or more first semiconductor bodies (semiconductor channel material nanosheet 14P #2, [0082], annotated FIG. 14 #1) extending in a first direction (annotated FIG. 14 #1, the first direction is horizontal in FIG. 14) between a first source or drain region (pFET S/D region 22S #1, [0091], annotated FIG. 14 #1) and a second source or drain region (pFET S/D region 22S #2, [0091], annotated FIG. 14 #1);
a second semiconductor device (nFET device, [0006], FIG. 14) having one or more second semiconductor bodies (semiconductor channel material nanosheet 14P #1, [0082], annotated FIG. 14 #1) extending in the first direction (FIG. 14) between a third source or drain region (nFET S/D region 26S #1, [0084], annotated FIG. 14 #1) and a fourth source or drain region (nFET S/D region 26S#1, [0084], annotated FIG. 14 #1), the one or more first semiconductor bodies spaced vertically from the one or more second semiconductor bodies (FIG. 14) in a second direction different from the first direction (FIG. 14: the second direction is taken to be the vertical direction in FIG. 14.), the third source or drain region spaced vertically from the first source or drain region in the second direction (FIG. 14);
a first insulator (silicon dioxide layer 24, [0060], FIG. 14: silicon dioxide is an insulator.) between the first source or drain region and the third source or drain region (FIG. 14: 24 is between 26S and 22S);
; and
a conductive contact extending through an entire thickness of the third source or drain region and at least a portion of a thickness of the first source or drain region (S/D contact structures 36, [0085], FIG. 14: 36 passes through the nFET and part of the pFET.), wherein the conductive contact has a same material composition present throughout an entire body of the conductive contact ([0086]: The contact structure includes a metal such as tungsten (W), The metal is deposited. Given the fact that the metal is deposited, few if any impurities should enter the contact structure. Therefore, the contact structure is made of a same material throughout the body of the conductive contact.), and wherein the conductive contact directly contacts a portion of the third source or drain region and a portion of the first source or drain region (FIG. 14: 36 is contacting 26S and 22S),”
Zhang doesn’t substantially teach:
“[[and]] a second insulator layer contacting a top surface of the third source or drain region, and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer”
However, Zhang and Pillarisetty together teach:
“[[and]] a second insulator layer (Pillarisetty: second ILD layer 170, [0117], FIG. 3: 170 has been planarized. 170 electrically isolates and physically protects the contacts 119,11, 117 and 125.) contacting a top surface of the third source or drain region (Zhang/Pillarisetty: One of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38.) and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer (Pillarisetty: [0117], FIG. 3: The contacts are formed in trenches formed in 170. Since 170 is planarized, the top of the contacts share this planarized surface with 170.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Zhang is modifiable in view of Pillarisetty.
This is because one of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38. Further, the planarized ILD layer 170, after etching, acts as a mold for the formation of the contacts. One of ordinary skill in the art would recognize that such molds allow for the contacts to be formed according to precise dimensions while isolating the contacts at the same time. This is beneficial because forming contacts with similar intended dimensions reduces manufacturing errors which may render the semiconductor device faulty.
PNG
media_image1.png
759
1252
media_image1.png
Greyscale
Annotated FIG. 14 #1
Regarding Claim 2,
Zhang/Pillarisetty teaches:
“The integrated circuit of claim 1, wherein the one or more first semiconductor bodies and the one or more second semiconductor bodies comprise germanium, silicon, or any combination thereof (Zhang: [0064], [0065]: 26S and 14P typically comprise a same semiconductor material. 26 may comprise silicon. Therefore, 14 P may comprise silicon.).”
Regarding Claim 3,
Zhang/Pillarisetty teaches:
“The integrated circuit of claim 1, wherein the conductive contact comprises any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co) (Zhang: [0086]: 36 can include tungsten.).”
Regarding Claim 7,
Zhang/Pillarisetty teaches:
“The integrated circuit of claim 1, wherein no material gradient is present at a boundary between the conductive contact and the first source or drain region or between the conductive contact and the third source or drain region (Zhang: [0086]: the conductive contact may be made of tungsten. Since tungsten is a refractory material, it does not react with the S/D regions (26S and 22S) around it. Therefore, there is a sharp boundary between the conductive contact, and the S/D regions around it.).”
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Pillarisetty as applied to claims 1, 2, 3, and 7 above, and further in view of Cheng et al (US 20190378764 A1). Chang et al will be referenced to as Chang henceforth.
Regarding Claim 4,
Zhang/Pillarisetty teaches:
“The integrated circuit of claim 1”
Zhang/Pillarisetty doesn’t substantially teach:
“wherein the conductive contact has an aspect ratio between 4:1 and 8:1”
However, Cheng teaches:
“(Cheng: H, W, [0032], [0033], FIG. 2B: Cheng states H may be around 100nm and W may be 15nm. 100/15 = 20/3 which is a ratio of 6 and 2/3 to 1 which lies in Applicant’s range ).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Zhang/Pillarisetty is modifiable in view of Cheng.
This is because Cheng covers an instance within the claimed range of applicant’s invention. By MPEP 2144.05, a prima facie case of obviousness exists because the prior art contains an example within the claim.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Pillarisetty as applied to claims 1, 2, 3, and 7 above, and further in view of Lin et al (US 20220344516 A1). Lin et al will be referenced to as Lin henceforth.
Regarding Claim 5,
Zhang/Pillarisetty teaches:
“The integrated circuit of claim 1”
Zhang/Pillarisetty further teaches:
“second semiconductor bodies (Zhang: semiconductor channel material nanosheet 14P #1, [0082], annotated FIG. 14 #1)”, but not within the context of the claim
Zhang/Pillarisetty doesn’t substantially teach:
“wherein the third source or drain region includes one or more first regions that contact corresponding second semiconductor bodies and a second region that contacts each of the one or more first regions, wherein the second region has a higher dopant concentration than each of the one or more first regions.”
However, Lin teaches:
“wherein the third source or drain region includes one or more first regions (Lin: semiconductor material layer 92A, [0042], FIG. 20B) that contact corresponding second semiconductor bodies (Lin: second nanostructures 54A-C, [0019], FIG. 20B) and a second region that contacts each of the one or more first regions (Lin: second semiconductor material layer 92B, [0042], FIG. 20B), wherein the second region has a higher dopant concentration than each of the one or more first regions (Lin: [0076], FIG. 20B: 92A are the first semiconductor material segments and 92B the second).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Zhang/Pillarisetty is modifiable in view of Lin.
This is because the different doping profiles of the regions of Lin where the second region has a greater doping concentration than the first prevents short current between channels making the device more energy efficient and less prone to defects. This is because with the second region having a greater concentration of dopants, it is easier for current to flow in the second region compared to the first as there are more slots for electrons/holes to be in the second region compared the first making it more probable for electrons/holes to travel to the second region rather than the first.
Regarding Claim 6,
Zhang/Pillarisetty/Lin teaches:
“The integrated circuit of claim 5, wherein the conductive contact does not contact any of the one or more first regions (Lin: FIG. 20B: contact 112 [0074] is not contacting 92A.).”
Claims 8, 9, 10, 11, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Pillarisetty as applied to claims 1, 2, 3, and 7 above, and further in view of Chang et al (US 20170221992 A1). Chang et al will be referenced to as Chang henceforth.
Regarding Claim 8,
Zhang/Pillarisetty teaches:
“the integrated circuit of claim 1”
Zhang/Pillarisetty doesn’t substantially teach:
“A printed circuit board”
However, Zhang/Pillarisetty and Chang together teach:
“A printed circuit board comprising the integrated circuit of claim 1 (Zhang/Chang: [0060]: The integrated circuit of claim 1 as covered by Zhang may be incorporated into a motherboard. A motherboard is a main printed circuit board.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Zhang/Pillarisetty is modifiable in view of Chang.
This is because the invention of Chang teaches that an integrated circuit including a multi-nanosheet device may be incorporated into a printed circuit board (a mother board is just a printed circuit board with parts affixed onto it) for the purpose of forming an intermediate product such as a motherboard. This provides the benefit of using the invention of Zhang in a computing device usable by people.
Regarding Claim 9,
Zhang/Pillarisetty/Chang teaches:
“An electronic device, comprising: a chip package comprising one or more dies (Chang: [0060]), at least one of the one or more dies (Chang: [0060]) comprising a first semiconductor device having one or more first semiconductor nanoribbons (Zhang: semiconductor channel material nanosheet 14P #2, [0082], annotated FIG. 14 #1) extending in a first direction (Zhang: annotated FIG. 14 #1, the first direction is horizontal in FIG. 14) between a first source or drain region (Zhang: pFET S/D region 22S #1, [0091], annotated FIG. 14 #1) and a second source or drain region (Zhang: pFET S/D region 22S #2, [0091], annotated FIG. 14 #1);
a second semiconductor device (Zhang: nFET device, [0006], FIG. 14) having one or more second semiconductor nanoribbons (Zhang: semiconductor channel material nanosheet 14P #1, [0082], annotated FIG. 14 #1) extending in the first direction (Zhang: FIG. 14) between a third source or drain region (Zhang: nFET S/D region 26S #1, [0084], annotated FIG. 14 #1) and a fourth source or drain region (Zhang: nFET S/D region 26S#1, [0084], annotated FIG. 14 #1), the one or more first semiconductor nanoribbons spaced vertically from the one or more second semiconductor nanoribbons in a second direction different from the first direction (Zhang: FIG. 14: the second direction is taken to be the vertical direction in FIG. 14.), the third source or drain region spaced vertically from the first source or drain region in the second direction (Zhang: FIG. 14);
a first insulator (Zhang: silicon dioxide layer 24, [0060], FIG. 14: silicon dioxide is an insulator.) between the first source or drain region and the third source or drain region (Zhang: FIG. 14: 24 is between 26S and 22S);
[[and]] a second insulator layer (Pillarisetty: second ILD layer 170, [0117], FIG. 3: 170 has been planarized. 170 electrically isolates and physically protects the contacts 119, 115, 117 and 125.) contacting a top surface of the third source or drain region (Zhang/Pillarisetty: One of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38.); and a conductive contact extending through an entire thickness of the third source or drain region and at least a portion of a thickness of the first source or drain region (Zhang: S/D contact structures 36, [0085], FIG. 14: 36 passes through the nFET and part of the pFET.), wherein the conductive contact has a same material composition present throughout an entire body of the conductive contact (Zhang: ([0086]: The contact structure includes a metal such as tungsten (W), The metal is deposited. Given the fact that the metal is deposited, few if any impurities should enter the contact structure. Therefore, the contact structure is made of a same material throughout the body of the conductive contact.), and wherein the conductive contact directly contacts a portion of the third source or drain region and a portion of the first source or drain region (Zhang: FIG. 14: 36 is contacting 26S and 22S), and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer (Pillarisetty: [0117], FIG. 3: The contacts are formed in trenches formed in 170. Since 170 is planarized, the top of the contacts share this planarized surface with 170.).”
Regarding Claim 10,
Zhang/Pillarisetty/Chang teaches:
“The electronic device of claim 9, wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons comprise germanium, silicon, or any combination thereof (Zhang: ([0064], [0065]: 26S and 14P typically comprise a same semiconductor material. 26 may comprise silicon. Therefore, 14 P may comprise silicon.).”
Regarding Claim 11,
Zhang/Pillarisetty/Chang teaches:
“The electronic device of claim 9, wherein the conductive contact comprises any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co) (Zhang: [0086]: 36 can include tungsten.).”
Regarding Claim 15,
Zhang/Pillarisetty /Chang teaches:
“The electronic device of claim 9, wherein no material gradient is present at a boundary between the conductive contact and the first source or drain region or between the conductive contact and the third source or drain region (Zhang: [0086]: the conductive contact may be made of tungsten. Since tungsten is a refractory material, it does not react with the S/D regions (26S and 22S) around it. Therefore, there is a sharp boundary between the conductive contact, and the S/D regions around it.).”
Regarding Claim 16,
Zhang/Pillarisetty /Chang teaches:
“The electronic device of claim 9, further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board (Chang: [0060]: The integrated circuit may be incorporated into a motherboard).”
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Pillarisetty /Chang as applied to claims 8, 9, 10, 11, 15 and 16 above, and further in view of Cheng.
Regarding Claim 12,
Zhang/Pillarisetty/Chang teaches:
“The electronic device of claim 9”
Zhang/Pillarisetty/Chang doesn’t substantially teach:
“wherein the conductive contact has an aspect ratio between 4:1 and 8:1.”
However, Cheng teaches:
“wherein the conductive contact has an aspect ratio between 4:1 and 8:1 (Cheng: H, W, [0032], [0033], FIG. 2B: Cheng states H may be around 100nm and W may be 15nm. 100/15 = 20/3 which is a ratio of 6 and 2/3 to 1 which lies in Applicant’s range)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Zhang/Pillarisetty/Chang is modifiable in view of Cheng.
This is because Cheng covers an instance within and the claimed range of applicant’s invention. By MPEP 2144.05, a prima facie case of obviousness exists because the prior art contains an example within the claim.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Pillarisetty/Chang as applied to claims 8, 9, 10, 11, 15, and 16 above, and further in view of Lin.
Regarding Claim 13,
Zhang/Pillarisetty/Chang teaches:
“The electronic device of claim 9”
Zhang/Pillarisetty/Chang doesn’t substantially teach:
“wherein the third source or drain region includes one or more first regions that contact corresponding second semiconductor nanoribbons and a second region that contacts each of the one or more first regions, wherein the second region has a higher dopant concentration than each of the one or more first regions.”
However, Lin teaches:
“wherein the third source or drain region includes one or more first regions (Lin: semiconductor material layer 92A, [0042], FIG. 20B) that contact corresponding second semiconductor nanoribbons (Lin: second nanostructures 54A-C, [0019], FIG. 20B) and a second region that contacts each of the one or more first regions (Lin: second semiconductor material layer 92B, [0042], FIG. 20B), wherein the second region has a higher dopant concentration than each of the one or more first regions (Lin: [0076], FIG. 20B: 92A are the first semiconductor material segments and 92B the second).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Zhang/Pillarisetty/Chang is modifiable in view of Lin.
This is because the different doping profiles of the regions of Lin where the second region has a greater doping concentration than the first region prevents short current between channels making the device more energy efficient and less prone to defects. This is because with the second region having a greater concentration of dopants, it is easier for current to flow in the second region compared to the first as there are more slots for electrons/holes to be in the second region compared the first making it more probable for electrons/holes to travel to the second region rather than the first.
Regarding Claim 14,
Zhang/Pillarisetty/Chang/Lin teaches:
“The electronic device of claim 13, wherein the conductive contact does not contact any of the one or more first regions (Lin: FIG. 20B: contact 112 [0074] is not contacting 92A).”
Claims 17 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Pillarisetty/Chang as applied to claims 8, 9, 10, 11, 15, and 16 above, and further in view of Wu et al (US 20200043858 A1). Wu et al will be referenced to as Wu henceforth.
Regarding Claim 17,
Zhang teaches:
“An integrated circuit comprising: a first semiconductor device having one or more first semiconductor bodies (Zhang: semiconductor channel material nanosheet 14P #2, [0082], annotated FIG. 14 #1) extending in a first direction (Zhang: annotated FIG. 14 #1, the first direction is horizontal in FIG. 14) between a first source or drain region (Zhang: pFET S/D region 22S #1, [0091], annotated FIG. 14 #1) and a second source or drain region (Zhang: pFET S/D region 22S #2, [0091], annotated FIG. 14 #1);
a second semiconductor device (Zhang: nFET device, [0006], FIG. 14) having one or more second semiconductor bodies (Zhang: semiconductor channel material nanosheet 14P #1, [0082], annotated FIG. 14 #1) extending in the first direction (Zhang: FIG. 14) between a third source or drain region (Zhang: nFET S/D region 26S #1, [0084], annotated FIG. 14 #1) and a fourth source or drain region (Zhang: nFET S/D region 26S#1, [0084], annotated FIG. 14 #1), the one or more first semiconductor bodies spaced vertically from the one or more second semiconductor bodies in a second direction different from the first direction (Zhang: FIG. 14: the second direction is taken to be the vertical direction in FIG. 14.), the third source or drain region spaced vertically from the first source or drain region in the second direction (Zhang: FIG. 14);
an insulator layer (Zhang: silicon dioxide layer 24, [0060], FIG. 14: silicon dioxide is an insulator.) between the first source or drain region and the third source or drain region (Zhang: FIG. 14: 24 is between 26S and 22S);
and a conductive contact extending through an entire thickness of the third source or drain region and at least a portion of a thickness of the first source or drain region (Zhang: S/D contact structures 36, [0085], FIG. 14: 36 passes through the nFET and part of the pFET) directly contacting a portion of the third source or drain region and a portion of the first source or drain region (Zhang: FIG. 14: 36 is contacting 26S and 22S)”
Zhang/Pillarisetty doesn’t substantially teach:
“wherein the conductive contact comprises a conductive layer and a conductive material on the conductive layer and having a same refractory metal as the conductive layer”
However, Wu teaches:
“wherein the conductive contact comprises a conductive layer (Wu: barrier layer 760, [0041]], [0045], FIG. 14: 760 may be cobalt.) and a conductive material on the conductive layer (conductive contact 840, [0045], FIG. 14: The conductive contact 840 refers to the conductive material on the barrier layer 760. However, it is also acceptable to refer to 760 as part of 840. 840 may be made of cobalt.), each of the conductive layer and the conductive material consisting of (Wu: [0041], [0045], FIG. 14: The conductive contact and the barrier layer may both consist of cobalt.)
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Zhang/Pillarisetty/Chang is modifiable in view of Wu.
This is because Zhang teaches a conductive contact made of tungsten. Zhang doesn’t substantively teach a conductive contact made of cobalt. Wu teaches a conductive contact made of tungsten. Wu also teaches that a conductive contact may be made of cobalt. Because both Zhang and Wu have a conductive contact made of tungsten, one of ordinary skill in the art would have deemed it obvious to substitute the conductive contact made of tungsten of Zhang for the conductive contact made of cobalt of Wu for the predictable result of a conductive contact with good conductivity.
Further Zhang/Pillarisetty/Chang is modifiable in view of Wu because one of ordinary skill in the art would recognize that the barrier layer of Wu would improve the invention of Zhang/Chang as the material of barrier layer 760 helps to prevent leakage or diffusion, and enhances electrical conductivity. Therefore, one of ordinary skill in the art would consider it obvious to have a conductive layer and a conductive material both made of cobalt.
Regarding Claim 18,
Zhang/Pillarisetty/Chang/Wu teaches:
“The integrated circuit of claim 17, wherein the refractory metal is any one of tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co) (Zhang: [0086]: 36 can include tungsten.).”
Regarding Claim 20,
Zhang/Pillarisetty/Chang/Wu teaches:
“The integrated circuit of claim 17, wherein no material gradient is present at a boundary between the conductive layer and the first source or drain region or between the conductive layer and the third source or drain region (Zhang: [0086]: the conductive contact may be made of tungsten. Since tungsten is a refractory material, it does not react with the S/D regions (26S and 22S) around it. Therefore, there is a sharp boundary between the conductive contact, and the S/D regions around it.).”
Regarding Claim 21,
Zhang/Pillarisetty/Chang/Wu/ teaches:
“The integrated circuit of claim 17, wherein the insulator layer is a first insulator layer (Zhang/Pillarisetty: Zhang: silicon dioxide layer 24, [0060], FIG. 14: silicon dioxide is an insulator: the insulator layer becomes a first insulator layer when second ILD layer of Pillarisetty is introduced.), the integrated circuit further comprising a second insulator layer (Pillarisetty: second ILD layer 170, [0117], FIG. 3: 170 has been planarized. 170 electrically isolates and physically protects the contacts 119, 115, 117 and 125.) contacting a top surface of the third source or drain region (Zhang/Pillarisetty: One of ordinary skill in the art would recognize that the placement of 170 of Pillarisetty over the contacts 36 and 38 and the source/drain regions 26S of Zhang would provide the benefit of electrically isolating and physically protecting the contacts 36 and 38.), and wherein a top surface of the conductive contact is coplanar with a top surface of the second insulator layer (Pillarisetty: [0117], FIG. 3: The contacts are formed in trenches formed in 170. Since 170 is planarized, the top of the contacts share this planarized surface with 170.).”
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 102(a)(1) and 103 rejections.
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Pillarisetty and Wu.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with an amended variation of claim 5 such as:
“wherein the third source or drain region includes one or more first regions which each continuously contact corresponding second semiconductor bodies and a second region that contacts each of the one or more first regions, wherein the second region has a higher dopant concentration than each of the one or more first regions.”
It would overcome the current rejections for claims, 1, 9, and 17. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ who