DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 01/30/2026 has been accepted and entered. Claims 1-7, 11, 13-18, and 21-26 remain pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 11, 13-18, and 21-26 is/ are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (Advanced Materials, Vol. 34, No. 48, 4 December 2021-XuNPL21; NPL from IDS filed on 08/04/2023) in view of Bao et al. (US20150137377A1-Bao77).
Regarding claim 1, XuNPL21 discloses an integrated circuit (IC) device (Title) comprising:
a transistor (Abstract-L4) comprising
a gate (Abstract L3) and
a channel (Abstract L 10); and
a source or drain (S/D) contact (Abstract L2-3)
coupled to the channel (Abstract L 9-10),
the S/D contact comprising a plurality of layers of a material (Ti3C2Tx Mxene layers so a plurality of layers-Abstract L 2-3),
a layer of the material comprising a transition metal (Ti as the transition metal-Abstract L2-3)and
at least one of carbon and nitrogen (Carbon in Ti3C2Tx -Abstract L 2-3).
XuNPL21 does not disclose an integrated circuit (IC) device comprising
a trench interconnect structure coupled to the S/D contact ,
the trench interconnect structure comprising
a plurality of layers of a material,
a layer of the material comprising
a transition metal and
at least one of carbon and nitrogen.
Bao77 teaches an integrated circuit (IC) device comprising
a trench interconnect structure coupled to the S/D contact (trench interconnect structure 36/38/30/28 coupled to S/D contact 16/18, which is connected to macrocell 20; the substrate including at least one transistor with source and drain, so macrocell 20 is connected to a source or drain-[0041] L1-5, [0028], Fig 6),
the trench interconnect structure comprising
a plurality of layers of a material (multilayer of graphene 30, 28, 38, and 36 -[0045] L1-4, Fig 6),
a layer of the material comprising
a transition metal (multilayer of graphene 30, 28, 38, and 36 with 36 being copper, aluminum, silver, gold, calcium, platinum, tin, lithium, zinc, nickel, and tungsten so a transition metal-[0041] L9-16) and
at least one of carbon and nitrogen (multilayer of graphene 30-[0045] L1-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 2, XuNPL21 and Bao77 combination discloses all the elements of claim 1, as noted above.
Bao77 further teaches an integrated circuit (IC) device
wherein the transition metal in the material comprises an element in group 3 through 6 of the periodic table (multilayer of graphene 30, 28, 38, and 36 with 38 being cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride so comprising an element in group 3 through 6 -[0042] L9-16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 3, XuNPL21 and Bao77 combination discloses all the elements of claim 1, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device (Title)
further comprising a second layer formed between two of the plurality of layers (Second layer of element F or O between two of the plurality of layers Ti3C2Tx or Layer of Carbon between two of layers of titanium-Fig 1b),
the second layer comprising a main group element (Second layer of element F or O between two of the plurality of layers Ti3C2Tx or Layer of element Carbon between two of the plurality of layers of titanium-Fig 1b, Page 2 [2.1] L20-22; Page 3 L1-2).
Regarding claim 4, XuNPL21 and Bao77 combination discloses all the elements of claim 3, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device (Title)
wherein the main group element is in one of group 13 or group 14 of the periodic table (Carbon is an element of group 14; Layer of Carbon between layers of titanium-Page 2 [2.1] L20-22; Fig 1b).
Regarding claim 5, XuNPL21 and Bao77 combination discloses all the elements of claim 1, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device (Title)
wherein the channel comprises a transition metal dichalcogenide (TMD) (MoS2 channel so TMD-Abstract L9-10).
Regarding claim 11, XuNPL21 and Bao77 combination discloses all the elements of claim 1, as noted above.
Bao77 further teaches an integrated circuit (IC) device
wherein the trench interconnect structure comprises
a liner (38/30/28-Fig 6) and
a fill region (36-Fig 6),
the liner between the S/D contact and the fill region (liner 38/30/28 between S/D contact 16 and fill region 36-Fig 6),
wherein the liner comprises the plurality of layers of the material (multilayer of graphene 30, 28, and 38 -[0045] L1-4, Fig 6) and
the fill region comprises a metal (36 being copper, aluminum, silver, gold, calcium, platinum, tin, lithium, zinc, nickel, and tungsten so a transition metal-[0041] L9-16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 13, XuNPL21 discloses an integrated circuit (IC) device (Title) comprising:
a transistor (Abstract-L4) comprising
a gate (Abstract L3) and
a channel (Abstract L 10); and
a source or drain (S/D) contact (Abstract L2-3) coupled to the channel (Abstract L 9-10), and
an interconnect region coupled to the S/D contact (Top half of Ti3C2Tx connected to Bottom half of Ti3C2Tx S/D contact-Fig 4b),
the interconnect region comprising a plurality of layers of a material (Ti3C2Tx Mxene layers so a plurality of layers-Abstract L 2-3, Fig 4b),
a layer of the material comprising a transition metal (Ti3C2Tx comprising Ti as the transition metal-Abstract L2-3) and
at least one of carbon and nitrogen (Carbon in Ti3C2Tx -Abstract L 2-3).
XuNPL21 does not disclose an integrated circuit (IC) device
wherein the interconnect region is one of a trench structure or a via structure,
Bao77 teaches an integrated circuit (IC) device
wherein the interconnect region is one of a trench structure or a via structure, (interconnect region 30/28/36/38 being a trench 26-Fig 2, Fig 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 14, XuNPL21 and Boa77 combination discloses all the elements of claim 13, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device (Title)
wherein the transition metal in the material comprises an element in group 3 through 6 of the periodic table (Ti is an element in group 4 so in group 3 through 6).
Regarding claim 15, XuNPL21 and Bao77 combination discloses all the elements of claim 13, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device (Title)
wherein the interconnect region extends in a direction substantially parallel to a support structure (Top half of Ti3C2Tx layers extending horizontally and parallel to support-Fig 1a, Fig 1f, Fig 4b), and the plurality of layers are arranged in the direction substantially parallel to the support structure (Ti3C2Tx layers are vertically stacked so parallel to the support in a direction perpendicular to the support-Fig 4b).
Regarding claim 16, XuNPL21 and Bao77 combination discloses all the elements of claim 13, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device (Title)
wherein the interconnect region extends in a direction substantially perpendicular to a support structure (Top half of Ti3C2Tx layers are vertically stacked so parallel to the support in a direction perpendicular to the support-Fig 4b), and
the plurality of layers are arranged in the direction substantially perpendicular to the support structure (Ti3C2Tx layers are vertically stacked so parallel to the support in a direction perpendicular to the support-Fig 4b).
Regarding claim 17, XuNPL21 and Bao77 combination discloses all the elements of claim 16, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device (Title)
wherein the interconnect region is a first interconnect region (Top half of Ti3C2Tx layers has been interpretated as a first interconnect region-Fig 4b),
the IC device further comprising a second interconnect region (Bottom half of Ti3C2Tx layers has been interpretated as the second interconnect region-Fig 4b),
wherein the second interconnect region extends in a direction substantially parallel to the support structure (Bottom half of Ti3C2Tx layers has been interpretated as the second interconnect region, layers are vertically stacked so parallel to the support in a direction perpendicular to the support-Fig 4b), and
the plurality of layers are arranged in the direction substantially parallel to the support structure ( Ti3C2Tx layers are vertically stacked on the support so parallel to the support in a direction perpendicular to the support-Fig 1f, Fig 4b).
Regarding claim 18, XuNPL21 and Bao77 combination discloses all the elements of claim 13, as noted above.
Bao77 further teaches an integrated circuit (IC) device
further comprising a metal interconnect coupled to the interconnect region (metal interconnect vertical 230/228 coupled with interconnect region horizontal 214/220/228/230-Fig 12, [0076]),
wherein the interconnect region forms a liner between the metal interconnect and the S/D contact (interconnect region horizontal 214/220/228/230 forming a liner between the metal interconnect vertical 230/228 and the S/D contact 212-Examiner’s annotated Fig 12, [0076]),.
Regarding claim 21, XuNPL21 and Bao77 discloses all the elements of claim 11, as noted above.
Bao77 further teaches an integrated circuit (IC) device
wherein the liner (228/214/220-Fig 12) has a thickness of less than 2 nanometers (liner 228 having a thickness of 1nm so being less than 2nm-[0068] L12-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 22, XuNPL21 and Bao77 discloses all the elements of claim 13, as noted above.
Bao77 further teaches an integrated circuit (IC) device
wherein the plurality of layers of the material are a liner (liner 38,30.28-Fig 6),
the interconnect region further comprising a metal fill (metal fill 36, 36 being copper, aluminum, silver, gold, calcium, platinum, tin, lithium, zinc, nickel, and tungsten so a transition metal-[0041] L9-16, Fig 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 23, XuNPL21 and Bao77 discloses all the elements of claim 22, as noted above.
Bao77 further teaches an integrated circuit (IC) device
wherein the liner has a thickness of less than 5 nanometers (liner 228/214/220 with 228 having a thickness of 1nm so being less than 5 nm-[0068] L12-14, Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 24, XuNPL21 and Bao77 discloses all the elements of claim 13, as noted above.
Bao77 further teaches an integrated circuit (IC) device
wherein the interconnect region (214/220/228/230-Fig 12) is a first interconnect region (first interconnect region 214/220/228/230-Fig 12),
the IC device further comprising a second interconnect region (Second interconnect region 236/232/234-Fig 12),
wherein the second interconnect region extends in a direction substantially perpendicular to the first interconnect region (Second interconnect region 236/232/234 being substantially perpendicular to 230/228 of first interconnect region 214/220/228/230 -Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 25, XuNPL21 and Bao77 discloses all the elements of claim 24, as noted above.
Bao77 further teaches an integrated circuit (IC) device further comprising
a third interconnect region (cap layer 232/236-Fig 12) comprising a metal (236 comprising Palladium-[0075] L6),
wherein the first interconnect region and the second interconnect region are coupled to the third interconnect region (cap layer 232/236 coupled with Second interconnect region 236/232/234 and First interconnect region 214/220/228/230-Fig 12, [0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
Regarding claim 26, XuNPL21 and Bao77 discloses all the elements of claim 13, as noted above.
Bao77 further teaches an integrated circuit (IC) device
wherein a first layer of the material comprising the transition metal and at least one of carbon and nitrogen is directly over a second layer of the material (First layer of the material/top dashed line rectangle comprising metal from 230/220 and carbon from multi-layer graphene 214 is over a second layer of the same material-Examiner's annotated Fig 12, [0062] L1-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21, as taught by Bao77 for the purpose of lowering the contact resistance where the graphene intersects with the metal (Bao77:[0054]).
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Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (Advanced Materials, Vol. 34, No. 48, 4 December 2021-XuNPL; NPL from IDS filed on 08/04/2023) in view of Bao et al. (US20150137377A1-Bao77), and further in view of Cheng et al. (US 20210066627-Cheng27).
Regarding claim 6, XuNPL21 and Bao77 combination discloses all the elements of claim 1, as noted above.
XuNPL21 and Bao77 combination does not disclose an integrated circuit (IC) device
wherein the channel comprises at least one nanoribbon formed over a support structure ,
wherein the at least one nanoribbon extends in a direction substantially parallel to the support structure.
Cheng27 teaches an integrated circuit (IC) device
wherein the channel comprises at least one nanoribbon formed over a support structure (nanoribbons 24-1 over support 20-See Examiner's annotated Fig 9B),
wherein the at least one nanoribbon extends in a direction substantially parallel to the support structure (24-1 is parallel to support structure 20 in the horizontal direction-Examiner's annotated Fig 9B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit (IC) device of XuNPL21 in view of Bao77, as taught by Cheng27 for the purpose of improving the device uniformity throughout wafer (Cheng27: [0039] L17-18).
Regarding claim 7, XuNPL21, Bao77, and Cheng27 combination discloses all the elements of claim 6, as noted above.
XuNPL21 further discloses an integrated circuit (IC) device
wherein a layer of the material extends in a direction substantially parallel to the at least one nanoribbon (Layer of carbon extends horizontally and substantially parallel to the channel MoS2-Fig 4b).
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Response to Arguments
Applicant’s arguments, see pages 6-7 of Remarks, filed on 01/30/2026 with respect to Claims 1-7, 11, 13-18, and 21-26 have been fully considered and are persuasive, however, the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claim(s) 1-5, 11, 13-18, and 21-26 is/ are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (Advanced Materials, Vol. 34, No. 48, 4 December 2021-XuNPL21; NPL from IDS filed on 08/04/2023) in view of Bao et al. (US20150137377A1-Bao77).
Therefore, claim(s) 1-5, 11, 13-18, and 21-26 stand rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (Advanced Materials, Vol. 34, No. 48, 4 December 2021-XuNPL21; NPL from IDS filed on 08/04/2023) in view of Bao et al. (US20150137377A1-Bao77).
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (Advanced Materials, Vol. 34, No. 48, 4 December 2021-XuNPL; NPL from IDS filed on 08/04/2023) in view of Bao et al. (US20150137377A1-Bao77), and further in view of Cheng et al. (US 20210066627-Cheng27).
Therefore, claim(s) 6-7 stand rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (Advanced Materials, Vol. 34, No. 48, 4 December 2021-XuNPL; NPL from IDS filed on 08/04/2023) in view of Bao et al. (US20150137377A1-Bao77), and further in view of Cheng et al. (US 20210066627-Cheng27).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sen Gupta et al. (US 20230102219 A1) teaches an integrated circuit (IC) device comprising a transistor(100-fig 1) comprising a gate (104-Fig 1) and a channel (103); and a source or drain (S/D) contact coupled to the channel (112a/b coupled to channel ([0015]); and a trench interconnect structure coupled to the S/D contact (1636-Fig 8), with S/D contact containing carbon (Title).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 03/06/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812