DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 03 September 2025, with respect to drawings objections have been fully considered and are persuasive. Examiner finds Figs. 9 and 10 of the instant application to overcome the issues raised in the objections. The drawings objections of previous office action has been withdrawn.
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the new ground of rejection that rely on Ashrafzadeh (US 20140312458 A1) as an added secondary reference to teach the added claim limitations.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: claim 15 recites a through-silicon via whereas paragraph [0025] of the specification recites a through-substrate via. Examiner encourages applicant to either amend the claims and/or the specifications in order for claim terms to be consistent with the specification. For the purpose of compact prosecution, the examiner will find art that teaches a through substrate via.
Claim Objections
Claim 15 is objected to because of the following informalities: a through-silicon via couple [sic: coupled] to the first transformer coil or second transformer coil. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210335690 A1) and further in view of Saraswat (US 20130335059 A1), Fajardo (US 20080075974 A1), and Ashrafzadeh (US 20140312458 A1).
Regarding claim 1, Huang teaches an integrated circuit (IC) device (Figs. 30A-30C, [0002]-[0003]), comprising:
a support structure (Fig. 30B, [0067]: 115 is a device layer having transistors, analogous to Applicant’s definition in Specification ¶ 0044) having a first surface (bottom surface of 115) and a second surface (top surface of 115) opposing the first surface;
a first inductor (Figs. 30B & 28, [0086]: right 140: “ the conductive features 140 comprise a metal-insulator-metal (MIM) inductor 140’… ”) over the support structure (Fig. 30B shows 140 over 115), the first inductor being closer to the second surface than the first surface (Fig. 30B shows right 140 closer to the top surface of 115 than to the bottom surface of 115);
a second inductor (Figs. 30B & 28, [0086]: left 140: “ the conductive features 140 comprise a metal-insulator-metal (MIM) inductor 140’… ”) over the support structure (Fig. 30B shows 140 over 115), the second inductor being closer to the second surface than the first surface (Fig. 30B shows left 140 closer to the top surface of 115 than to the bottom surface of 115);
a semiconductor device (Fig. 30B, [0078]: 55&102 are gate structures) over or at least partially in the support structure (BRI: 55&102 are within 115, hence it is at least partially in 115), the semiconductor device coupled to the first inductor or the second inductor (Fig. 30B, [0046]-[0052], [0083]-[0086]: gate structures 55&102 are coupled with source/drains 92; 92 are coupled to 140 through 130&129 and 134) and being closer to the first surface than the second surface (Fig. 30B shows 102 and/or bottom-most 55 closer to bottom of 115 than to the top of 115);
a first via (Fig. 30B, [0081], 130&129) at least partially in the support structure (Fig. 30B shows 129 extending vertically into 92, which is part of 115) and a second via (Figs. 30B & 30C & [0081] describes a plurality of contacts 130&129 connected to each source/drain 92 ) at least partially in the support structure (Fig. 30B shows 129 extending vertically into 92, which is part of 115), wherein the first via and the second via are connected to the first inductor (Fig. 28 and [0083]-[0086] shows 130&129 are connected to 140 through 134 & 142) ; and
a third via (Fig. 30B & [0081] describes a plurality of contacts 130&129 connected to each source/drain 92) at least partially in the support structure (Fig. 30B shows 129 extending vertically into 92, which is part of 115) and a fourth via (Fig. 30B & [0081] describes a plurality of contacts 130&129 connected to each source/drain 92; also Figs. 1-6B & [0019] describe a plurality of source/drains for multiple FET types 50N and 50P ) at least partially in the support structure (Fig. 30B shows 129 extending vertically into 92, which is part of 115), wherein the third via and the fourth via are connected to the second transformer coil (Fig. 28 and [0083]-[0086] shows 130&129 are connected to 140 through 132/134/136).
However, Huang does not teach the first inductor and the second inductor are made of coils.
Saraswat, in the same field of invention, teaches an integrated circuit device (Fig. 3, abstract) with an inductor (Fig. 3, [0019]: 331) is made of at least one coil ([0019]: 332 or 334).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Saraswat into the integrated circuit device of Huang to use at least one coil in making inductors in an integrated device at least comprising of a support structure, a semiconductor device at least partially in the support structure, a first inductor and a second inductor over the support structure, with either the first inductor or second inductor coupled to the semiconductor device. The ordinary artisan would have been motivated to modify Huang in the manner set forth above for at least the purpose of designing a multi-stack integrated circuit architecture with an integrated voltage regulator (Saraswat Fig. 4, [0021]: 400) that are positioned in the interior (Saraswat Fig. 3, [0021]: 304) of the die (Saraswat Fig. 3, [0021]: 306), with the intent of using the voltage regulators in system architectures such as desktop or laptop computers, smartphones, or ATM machines (Saraswat Fig. 7, [0028]-[0029]) and for the further purpose of reducing the size and increasing the density of the integrated circuit package (Saraswat [0003]).
However, Huang in view of Saraswat does not explicitly teach the inductor coil is a transformer coil.
Fajardo, in the same field of invention, teaches a voltage regulator with an inductive component such as an inductor or a transformer ([0002]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Fajardo into the device of Huang in view of Saraswat to use transformers as an inductive coil in an integrated device at least comprising of a support structure, a semiconductor device at least partially in the support structure, a first inductor coil and a second inductor coil over the support structure, with either the first inductor coil or second inductor coil coupled to the semiconductor device. The ordinary artisan would have been motivated to modify Huang in view of Saraswat in the manner set forth above for at least the purpose of substituting equivalents known in the art for the same purpose of providing inductance to an electronic circuit (Fajardo [0002]) or, alternatively, for the purpose of simple substitution of inductor with a transformer to obtain a predictable result, which is to provide inductance to an electronic circuit (Fajardo [0002]). See MPEP § 2144.06 (II) and § 2143 (I) (B).
However, Huang in view of Saraswat and Fajardo does not teach: wherein the first via, second via, third via, and fourth via each extend between the first surface of the support structure and the second surface of the support structure.
Ashrafzadeh, in the same field of invention, teaches a device (300, see Fig. 3A) wherein the first via (331 is a via for inductor 370, see [0091] and [0107]), second via (332), third via (331; Huang in view of Saraswat, Fajardo and Ashrafzadeh teaches a third via for the second inductor of Huang), and fourth via (332; Huang in view of Saraswat, Fajardo and Ashrafzadeh teaches a fourth via for the second inductor of Huang) each extend between the first surface (bottom surface of 330) of the support structure and the second surface (top surface of 330) of the support structure (330 is a substrate; hence 330 is a support structure).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ashrafzadeh into the device of Huang in view of Saraswat and Fajardo to extend a first via, a second via, a third via, and a fourth via between a first surface of the support structure and a second surface of the support structure in an integrated circuit device at least comprising of the support structure having the first surface and an opposing second surface; a first transformer coil over the support structure; a second transformer coil over the support structure; the first via and the second via, with these vias connected to the first transformer coil; and the third via and the fourth via, with these vias connected to the second transformer coil. The ordinary artisan would have been motivated to modify Huang in view of Saraswat and Fajardo in the manner set forth above for at least the purpose of using the first, second, third, and fourth via to provide electrical connections to redistribution layers (352, see Ashrafzadeh Fig. 3A, [0090]) and at least one semiconductor die (342, 344; see Ashrafzadeh Fig. 3A and [0112]) under the support structure for the further purpose of better device integration density with reduced manufacturing costs of power management devices (Ashrafzadeh [0003], [0089]).
Regarding claim 6, the IC device according to claim 1, wherein the first transformer coil includes a portion (Saraswat Fig. 3, [0019]: top horizontal portion of 332; Fig. 3 shows the top horizontal portion of 332 is part of a layer that is comprised of the top horizontal portions of 332 and 334) of a first layer (Saraswat Fig. 3, [0018]: the layer that is comprised of the top horizontal portions of 332 and 334) comprising an electrically conductive material (Saraswat [0019] explains this is a part of continuous coil of vias and metal layers; metal is known in the art as conductive) and a portion (Saraswat Fig. 3, [0019] :338) of a second layer (Saraswat Fig. 3, [0018]: 310) comprising an electrically conductive material (Saraswat [0019] :338 is a metal layer), and the first layer is between the support structure and the second layer (Saraswat Fig. 3 shows the top horizontal portions of 332 and 334 is in between 316 and 310; 316 is an RDL connecting the inductor 331 to the rest of the die 404, see Fig. 4 and [0021]; 404 is analogous to Huang’s support structure; hence Huang in view of Saraswat teaches the first layer is between the support structure and the second layer).
Regarding claim 7, the IC device according to claim 1, wherein the portion of the first layer is coupled to the portion of the second layer by a via (Saraswat Fig. 3, [0018]: 322) that is closer to the second surface than the first surface (Huang in view of Saraswat teaches placing the upside-down structure of Saraswat Fig. 3 within element 136 in Huang Fig. 30B; hence Huang in view of Saraswat teaches via 322 closer to the second surface, which is the top surface of 115 in Huang Fig. 30B, than to the bottom surface of 115 in Huang Fig. 30B)).
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210335690 A1), Saraswat (US 20130335059 A1), Fajardo (US 20080075974 A1) and Ashrafzadeh (US 20140312458 A1), as applied to claim 1 above, and in further view of Xie (US 20230100113 A1) and Sisodia (US 20220223514 A1).
Regarding claim 2, Huang in view of Saraswat and Fajardo teaches the IC device according to claim 1, further comprising:
a power plane (Huang Fig. 30B, [0091]: a plurality of 148 supplies voltage connections) over the support structure (Huang Fig. 30B, [0091]: as shown in Fig. 30B, 148 is over 115);
a ground plane (Huang Figs. 30B, [0091]: a plurality of 148 supplies ground connections) over the support structure (Huang Figs. 30B, [0091]: as shown in the Figures, 148 is over 115);
a first power rail (Huang Figs. 30A, 30B, 30C, [0083]: 134; “power rail 134 comprises a metal layer”), the first power rail coupled to the power plane and to the semiconductor device (as shown in Figs. 30A-30C and [0084]-[0091], 134 is coupled to transistor to 148 to supply voltage ); and
However, Huang in view of Saraswat, Fajardo, and Ashrafzadeh does not teach the first power rail to be a buried power rail that is at least partially in the support structure.
Xie, in the same field of invention, teaches a semiconductor device (see abstract) wherein the first power rail is a buried power rail (Fig. 14, [0050]: 1402; 1402 is a backside power rail, hence analogous to Huang’s first power rail) that is at least partially in the support structure (Fig. 14, [0027]: 206 is a fin region with device stack 220 shown in Fig. 2, hence, 206&220 is analogous to Huang’s support structure; also see Figs. 2-8 and [0027]-[0042]; as shown in Fig.14, 1402 is at least partially in 206).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Xie into the device of Huang in view of Saraswat, Fajardo, and Ashrafzadeh to make the first power rail be a buried power rail that is partially in the support structure in an IC device at least comprising of a power plane over a support structure, a ground plane over a support structure, wherein the first buried power rail is coupled to the power plane and a semiconductor device. The ordinary artisan would have been motivated to modify Huang in view of Saraswat and Fajardo in the manner set forth above for at least the purpose of using the buried power rail as a solution to problems related to power distribution networks due to the requirements of scaling down the size and increasing the density of semiconductor devices (Xie [0002]).
However, Huang in view of Saraswat, Fajardo, Ashrafzadeh, and Xie does not teach
a second buried power rail at least partially in the support structure, the second buried power rail coupled to the ground plane and to the semiconductor device.
Sisodia, in the same field of invention, teaches a semiconductor device (Fig. 3, [0022]: 300) comprising of a second buried power rail (Figs. 2&3, [0023]: 314 is a frontside metal rail connected to transistors T1 & T6 of write word line WWL; [0021] teaches a front-side power delivery network; since 314 is coupled to T1/T6 extending from a top horizontal plane down to a device plane as shown in Fig. 3, then Sisodia teaches a buried power rail) at least partially in the support structure (as shown in Fig. 3, 314 is connected to device plane, which is the horizontal plane containing N-wells), the second buried power rail coupled to the ground plane (Figs. 2&3, [0020]: shows 314 coupled to GND of T3) and to the semiconductor device (¶ [0023]: 314 is connected to transistors T1 & T6).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sisodia into the device of Huang in view of Saraswat, Fajardo, Ashrafzadeh, and Xie to add a second buried power rail, with the second buried power rail at least partially in a support structure, and with the second power rail coupled to a ground plane and to a semiconductor device in an IC device at least comprising of the a power plane over the support structure, a ground plane over the support structure, a first buried power rail that is partially in the support structure in an IC device, the second power rail, and the semiconductor device that is at least partially in the support structure. The ordinary artisan would have been motivated to modify Huang in view of Saraswat, Fajardo, Ashrafzadeh, and Xie in the manner set forth above for at least the purpose of providing a power distribution network to an 8-transistor static random access memory (SRAM) bitcell that accommodates two wordlines in the same pitch without narrowing the device width and without increasing the wordline resistance and capacitance, which may degrade device performance (Sisodia [0002], [0009]).
Regarding claim 3, the IC device according to claim 2, wherein the first buried power rail or the second buried power rail has a longitudinal axis (Sisodia Fig. 3: horizontal axis) parallel to the first surface or the second surface (Sisodia Fig. 3 shows 314 extending horizontally and is parallel to the top surfaces of the device layers, i.e., those N-well regions below 314 ).
Regarding claim 4, the IC device according to claim 2, wherein the power plane or the ground plane is closer to the second surface than the first surface (Huang Fig. 30B shows 148 closer to the top surface of 115 than to the bottom surface of 115).
Claim(s) 15 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210335690 A1) and further in view of Fajardo (US 20080075974 A1), Liu (CN 107994007 A) and Ashrafzadeh (US 20140312458 A1).
Regarding claim 15, Huang teaches the integrated circuit (IC) structure (Figs. 30A-30C, [0002]-[0003]), comprising:
a support structure (Fig. 30B, [0067]: 115 is a device layer having transistors, analogous to Applicant’s definition in Specification ¶ 0044);
a first layer (¶ [0085]: 138 ) over the support structure (Fig 30B shows 138 over 115), the first layer comprising an electrically conductive material (¶ [0085]: right 140; 140 is a conductive via);
a first inductor (¶ [0086]: left 140; “the conductive features 140 comprise a metal-insulator-metal (MIM) inductor 140’ ”) in the first layer, the first inductor comprising a first portion (¶ [0086]: 140’ is a metal-insulator-metal inductor; hence it has a first portion made of metal) of the electrically conductive material (as explained in ¶ [0086], 140’ is composed of metal-insulator-metal);
a second inductor (Fig. 30B: right 140; [0086]: [0086]: “the conductive features 140 comprise a metal-insulator-metal (MIM) inductor 140’ ”) in the first layer (Fig. 30B shows right 140 is in layer 138), the second transformer coil comprising a second portion (¶ [0086]: 140’ is a metal-insulator-metal inductor; hence it has a first portion made of metal) of the electrically conductive material (as explained in ¶ [0086], 140’ is composed of metal-insulator-metal);
a second layer (Fig. 30B & 27, [0082]: 132) over the support structure, wherein the second layer is between the support structure and the first layer (Fig. 30B shows 132 in between 138 and 115 along the vertical axis);
a first elongated structure (Figs. 30A & 30B, [0083]: 134; 134 is elongated along the horizontal axis) in the second layer (Fig. 30A shows 134 inside 132), the first elongated structure comprising an electrically conductive material (¶ [0083]: 134 are conductive lines made of copper, aluminum, etc.) and coupled to the second inductor (Fig. 30B shows 134 connected to 140’ through 142, which is shown but not labelled);
a second elongated structure (Figs. 30A & 30B, [0083]: 134; 134 is elongated along the horizontal axis; Huang teaches a plurality of 134, as shown in Fig. 30A) in the second layer (Figs. 30A & 30B show 134 inside 132), the second elongated structure comprising an electrically conductive material (¶ [0083]: 134 are conductive lines made of copper, aluminum, etc.) and coupled to the second inductor (Fig. 30B shows a plurality of 134 and 140’, with 134 connected to 140’ through 142; 142 is shown but not labelled).
However, Huang does not teach the first and second inductors to be transformers.
Fajardo, in the same field of invention, teaches a voltage regulator with an inductive component such as an inductor or a transformer ([0002]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Fajardo into the device of Huang to substitute inductors with transformers in an integrated circuit structure at least comprising of a support structure; a first layer over the support structure, with the first layer comprising of an electrically conductive material; a first inductor in the first layer, with the first inductor comprising a portion of the electrically conductive material; a second inductor in the first layer, with the second inductor comprising a portion of the electrically conductive material; a first elongated structure in a second layer in between the support structure and the first layer, with the first elongated structure coupled to the first transformer; a second elongated structure in the second layer, with the second elongated structure coupled to the second transformer. The ordinary artisan would have been motivated to modify Huang in the manner set forth above for at least the purpose of substituting equivalents known in the art for the same purpose of providing inductance to an electronic circuit (Fajardo [0002]) or, alternatively, for the purpose of simple substitution of inductor with a transformer to obtain a predictable result, which is to provide inductance to an electronic circuit (Fajardo [0002]). See MPEP § 2144.06 (II) and § 2143 (I) (B).
However, Huang in view of Fajardo does not teach a transformer made of a first transformer coil and a second transformer coil, with second transformer coil to having a first end and a second end, and at least partially enclosed by the first transformer coil.
Liu, in the same field of invention, teaches a transformer (Fig. 2, [0018]; see English translation mailed together with previous office action on 04 June 2025) made of a first transformer coil (Fig. 2, [0025]: 14 is a half-turn spiral inductor; hence it is a coil) and a second transformer coil (Fig. 2, [0025]: 9 is a multi-turn spiral inductor; hence 9 is a coil), with second transformer coil to having a first end (Fig. 2: right end of 9) and a second end (Fig. 2: left end of 9), and at least partially enclosed by the first transformer coil (Fig. 2 shows 9 partially enclosed by 14 at the bottom side of the figure).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang in view of Fajardo into the device of Liu to provide a transformer made of a first transformer coil and a second transformer coil, with the second transformer coil having a first end and a second end and with the second transformer coil at least partially enclosed by the first transformer coil in an integrated circuit structure at least comprising of a support structure; a first layer over the support structure, with the first layer comprising of an electrically conductive material; the first transformer coil in the first layer, with the first transformer coil comprising a portion of the electrically conductive material; a second transformer coil in the first layer, with the second transformer coil comprising a portion of the electrically conductive material; a first elongated structure in a second layer in between the support structure and the first layer, with the elongated structure coupled to the first end of the first transformer; a second elongated structure in the second layer with the second elongated structure coupled to the second end of the second transformer. The ordinary artisan would have been motivated to modify Huang in view of Fajardo in the manner set forth above for at least the purpose of adding CMOS switches (Fig. 2, [0010], [0026]: 10, 11, 12, 13) at various positions of second transformer coil to make the inductance of the transformer coil be adjustable (Liu [0002]) and for the further purpose of having a stable, repeatable inductance value with higher quality factor, smaller chip area, and smaller insertion loss (Liu [0005]) and for using the CMOS switches as a method for reconfiguring the semiconductor devices after tape-out to optimize its circuit performance (Liu [0006]).
However, Huang in view of Fajardo and Liu does not teach: a through-silicon via couple to the first transformer coil or second transformer coil, the through-silicon via extending between a first surface of the support structure and a second surface of the support structure.
Ashrafzadeh, in the same field of invention, teaches a device (300, see Fig. 3A) comprising a through-silicon via (331 or 332) couple to the first transformer coil (370) or second transformer coil (Huang teaches a second transformer coil; in view of Ashrafzadeh, that coil is coupled to 332), the through-silicon via extending between a first surface (bottom surface of 330) of the support structure (330) and a second surface (top surface of 330) of the support structure.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ashrafzadeh into the device of Huang in view of Fajardo and Liu to couple a through-silicon via to a first transformer or a second transformer coil, with the through-silicon via extending between a first surface of the support structure and a second surface of the support structure in an integrated circuit structure at least comprising of the support structure; a first layer over the support structure; the first transformer coil in the first layer; and the second transformer coil in the first layer. The ordinary artisan would have been motivated to modify Huang in view of Fajardo, and Liu in the manner set forth above for at least the purpose of using the through-silicon via to provide electrical connections to redistribution layers (352, see Ashrafzadeh Fig. 3A, [0090]) and at least one semiconductor die (342, 344; see Ashrafzadeh Fig. 3A and [0112]) under the support structure for the further purpose of better device integration density with reduced manufacturing costs of power management devices (Ashrafzadeh [0003], [0089]).
Regarding claim 18, the IC device according to claim 15, further comprising a semiconductor device (Huang Fig. 30B, [0078]: 55&102 are gate structures) over or at least partially in the support structure (BRI: 55&102 are within 115, hence it is at least partially in 115), wherein the semiconductor device is closer to the first surface than the second surface (Fig. 30B shows 102 and/or bottom-most 55 closer to bottom of 115 than to the top of 115) and is coupled to the first transformer coil or the second transformer coil (Fig. 30B, [0046]-[0052], [0083]-[0086]: gate structures 55&102 are coupled with source/drains 92; 92 are then coupled to inductor 140 through 130&129 and 134/142; also Huang in view of Fajardo and Liu teaches the plurality of 140’ to be first or second transformer coils), and the second layer is closer to the second surface than the first surface (Huang Fig. 30B shows 132 is closer to the top of 115 than to the bottom of 115).
Regarding claim 19, the IC device according to claim 18, wherein the second transformer coil is coupled to the semiconductor device by the first elongated structure (Huang Fig. 30B shows 140 coupled to 134) and a structure (Huang Fig. 30B, [0089], [0093]: the 142 under rightmost 140), the structure is in the first layer (Huang Fig. 30B shows 142 within layer 138), the structure comprises an electrically conductive material (Huang [0089]).
Regarding claim 20, the IC device according to claim 19, wherein a portion (Liu Fig. 2: left portion of 14) of the first transformer coil is between the first end of the second transformer coil (Liu Figs. 1 & 2, [0023], [0025]: 14 is formed by top metal layer 6; 9 spans from the top metal layer 6 to the sub-top metal layers 5 through 1; Liu Fig. 3 shows the right end of 9 is in the lowest metal layer 1; hence left portion of 14 is on top of the right end of 9) and the structure (Liu’s structure is placed upside-down to substitute Huang’s inductor 140’ in Fig. 30B; hence, Huang’s structure 134 in Fig. 30B is on top of Liu’s 14; hence 14 is in between the first end of the first transformer coil and the structure).
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210335690 A1), Fajardo (US 20080075974 A1), Liu (CN 107994007 A), and Ashrafzadeh (US 20140312458 A1), as applied to claim 15 above, and further in view of Kim (US 20110084765 A1).
Regarding claim 16, Huang in view of Fajardo, Liu, and Ashrafzadeh teaches the IC device according to claim 15, wherein the first elongated structure is coupled to the first end by a via (Huang Fig. 30B, [0089], [0093]: 142; Fig. 30B shows 134 is coupled to 142). However, Huang in view of Fajardo and Liu does not teach the via across a portion of the first layer and a portion of the second layer.
Kim, in the same field of invention, teaches an inductor (Fig. 10, [0046]: 1000; Abstract and Fig. 11 and [0047]: teaches that this can be applied to inductors and transformers) connected to a via (Fig 10 and [0046] shows elongated structures 1010 and 1008 of inductor 1000 each connected to an unmarked via) across a portion (the portion of BEOL next to the via) of a first layer (Figs. 10 and 1, [0005]: BEOL) and a portion (the portion of the FEOL next to the via) of the second layer (Figs. 10 and 1, [0005]: FEOL; as shown in Fig. 10, each unmarked via goes from BOEL to FEOL in order for the inductor to be connected to circuit 1018 within FEOL;).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Huang in view of Fajardo, Liu, and Ashrafzadeh to provide a via across a portion of a first layer and a portion of the a second layer in an integrated structure at least comprising a support structure; the first layer over the support structure; a first transformer coil in the first layer; a second transformer coil in the first layer; the second layer over the support structure; a first elongated structure in the second layer, with the first elongated structure coupled to a first end of the second transformer coil and to the via. The ordinary artisan would have been motivated to modify Huang in view of Fajardo, Liu, and Ashrafzadeh in the manner set forth above for at least the purpose of creating the transformer coils in a BEOL layer below an FEOL support structure and using a via that spans between the BEOL layer and FEOL layer to connect the elongated structures of the transformer coils to a circuitry in the FEOL layer (Kim [0046]) and for the further purpose of improving the inductance values requiring less space and have less electromagnetic interference with other components in the integrated circuit (Kim [0013]) and with reduced manufacturing cost (Kim [0007], [0012]).
Regarding claim 17, the IC device according to claim 16, wherein the via has a longitudinal axis (Kim Fig. 10: vertical axis) perpendicular to the first layer or the second layer (Kim Fig. 10 shows via extends along the vertical axis, which is perpendicular to FEOL and BEOL, with the FEOL and BEOL extending along the horizontal axis).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899