DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 February 2026 has been entered.
Response to Arguments
Regarding the objection(s) to the drawings and the objection(s) to the specification in the Office Action filed on 15 July 2025, these objections have not yet been addressed by Applicant. As such, each of the above listed objections are maintained.
Regarding the non-statutory double patenting rejections in the Office Action filed on 15 July 2025, Applicants amendments to the claims in the reply filed 9 October 2025 have sufficiently addressed these rejections. As such, said rejections are hereby withdrawn.
The cancelation of Claim 2 & 3 in the response filed on 13 February 2026 is acknowledged.
Applicant’s request for the rejoinder of Claims 9 – 16 on Page 9 of the response filed on 13 January 2026 is acknowledged. However, Independent Claim 9, upon which Claims 10 – 16 depend, remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Regarding the rejections to the claims under 35 U.S.C. 103 in the Office Action filed 13 November 2025, Applicant’s amendments in the reply filed 13 January 2026 are acknowledged and have been fully considered but are not found persuasive.
On page 8 of the aforementioned reply, Applicant argues: Shih as disclosing the dummy chip retracted from an outer sidewall of the layer 310. As such, Applicant does not understand Shih as disclosing the dummy chip in vertical alignment with the outer sidewall of the layer 310.
Admittedly, SHI shows the dummy chip (SHI Annotated Fig. 13: leftmost 420b) retracted from an outer sidewall of the layer (SHI Annotated Fig. 13: 310). However, as presently written, the language of independent Claims 1 & 17 does not preclude the outer sidewall of the dummy chip as being defined as: the leftmost portion of 500 attached to the leftmost 420b in the rightmost 10a, as seen in SHI Annotated Fig. 13, which satisfies SHI as disclosing the dummy chip 420b as having an outer sidewall in vertical alignment with the outer sidewall of the layer 310. Moreover, this interpretation is consonant with the elected species as presented in Fig. 2, 200b of the instant application where the outer sidewall of the dummy chip (Fig. 2, 200b: leftmost 212 on 224) may be interpreted as the leftmost portion of 216 attached to the leftmost 212 in 224, as seen in Fig. 2, 200b of the instant application, which satisfies associated claim limitation “the dummy die has an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion” of independent claim 1, and the associated claim limitation “the second die having an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion” of independent claim 17. As such, amending independent claim 1 to require “the dummy die has an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion” and/or amending independent claim 17 to require “the second die having an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion” is not deemed to patentably distinguish Applicant’s claimed device from the known device of SHI in view of CHE.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Re: Claim 20 (Original), the drawings pertaining to the elected species must show “the first die includes transistors”. However, the drawings pertaining to the elected species show no such transistors included in the first die (Fig. 2: 206).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Re: Claim 20 (Original), the sections of the specification ([0028] - [0031]) providing the detailed description of Fig. 2 (which contains the presentation of the elected species) must describe the first die (206) to include transistors and the second die (210) to not include transistors.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1,
Lin. 7 recites the limitation “the dummy” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “the dummy die”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 17 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over SHI (US 20210175188 A1) in view of CHE (US 20210391322 A1).
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Re: Independent Claim 1 (Currently Amended), SHI discloses:
A package (SHI Annotated Fig. 13: rightmost 10a) comprising
a substrate (SHI Annotated Fig. 13: S1),
the substrate comprising a redistribution layer… (SHI Annotated Fig. 13: 410);
an active die (SHI Annotated Fig. 13: leftmost 420a) on the substrate;
a dummy die (SHI Annotated Fig. 13: leftmost 420b) on the substrate proximate to an edge (SHI Annotated Fig. 13: leftmost vertical edge of leftmost 420a) of the active die,
the dummy die physically coupled with the substrate with [an adhesive]; and
(SHI Annotated Fig. 13 shows 420b physically coupled with S1 with “adhesive” 430; SHI ¶ [0041])
wherein the dummy die has an outer sidewall (SHI Annotated Fig. 13: leftmost portion of 500 attached to leftmost 420b, where this interpretation is consonant with the elected species as presented in Fig. 2: 200b of the instant application. See Response to Arguments section for more details.) in vertical alignment with an outer sidewall (SHI Annotated Fig. 13: leftmost sidewall of S1) of the [substrate].
SHI does not disclose:
the substrate comprising a redistribution layer on a silicon wafer portion
And SHI does not disclose:
wherein the dummy die has an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion
However, CHE discloses:
the substrate (CHE Fig. 1E: 138/137/131/105/119 where 131 comprises 135 and 133.) comprising a redistribution layer (CHE Fig. 1E: 131) on a silicon wafer portion (CHE Fig. 1E: 105 where CHE [0015] teaches “the wafer 100 includes a substrate 105…[which] may be formed of silicon”.);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHE with those of SHI to enable the substrate to comprise a redistribution layer on a silicon wafer portion in SHI according to the teachings of CHE, as the interposer design of CHE provides a means to improve the density of integrated circuits in device packaging (CHE ¶ [0001] – [0002]), wherein a chief component of said interposer design is the choice in device scaffold material, i.e. silicon wafer.
Further, this combination also satisfies the claim limitation “wherein the dummy die has an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion”, as combining the teachings of CHE with those of SHI to enable the substrate to comprise a redistribution layer on a silicon wafer portion in SHI according to the teachings of CHE would yield a substrate with the same general shape and alignment with respect to the dummy die as presented in SHI.
SHI also does not disclose:
the dummy die physically coupled with the substrate with a die attach film (DAF)
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to specifically use DAF to physically couple the dummy die with the substrate, as claimed, as SHI discloses the dummy die is physically coupled with the substrate with an adhesive, but SHI does not specify a particular type of adhesive (SHI ¶ [0041]). Therefore, a person having ordinary skill in the art would look to the prior art for a type of adhesive recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the type of adhesive—specifically DAF, CHE ¶ [0094]—disclosed in CHE meets these criteria, as both SHI and CHI disclose similar devices and use said adhesive for similar purposes, namely physically coupling a substrate to a die (CHE Fig. 7C: 128; ¶ [0094]).
Re: Independent Claim 17 (Currently Amended), SHI discloses:
A package (SHI Annotated Fig. 13: rightmost 10a) comprising:
a substrate (SHI Annotated Fig. 13: S1),
the substrate comprising a redistribution layer… (SHI Annotated Fig. 13: 410);
a first die (SHI Annotated Fig. 13: leftmost 420a) on the substrate,
the first die electrically coupled to the substrate by metal interconnects;
(SHI Annotated Fig. 13 shows 420a electrically coupled to S1 via 416)
a second die (SHI Annotated Fig. 13: leftmost 420b) on the substrate,
the second die not electrically coupled to the substrate by metal interconnects; and (SHI Annotated Fig. 13 shows 420b not electrically coupled to S1 via metal interconnects.)
wherein the second die is physically coupled with the substrate by an adhesive material (SHI Annotated Fig. 13 shows 420b physically coupled with S1 by an adhesive material 430.),
the second die having an outer sidewall (SHI Annotated Fig. 13: leftmost portion of 500 attached to leftmost 420b, where this interpretation is consonant with the elected species as presented in Fig. 2: 200b of the instant application. See Response to Arguments section for more details.) in vertical alignment with an outer sidewall (SHI Annotated Fig. 13: leftmost sidewall of S1) of the [substrate].
SHI does not disclose:
the substrate comprising a redistribution layer on a silicon wafer portion
And SHI does not disclose:
the second die having an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion.
However, CHE discloses:
the substrate (CHE Fig. 1E: 138/137/131/105/119 where 131 comprises 135 and 133.) comprising a redistribution layer (CHE Fig. 1E: 131) on a silicon wafer portion (CHE Fig. 1E: 105 where CHE [0015] teaches “the wafer 100 includes a substrate 105…[which] may be formed of silicon”.);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHE with those of SHI to enable the substrate to comprise a redistribution layer on a silicon wafer portion in SHI according to the teachings of CHE, as the interposer design of CHE provides a means to improve the density of integrated circuits in device packaging (CHE ¶ [0001] – [0002]), wherein a chief component of said interposer design is the choice in device scaffold material, i.e. silicon wafer.
Further, this combination also satisfies the claim limitation “the second die having an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion”, as combining the teachings of CHE with those of SHI to enable the substrate to comprise a redistribution layer on a silicon wafer portion in SHI according to the teachings of CHE would yield a substrate with the same general shape and alignment with respect to the second die as presented in SHI.
Re: Claim 18 (Original), SHI & CHE disclose all of the limitations of Claim 17, upon which this claim depends. SHI further discloses:
wherein the first die includes one or more metal pads at a bottom of the first die (SHI Annotated Fig. 13 shows the bottom of 420a bonded with “micro-bumps” 416 for the purpose of forming an electrical connection, as taught by SHI [0040], which is known in the art to be achieved via metal pads at the bottom of 420a.) that are bonded, respectively, with one or more metal pads in the substrate (SHI Annotated Fig. 13 shows 416 bonded with one or more metal pads 415 in S1.)
Re: Claim 19 (Previously Presented), SHI & CHE disclose all of the limitations of Claim 18, upon which this claim depends.
SHI further discloses:
wherein the one or more metal pads in the substrate comprise copper. (SHI [0039] teaches “the metal layer 414 may comprise a plurality of [metal] pads 415”, and SHI [0038] teaches 414 may comprise copper. Further, SHI Annotated Fig. 13 shows 414 and 415 are of the same composition.).
SHI does not disclose:
wherein the one or more metal pads at the bottom of the first die and the one or more metal pads in the substrate comprise copper.
However, CHE discloses:
wherein the one or more metal pads (CHE Fig. 1E: 223) at the bottom of the first die (CHE Fig. 1E: 204) and the one or more metal pads (CHE Fig. 1E: 123) in the substrate (CHE Fig. 1E: 138/137/131/105/119) comprise copper (CHE [0027] teaches 223 and 123 may both comprise copper, as they may be bonded to each other in a direct copper-to-copper bond.).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the material of said metal pads of SHI with that of CHE, as these inventions are from the same field of endeavor, and the interposer design of CHE provides a means to improve the density of integrated circuits in device packaging, CHE [0001] – [0002], a chief component of said interposer design being the choice in bonding method, i.e. direct copper-to-copper bonding.
Re: Claim 20 (Original), SHI & CHE disclose all of the limitations of Claim 17, upon which this claim depends. SHI further discloses:
wherein the first die includes transistors (SHI [0028] teaches the “420a are active integrated circuit [die] with certain functions, for example, GPU (graphics processing unit), CPU (central processing unit), memory chips, etc.”, which are known in the art to include transistors.) and wherein the second die does not include transistors (SHI [0029] teaches “the dummy [die] 420b may be dummy silicon chips, dies or pieces”, which are known in the art to not include transistors.).
Re: Claim 21 (Original), SHI & CHE disclose all of the limitations of Claim 17, upon which this claim depends. SHI further discloses:
wherein the first die is an active die (SHI [0042] teaches the 420a are active die.), and wherein the second die is a dummy die (SHI [0041] teaches the 420b are dummy die.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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