DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding the objection(s) to the drawings and the objection(s) to the specification in the Office Action filed on 15 July 2025, these objections have not yet been addressed by Applicant. As such, each of the above listed objections is maintained.
Applicant’s request for the rejoinder of Claims 9 – 16 and 22 – 25 on Page 9 of the response filed on 2 July 2026 is acknowledged. However, Independent Claims 9 & 22, from which Claims 10 – 16 & 23 – 25 respectively depend, remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Applicant’s amendment to Claim 1 addressing the rejection under 35 U.S.C. 112(b) in the reply filed 2 July 2026 is acknowledged. This rejection has been overcome by the amendment of said claim, and the associated rejection is therefore withdrawn.
Regarding the rejections to the claims under 35 U.S.C. 103 in the Office Action filed 6 April 2026, Applicant’s amendments in the reply filed 2 July 2026 are acknowledged and have been fully considered but are not found persuasive.
Applicant argues that SHI does not disclose “a redistribution layer on a silicon wafer portion…having through silicon vias (TSVs) therein.” Admittedly, SHI does not disclose this limitation; however, CHE teaches this and other limitations not disclosed by SHI. Further, SHI identifies redistribution layers on TSV interposers as conventional, and CHE demonstrates the predictable implementation thereof. Therefore, it would have been obvious to substitute the substrate of CHE for that of SHI. Accordingly, Applicant’s argument does not overcome the rejection in which SHI is modified in view of CHE.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Regarding Claim 20, the drawings pertaining to the elected species must show “the first die includes transistors”. However, the drawings pertaining to the elected species show no such transistors included in the first die (Fig. 2: 206).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding Claim 20, the sections of the specification ([0028] - [0031]) providing the detailed description of Fig. 2 (which contains the presentation of the elected species) must describe the first die (206) to include transistors and the second die (210) to not include transistors.
Examiner’s Note
For the prior art rejections to follow, consider both the original figures and the annotated figure provided below.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 & 17 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over SHI (US 20210175188 A1) in view of CHE (US 20210391322 A1).
Regarding Claim 1,
SHI discloses:
A package (SHI Annotated Fig. 13: rightmost 10a) comprising
a substrate (SHI Annotated Fig. 13: S1), the substrate comprising
a redistribution layer… (SHI Annotated Fig. 13: 410);
an active die (SHI Annotated Fig. 13: leftmost 420a)
on the substrate;
a dummy die (SHI Annotated Fig. 13: leftmost 420b)
on the substrate
proximate to an edge (SHI Annotated Fig. 13: leftmost vertical edge of leftmost 420a) of the active die,
the dummy die physically coupled with the substrate with a die attach film (DAF); and
(SHI Annotated Fig. 13 shows 420b physically coupled with S1 with “adhesive” 430; SHI ¶ [0041]. As a “film” may be interpreted as a “layer” and 430 clearly constitutes a layer which is used to attach dummy die 420b to substrate S1, under a broadest reasonable interpretation 430 may be construed as a “die attach film”.)
wherein the dummy die has an outer sidewall (SHI Annotated Fig. 13: leftmost portion of 500 attached to leftmost 420b, where this interpretation is consonant with the elected species as presented in Fig. 2: 200b of the instant application.) in vertical alignment with an outer sidewall (SHI Annotated Fig. 13: leftmost sidewall of S1) of the [substrate].
SHI does not disclose:
the substrate comprising a redistribution layer on a silicon wafer portion,
the silicon wafer portion having through silicon vias (TSVs) therein:
CHE discloses:
the substrate (CHE Fig. 1E: 138/137/131/105/119 where 131 comprises 135 and 133.) comprising a redistribution layer (CHE Fig. 1E: 131) on a silicon wafer portion (CHE Fig. 1E: 105 where CHE [0015] teaches “the wafer 100 includes a substrate 105…[which] may be formed of silicon”.), the silicon wafer portion having through silicon vias (TSVs) therein (Fig. 1E: 109);
Based on the foregoing factual findings, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of SHI with those of CHE such that the substrate of SHI is replaced with the substrate of CHE, thereby satisfying the claimed limitations “the substrate comprising a redistribution layer on a silicon wafer portion, the silicon wafer portion having through silicon vias (TSVs) therein”, as SHI identifies that such packages are conventionally formed with the redistribution layers on TSV interposers (SHI Par. 3), and CHE teaches the conventionally formed package, thereby demonstrating its predictable implementation. Therefore, said person of ordinary skill would have found it obvious to substitute the known substrate of CHE for that of SHI. Admittedly, SHI teaches advantages of employing such packages with no TSV interposer for the sake of cost and complexity (SHI Par. 5). However, the sacrifice of this advantage would not have rendered the aforementioned substitution nonobvious, as SHI recognizes the substrate design of CHE to be conventional though potentially undesirable in certain applications (SHI Par. 5). See also MPEP § 2143.01(V). Further, said person having ordinary skill would have had a reasonable expectation of success in this endeavor, as they would have known how to execute such a modification and the results thereof would have been reasonably predictable. Accordingly, upon considering and weighing all foregoing evidence, the claimed invention is not found to be patentably distinct from that of SHI in view of CHE, consistent with KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). See also MPEP § 2143(I)(B).
SHI does not disclose:
wherein the dummy die has an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion.
However, the aforementioned modification in view of CHE also satisfies the claim limitation “wherein the dummy die has an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion”, as this modification would yield a substrate with the same general shape and alignment with respect to the dummy die as presented in SHI.
Regarding Claim 17,
SHI discloses:
A package (SHI Annotated Fig. 13: rightmost 10a) comprising:
a substrate (SHI Annotated Fig. 13: S1), the substrate comprising
a redistribution layer… (SHI Annotated Fig. 13: 410);
a first die (SHI Annotated Fig. 13: leftmost 420a)
on the substrate,
the first die electrically coupled to the substrate by metal interconnects;
(SHI Annotated Fig. 13 shows 420a electrically coupled to S1 via 416)
a second die (SHI Annotated Fig. 13: leftmost 420b)
on the substrate,
the second die not electrically coupled to the substrate by metal interconnects; and (SHI Annotated Fig. 13 shows 420b not electrically coupled to S1 via metal interconnects.)
wherein the second die is physically coupled with the substrate by an adhesive material (SHI Annotated Fig. 13 shows 420b physically coupled with S1 by an adhesive material 430.),
the second die having an outer sidewall (SHI Annotated Fig. 13: leftmost portion of 500 attached to leftmost 420b, where this interpretation is consonant with the elected species as presented in Fig. 2: 200b of the instant application.) in vertical alignment with an outer sidewall (SHI Annotated Fig. 13: leftmost sidewall of S1) of the [substrate].
SHI does not disclose:
the substrate comprising a redistribution layer on a silicon wafer portion,
the silicon wafer portion having through silicon vias (TSVs) therein;
CHE discloses:
the substrate (CHE Fig. 1E: 138/137/131/105/119 where 131 comprises 135 and 133.) comprising a redistribution layer (CHE Fig. 1E: 131) on a silicon wafer portion (CHE Fig. 1E: 105 where CHE [0015] teaches “the wafer 100 includes a substrate 105…[which] may be formed of silicon”.) the silicon wafer portion having through silicon vias (TSVs) therein (Fig. 1E: 109);
Based on the foregoing factual findings, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of SHI with those of CHE such that the substrate of SHI is replaced with the substrate of CHE, thereby satisfying the claimed limitations “the substrate comprising a redistribution layer on a silicon wafer portion, the silicon wafer portion having through silicon vias (TSVs) therein”, as SHI identifies that such packages are conventionally formed with the redistribution layers on TSV interposers (SHI Par. 3), and CHE teaches the conventionally formed package, thereby demonstrating its predictable implementation. Therefore, said person of ordinary skill would have found it obvious to substitute the known substrate of CHE for that of SHI. Admittedly, SHI teaches advantages of employing such packages with no TSV interposer for the sake of cost and complexity (SHI Par. 5). However, the sacrifice of this advantage would not have rendered the aforementioned substitution nonobvious, as SHI recognizes the substrate design of CHE to be conventional though potentially undesirable in certain applications (SHI Par. 5). See also MPEP § 2143.01(V). Further, said person having ordinary skill would have had a reasonable expectation of success in this endeavor, as they would have known how to execute such a modification and the results thereof would have been reasonably predictable. Accordingly, upon considering and weighing all foregoing evidence, the claimed invention is not found to be patentably distinct from that of SHI in view of CHE, consistent with KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). See also MPEP § 2143(I)(B).
SHI does not disclose:
the second die having an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion.
However, the aforementioned modification in view of CHE also satisfies the claim limitation “the second die having an outer sidewall in vertical alignment with an outer sidewall of the silicon wafer portion”, as this modification would yield a substrate with the same general shape and alignment with respect to the second die as presented in SHI.
Regarding Claim 18,
SHI does not disclose:
The package of claim17,
wherein the first die includes one or more metal pads at a bottom of the first die that are bonded, respectively, with one or more metal pads in the substrate.
CHE discloses:
wherein the first die (Fig. 1E: 205) includes one or more metal pads (Fig. 1E: 223) at a bottom of the first die that are bonded (Par. 27), respectively, with one or more metal pads (Fig. 1E: 123) in the substrate (Fig. 1E: 119 of 138/137/131/105/119).
Having substituted the substrate of CHE for that of SHI—as set forth with respect to Claim 17—said person having ordinary skill would have predictably employed CHE’s corresponding means of mounting/connecting the first die to the substrate, thereby satisfying the limitations of this claim.
Regarding Claim 19,
SHI does not disclose:
The package of claim 18,
wherein the one or more metal pads at the bottom of the first die and the one or more metal pads in the substrate comprise copper.
CHE discloses:
wherein the one or more metal pads (223) at the bottom of the first die (205) and the one or more metal pads (123) in the substrate (119 of 138/137/131/105/119) comprise copper (Par. 27).
Regarding Claim 20,
SHI discloses:
The package of claim 17,
wherein the first die includes transistors (SHI [0028] teaches the “420a are active integrated circuit [die] with certain functions, for example, GPU (graphics processing unit), CPU (central processing unit), memory chips, etc.”, which are known in the art to include transistors.) and wherein the second die does not include transistors (SHI [0029] teaches “the dummy [die] 420b may be dummy silicon chips, dies or pieces”, which are known in the art to not include transistors.).
Regarding Claim 21,
SHI discloses:
The package of claim 17,
wherein the first die is an active die (SHI [0042] teaches the 420a are active die.), and wherein the second die is a dummy die (SHI [0041] teaches the 420b are dummy die.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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