DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 20 February 2026 has been entered.
Response to Arguments
The objection(s) to the drawings and objection(s) to the specification in the Office Action filed on 17 October 2025 have not been addressed by Applicant. As such, each of the above listed objections are maintained.
Applicant’s request for the rejoinder of Claims 14 – 25 on Page 9 of the response filed on 10 February 2026 is acknowledged. However, Independent Claims 14 and 24, upon which Claims 15 – 23 and 25 respectively depend, remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Regarding the rejections to the claims under 35 U.S.C. 103 in the Office Action filed 12 December 2025, Applicant’s amendments in the reply filed 10 February 2026 are acknowledged and have been fully considered but are not found persuasive.
On page 9 of the aforementioned reply, Applicant argues:
Liou does not disclose a semiconductor device including a fin with a first end and a second end, a first gate structure over the first end of the fin, where the first gate structure does not extend down the first end of the fin, and a second gate structure over the fin and between the first end and the second end of the fin, the second gate structure having a bottommost surface at a same level as a bottommost surface of the first gate structure in a cross-sectional view through the fin from the first end of the fin to the second end of the fin, as is required by Applicant's claims.
To support this argument, Applicant provides a non-limiting example of an interpretation of the above claim language, for which Applicant asserts “Liou fails to disclose each and every feature of Applicant’s claims. Without admitting to the propriety of said non-limiting example, the Examiner asserts, as presently written, the language of Claim 1 does not preclude other interpretations, including but not limited to:
LIO discloses:
A semiconductor device (LIO Annotated Fig. 13), comprising:
a fin (LIO Annotated Fig. 13: 101 on the left side of the figure) with a first end (LIO Annotated Fig. 13: E1) and a second end (LIO Annotated Fig. 13: E2);
a first gate structure (LIO Annotated Fig. 13: 350, as LIO ¶ [0025] teaches 352 is a “gate electrode”.) over the first end of the fin (As seen in LIO Annotated Fig. 13),
a second gate structure (LIO Annotated Fig. 13: 370) over the fin and between the first end and the second end of the fin (As seen in LIO Annotated Fig. 13),
the second gate structure having a bottommost surface (LIO Annotated Fig. 13: the surface of 373—of which 370 is comprised—in direct contact with the fin 101. Note, 370 may be considered under a broad but reasonable interpretation to have a plurality of bottommost surfaces, i.e. at least one bottommost surface from each component of 370.) at a same level as a bottommost surface (LIO Annotated Fig. 13: the surface of 353—of which 350 is comprised—on the right side of 350 in direct contact with the fin 101. Note, 350 may be considered under a broad but reasonable interpretation to have a plurality of bottommost surfaces, i.e. at least one bottommost surface from each component of 350.) of the first gate structure in a cross-sectional view (LIO Annotated Fig. 13) through the fin from the first end of the fin to the second end of the fin (As seen in LIO Annotated Fig. 13).
However, LIO does not disclose:
and wherein the first gate structure does not extend down the first end of the fin.
Regardless, for a similar device, CHI discloses:
and wherein the first gate structure does not extend down the first end of the fin (CHI Annotated Figs. 4A & 6A show the first gate structure G does not extend down the first end E1 of the fin 504c, as the first dielectric 604t covers all of E1.).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first dielectric of LIO with that of CHI, as these inventions are from the same field of endeavor, and doing so provides a number of benefits in device fabrication and performance, as per CHI ¶ [0036].
As this interpretation satisfies the above cited limitations of this claim, amending Claim 1 to require “a second gate structure over the fin and between the first end and the second end of the fin, the second gate structure having a bottommost surface at a same level as a bottommost surface of the first gate structure in a cross-sectional view through the fin from the first end of the fin to the second end of the fin” is not deemed to patentably distinguish Applicant’s claimed device from the known device of LIO in view of CHI.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Re: Claim10, the first gate structure being a metal gate structure.
The above listed feature must be shown or the feature canceled from the claim. No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the following, as described in the specification:
Re: ¶ [0044], the “replacement metal gate process”.
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
The drawings are objected to because:
Re: Fig. 3E, a portion (331) of the dielectric layer (330) between the topmost edge of the semiconductor device (300) and the end of the first fin (310A) closest to this topmost edge is not shown. This is inconsistent with the previous step in fabrication, shown in Fig. 3D. There is a similar issue with the unlabeled fin symmetric to 310A in these figures.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: FINFET SELF-ALIGNED END-SURFACE PASSIVATION TECHNIQUE.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1 & 3 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over LIO (US 20170025540 A1) in view of CHI (US 20190067120 A1).
Re: Independent claim 1,
LIO discloses:
A semiconductor device (LIO Annotated Fig. 13), comprising:
a fin (LIO Annotated Fig. 13: 101 on the left side of the figure) with a first end (LIO Annotated Fig. 13: E1) and a second end (LIO Annotated Fig. 13: E2);
a first dielectric (LIO Annotated Fig. 13: 170 to the left of the fin where 170 may be silicon oxide, LIO ¶ [0023].) that covers the first end of the fin (LIO Annotated Fig. 13 shows 170 to the left of the fin covering E1.);
a second dielectric (LIO Annotated Fig. 13: 150 where 150 may be silicon oxide, LIO ¶ [0023].) that covers the second end of the fin (LIO Annotated Fig. 13 shows 150 covering E2);
a first gate structure (LIO Annotated Fig. 13: 350, as LIO ¶ [0025] teaches 352 is a “gate electrode”.) over the first end of the fin, wherein the first gate structure is on a top surface of the fin and a top surface of the first dielectric (LIO Annotated Fig. 13 shows 350 over E1 wherein 350 is on a top surface the fin and a top surface of 170 to the left of the fin.),
a second gate structure (LIO Annotated Fig. 13: 370) over the fin and between the first end and the second end of the fin (As seen in LIO Annotated Fig. 13),
the second gate structure having a bottommost surface (LIO Annotated Fig. 13: the surface of 373 of 370 in direct contact with the fin 101) at a same level as a bottommost surface (LIO Annotated Fig. 13: the surface of 353 on the right side of 350 in direct contact with the fin 101) of the first gate structure in a cross-sectional view (LIO Annotated Fig. 13) through the fin from the first end of the fin to the second end of the fin (As seen in LIO Annotated Fig. 13).
However, LIO does not disclose:
and wherein the first gate structure does not extend down the first end of the fin.
Regardless, for a similar device, CHI discloses:
and wherein the first gate structure does not extend down the first end of the fin (CHI Annotated Figs. 4A & 6A show the first gate structure G does not extend down the first end E1 of the fin 504c, as the first dielectric 604t covers all of E1.).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first dielectric of LIO with that of CHI, as these inventions are from the same field of endeavor, and doing so provides a number of benefits in device fabrication and performance, as per CHI ¶ [0036].
Re: Claim 3, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO is silent to:
wherein the top surface of the fin is substantially coplanar with the top surface of the first dielectric.
However, CHI discloses:
wherein the top surface of the fin (CHI Annotated Fig. 4A: 504c) is substantially coplanar with the top surface of the first dielectric (CHI Annotated Fig. 4A: 604t. Further, CHI ¶ [0062] teaches “604t…[is] such that [its] top surface [is] substantially coplanar with…504c”.).
Re: Claim 4, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO further discloses:
a second fin (LIO Annotated Fig. 13: 101 on the right side of the figure) with a third end (LIO Annotated Fig. 13: E3) and a fourth end (LIO Annotated Fig. 13: E4), wherein the third end of the second fin faces the second end of the fin (LIO Annotated Fig. 13 shows E3 facing E2), and wherein the second dielectric covers the third end of the second fin (LIO Annotated Fig. 13 shows 150 covering E3.).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the second dielectric of LIO with a dielectric similar to that of the first dielectric of CHI, which would cover all of E3 and E2 of LIO and, therefore, also satisfy the limitations of this claim. Performing such a substitution would be obvious, as these inventions are from the same field of endeavor, and doing so provides a number of benefits in device fabrication and performance, CHI ¶ [0036].
Re: Claim 5, LIO in view of CHI discloses all of the limitations of claim 4, upon which this claim depends.
LIO further discloses:
a third gate structure (LIO Annotated Fig. 13: 330, as LIO ¶ [0025] teaches 332 is a “gate electrode”.) over the second fin, wherein the third gate structure is on the second fin and the second dielectric (LIO Annotated Fig. 13 shows 330 over 101 on the right side of the figure, wherein the 330 is on 101 on the right side of the figure and 150.).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the second dielectric of LIO with a dielectric similar to that of the first dielectric of CHI, which the third gate structure of LIO would be on and, therefore, also satisfy the limitations of this claim. Performing such a substitution would be obvious, as these inventions are from the same field of endeavor, and doing so provides a number of benefits in device fabrication and performance, CHI ¶ [0036].
Re: Claim 6, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO further discloses:
wherein the first dielectric and the second dielectric are connected by a third dielectric (LIO Fig. 7: 170 along the length of the fin.) that is provided along a length of the fin (LIO Fig. 7 shows and LIO ¶ [0024] teaches the top portion of 101 protrudes from 170, which provides 170 along a length of 101 and connects 170 to the left of the fin to 150. Furthermore, LIO Fig. 7 is a fabrication step used in the forming of LIO Annotated Fig. 13, as per LIO ¶ [0033].).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the second dielectric of LIO with a dielectric similar to that of the first dielectric of CHI as well as to substitute the third dielectric of LIO with the third dielectric of CHI (CHI Annotated Fig. 4A: 604a), which would connect the first and second dielectrics and be provided along a length of the fin, therefore, also satisfy the limitations of this claim. Performing such substitutions would be obvious, as these inventions are from the same field of endeavor, and doing so provides a number of benefits in device fabrication and performance, CHI ¶ [0036].
Re: Claim 7, LIO in view of CHI discloses all of the limitations of claim 6, upon which this claim depends.
LIO is silent to:
wherein the third dielectric is spaced away from an edge of the fin that connects the first end of the fin to the second end of the fin.
However, CHI discloses:
wherein the third dielectric (CHI Annotated Fig. 4A: 604a) is spaced away from an edge of the fin (CHI Annotated Fig. 4A: 504c) that connects the first end (CHI Annotated Fig. 4A: E1) of the fin to the second end (CHI Annotated Fig. 4A: E2) of the fin (CHI Annotated Fig. 4A shows 604a spaced away from an edge of 504c that connects E1 to E2.).
Re: Claim 8, LIO in view CHI discloses all of the limitations of claim 7, upon which this claim depends.
LIO is silent to:
wherein the first gate structure is between the fin and the third dielectric.
However, CHI discloses:
wherein the first gate structure (CHI Annotated Fig. 6A: G) is between the fin and the third dielectric (CHI Fig. 6B is a cross-section through a “mid-fin” gate structure, G’ of CHI Annotated Fig. 6A, showing “metal gate electrode” 1108 between 504c and 604a. A parallel cross-section through G is similar.).
Re: Claim 9, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO further discloses:
wherein the first dielectric has a planar surface that contacts the first end of the fin (LIO ¶ [0021] teaches E1 is formed via an appropriate etching procedure, thereby resulting in a planar surface. Further, LIO Annotated Fig. 13 shows 170 to the left of the fin to be conformal with E1 and contacting E1 via 107.).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first dielectric of LIO with that of CHI, which would have a planar surface that contacts the first end of the fin and, therefore, also satisfy the limitations of this claim. Performing such a substitution would be obvious, as these inventions are from the same field of endeavor, and doing so provides a number of benefits in device fabrication and performance, CHI ¶ [0036].
Re: Claim 10, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO further discloses:
wherein the first gate structure is a metal gate structure (As per LIO ¶ [0028], 350 may become a metal structure via a “replacement metal gate process”.).
Re: Claim 11, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO further discloses:
wherein a face of the first gate structure is offset from the first end of the fin (LIO Annotated Fig. 13 shows a face of 350 offset from E1.).
Re: Claim 12, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO further discloses:
wherein the first gate structure wraps around sidewalls of the fin and the top surface of the fin (LIO Fig. 8 shows a plan view of 350 on 101, wrapping around the sidewalls of 101 and the top surface of 101. Furthermore, this step applies to the forming of LIO Annotated Fig. 13, as per LIO ¶ [0033], which supports this limitation, showing 350 on the top surface of 101.).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the first dielectric of LIO with that of CHI as well as to substitute the third dielectric of LIO with the third dielectric of CHI (CHI Annotated Fig. 4A: 604a), which would also provide the first gate structure wrapped around sidewalls of the fin and the top surface of the fin (CHI Annotated Figs. 4A & 6A also show first gate structure G wrapped around sidewalls of 504c and the top surface of 504c.), thus also satisfying the limitations of this claim. Performing such substitutions would be obvious, as these inventions are from the same field of endeavor, and doing so provides a number of benefits in device fabrication and performance, CHI ¶ [0036].
Re: Claim 13, LIO in view of CHI discloses all of the limitations of claim 12, upon which this claim depends.
LIO is silent to:
wherein the first gate structure forms a U-shape around the fin.
However, CHI discloses:
wherein the first gate structure forms a U-shape around the fin (CHI Fig. 6B is a cross-section through the “mid-fin” gate structure, G’ of CHI Annotated Fig. 6A, showing “metal gate electrode” 1108 forming a U-shape around 504c. A parallel cross-section through G is similar.).
Further, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute the geometry and placement of the first gate structure of LIO with that of CHI, as such geometry and placement of the first gate structure is dependent upon the first, second, and third dielectrics of CHI, these inventions are from the same field of endeavor, and performing such substitutions provide a number of benefits in device fabrication and performance, as per CHI ¶ [0036].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over LIO in view of CHI and in further view of CHA (US 20200058763 A1).
Re: Claim 2, LIO in view of CHI discloses all of the limitations of claim 1, upon which this claim depends.
LIO and CHI both are silent to:
wherein the fin comprises: a plurality of semiconductor channels in a vertical stack.
However, for a similar device, CHA discloses:
wherein the fin (CHA Fig. 3A: 40) comprises: a plurality of semiconductor channels (CHA Fig. 3A: 20 & 21) in a vertical stack (CHA Fig. 3A shows alternating layers of 20 & 21 in a vertical stack.).
Further, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute the fin structures of LIO in view of CHI with those of CHA, as these inventions are from the same field of endeavor, and the fin structures of CHA are known in the art to provide relative advantages in device performance, CHA ¶ [0003].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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