DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 26th, 2025 has been entered.
Response to Amendment
Applicant's amendment to the claims, filed on August 26th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on August 26th, 2025 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 7-11, with respect to the rejections of claims 1-5 under 35 U.S.C 102(a)(1) and 103(a) have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YI et al. (Pub. No.: US 2020/0395446 A1), hereinafter as YI.
Regarding claim 1, YI discloses an integrated circuit structure in Figs. 1 and 2, comprising: a vertical arrangement of nanowires (plurality of channel layers 120) (see Fig. 2 and [0019], [0055]); a gate stack (gate electrode 130/gate insulating film 110) over the vertical arrangements of nanowires (see Fig. 2 and [0020]); a first epitaxial source or drain structure (left source/drain region 107) at a first end of the vertical arrangement of nanowires (left end of the plurality of channel layers 120) (see Fig. 2 and [0019-0020]); and a second epitaxial source or drain structure (right source/drain region 107) at a second end of the vertical arrangement of nanowires (right end of the plurality of channel layers 120) (see Fig. 2 and [0019-0020]), wherein one or both of the first or second epitaxial source or drain structures has a central portion (second epitaxial region 107b) within an outer portion (first epitaxial region 107a), and an interface (interface between regions 107a and 107b) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion (an outermost sidewall of second epitaxial region 107a) is in contact with but does not vertically overlap with the vertical arrangement of nanowires (see Fig. 2 and [0038]).
Regarding claim 3, YI discloses the integrated circuit structure of claim 1, wherein the central portion and the outer portion comprise a same semiconductor material (both first and second epitaxial regions 107a and 107b include SiGe) (see [0038]).
Regarding claim 4, YI discloses the integrated circuit structure of claim 1, wherein the vertical arrangement of nanowires comprises silicon (see [0023]), and the first and second epitaxial source or drain structures comprise silicon and germanium (see [0038]).
Regarding claim 5, YI discloses the integrated circuit structure of claim 1, wherein the vertical arrangement of nanowires comprises silicon and germanium (see [0023]), and the first and second epitaxial source or drain structures comprise silicon and germanium (see [0038]).
Claims 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by BAE et al. (Pub. No.: US 2016/0276449 A1), hereinafter as BAE.
Regarding claim 6, BAE discloses an integrated circuit structure in Fig. 7, comprising: a fin (fin F1) (see [0029-0039]); a gate stack (gate structures 125b) over the fin (see [0027]); a first epitaxial source or drain structure (left source/drain regions 153 and 155) at a first end of the fin (left end of fin F1 in Fig. 7) (see [0057-0058]); and a second epitaxial source or drain structure (right source/drain regions 153 and 155) at a second end of the fin (right end of fin F1 in Fig. 7) (see [0057-0058]), wherein one or both of the first or second epitaxial source or drain structures has a central portion (source/drain region 155) within an outer portion (source/drain region 153), and an interface (interface between source/drain regions 153 and 155) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion is in contact with but does not vertically overlap with the fin (outermost sidewall of source/drain region 153 do not overlap with the fin F1 in Fig. 7) (see [0059-0060]).
Regarding claim 7, BAE discloses the integrated circuit structure of claim 6, wherein the central portion has an uppermost surface co-planar with an uppermost surface of the outer portion (see Fig. 7).
Regarding claim 8, BAE discloses the integrated circuit structure of claim 6, wherein the central portion and the outer portion comprise a same semiconductor material (include a first material) (see [0060]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over YI et al. (Pub. No.: US 2020/0395446 A1), hereinafter as YI, as applied to claim 1 above, in view of PARK et al. (Pub. No.: US 2022/0406919 A1), hereinafter as PARK.
Regarding claim 2, YI discloses the integrated circuit structure of claim 1, but fails to disclose wherein the central portion has an uppermost surface co-planar with an uppermost surface of the outer portion.
PARK discloses an integrated circuit in Fig. 4 comprising a first and second epitaxial source or drain structure (source/drain regions 150A) comprising a central portion (second epitaxial layer 150A2) and an outer portion (first epitaxial layer 150A1) (see [0038] and [0051]), wherein the central portion has an uppermost surface co-planar with an uppermost surface of the outer portion (uppermost surfaces of first and second epitaxial layers 150A1 and 150A2 are coplanar) (see Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the uppermost surfaces of the central portion and the outer portion of the integrated circuit structure of YI to be coplanar as same as the integrated circuit of PARK because the modified structure would improve the electrical functionality of the semiconductor device with more uniform surfaces for forming better inter-dielectric layer and higher quality device contacts.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over BAE et al. (Pub. No.: US 2016/0276449 A1), hereinafter as BAE, as applied to claim 6 above, in view of Chen et al. (Pub. No.: US 2022/0320309 A1), hereinafter as Chen.
Regarding claim 9, BAE discloses the integrated circuit structure of claim 6, wherein the vertical arrangement of nanowires comprises silicon (fin F1 include Si or SiGe) (see [0030]), but BAE fails to disclose the first and second epitaxial source or drain structures comprise silicon and germanium.
Chen discloses an integrated circuit structure in Fig. 20, comprising: a first epitaxial source or drain structure (left source/drain layers 130B/132B) at a first end of the vertical arrangement of nanowires (left end of the middle stack of semiconductor layers 110 in region 102B) (see [0045]); and a second epitaxial source or drain structure (right source/drain layers 130B/132B) at a second end of the vertical arrangement of nanowires (right end of the middle stack of semiconductor layers 110 in region 102B); and wherein the vertical arrangement of nanowires comprises silicon (semiconductor layers 110 includes silicon germanium) (see [0017]), and the first and second epitaxial source or drain structures comprise silicon and germanium (source/drain layers 130B/132B include silicon germanium) (see [0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the material of the first and second epitaxial source or drain structure of BAE to be silicon germanium as same as the material of the integrated circuit structure of Chen because having the silicon germanium as material for making the source/drain structure for integrated circuit structure would provide an advantage of controlling the stress and strain of the channel to improve carrier mobility.
Regarding claim 10, BAE discloses the integrated circuit structure of claim 6, wherein the vertical arrangement of nanowires comprises silicon germanium (fin F1 include SiGe) (see [0030]), but BAE fails to disclose the first and second epitaxial source or drain structures comprise silicon and germanium.
Chen discloses an integrated circuit structure in Fig. 20, comprising: a first epitaxial source or drain structure (left source/drain layers 130B/132B) at a first end of the vertical arrangement of nanowires (left end of the middle stack of semiconductor layers 110 in region 102B) (see [0045]); and a second epitaxial source or drain structure (right source/drain layers 130B/132B) at a second end of the vertical arrangement of nanowires (right end of the middle stack of semiconductor layers 110 in region 102B); and wherein the vertical arrangement of nanowires comprises silicon (semiconductor layers 110 includes silicon germanium) (see [0017]), and the first and second epitaxial source or drain structures comprise silicon and germanium (source/drain layers 130B/132B include silicon germanium) (see [0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the material of the first and second epitaxial source or drain structure of BAE to be silicon germanium as same as the material of the integrated circuit structure of Chen because having the silicon germanium as material for making the source/drain structure for integrated circuit structure would provide an advantage of controlling the stress and strain of the channel to improve carrier mobility.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over YI et al. (Pub. No.: US 2020/0395446 A1), hereinafter as YI and in view of BOMBERGER et al. (Pub. No.: US 2020/0303502 A1), hereinafter as Bomberger.
Regarding claim 11, YI discloses an integrated circuit structure in Figs. 1 and 2, comprising: a vertical arrangement of nanowires (plurality of channel layers 120) (see Fig. 2 and [0019], [0055]); a gate stack (gate electrode 130/gate insulating film 110) over the vertical arrangements of nanowires (see Fig. 2 and [0020]); a first epitaxial source or drain structure (left source/drain region 107) at a first end of the vertical arrangement of nanowires (left end of the plurality of channel layers 120) (see Fig. 2 and [0019-0020]); and a second epitaxial source or drain structure (right source/drain region 107) at a second end of the vertical arrangement of nanowires (right end of the plurality of channel layers 120) (see Fig. 2 and [0019-0020]), wherein one or both of the first or second epitaxial source or drain structures has a central portion (second epitaxial region 107b) within an outer portion (first epitaxial region 107a), and an interface (interface between regions 107a and 107b) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion (an outermost sidewall of second epitaxial region 107a) is in contact with but does not vertically overlap with the vertical arrangement of nanowires (see Fig. 2 and [0038]).
YI fails to disclose the integrated circuit structure is included in a component as part of a computing device comprising a board and the component coupled to the board; a memory coupled to the board, a communication chip coupled to the board and a battery coupled to the board.
Bomberger discloses a computing device (computing device 1000) comprising a board (motherboard 1002) (see Fig. 10 and [0135]); and a component including an integrated circuit structure (gate all around integrated circuit structure of processor 1004) coupled to the board, wherein the component including an integrated circuit structure (gate all around integrated circuit structure) (see [0138]); a memory (DRAM/ROM) coupled to the board (see [0136]); a communication chip (communication chip 1006) coupled to the board and a battery coupled to the board (see Fig. 10 and [0136-0137]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply and modify the integrated circuit of YI for making a computing device for having the same structure as Bomberger ‘s computing device including a board, a memory, a communication chip, and a battery with the component, the memory, communication chip and the battery coupled to the board because the modified structure would create a fully functional computing device for display and communication applications with low manufacturing cost.
Regarding claim 12, the combination of YI and Bomberger discloses the computing device of claim 11, further comprising: a memory (DRAM/ROM) coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 13, the combination of YI and Bomberger discloses the computing device of claim 11, further comprising: a communication chip coupled to the board (see Bomberger, Fig. 10 and [0137]).
Regarding claim 14, the combination of YI and Bomberger discloses the computing device of claim 11, further comprising: a battery coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 15, the combination of YI and Bomberger discloses the computing device of claim 11, wherein the component is a packaged integrated circuit die (see Bomberger, Fig.11 and [0142-0144]).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over BAE et al. (Pub. No.: US 2016/0276449 A1), hereinafter as BAE and in view of BOMBERGER et al. (Pub. No.: US 2020/0303502 A1), hereinafter as Bomberger.
Regarding claim 16, BAE discloses an integrated circuit structure in Fig. 7, comprising: a fin (fin F1) (see [0029-0039]); a gate stack (gate structures 125b) over the fin (see [0027]); a first epitaxial source or drain structure (left source/drain regions 153 and 155) at a first end of the fin (left end of fin F1 in Fig. 7) (see [0057-0058]); and a second epitaxial source or drain structure (right source/drain regions 153 and 155) at a second end of the fin (right end of fin F1 in Fig. 7) (see [0057-0058]), wherein one or both of the first or second epitaxial source or drain structures has a central portion (source/drain region 155) within an outer portion (source/drain region 153), and an interface (interface between source/drain regions 153 and 155) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion is in contact with but does not vertically overlap with the fin (outermost sidewall of source/drain region 153 do not overlap with the fin F1 in Fig. 7) (see [0059-0060]).
BAE fails to disclose the integrated circuit structure is included in a component as part of a computing device comprising a board and the component coupled to the board; a memory coupled to the board, a communication chip coupled to the board and a battery coupled to the board.
Bomberger discloses a computing device (computing device 1000) comprising a board (motherboard 1002) (see Fig. 10 and [0135]); and a component including an integrated circuit structure (gate all around integrated circuit structure of processor 1004) coupled to the board, wherein the component including an integrated circuit structure (gate all around integrated circuit structure) (see [0138]); a memory (DRAM/ROM) coupled to the board (see [0136]); a communication chip (communication chip 1006) coupled to the board and a battery coupled to the board (see Fig. 10 and [0136-0137]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply and modify the integrated circuit of BAE for making a computing device for having the same structure as Bomberger ‘s computing device including a board, a memory, a communication chip, and a battery with the component, the memory, communication chip and the battery coupled to the board because the modified structure would create a fully functional computing device for display and communication applications with low manufacturing cost.
Regarding claim 17, the combination of BAE and Bomberger discloses the computing device of claim 16, further comprising: a memory (DRAM/ROM) coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 18, the combination of BAE and Bomberger discloses the computing device of claim 16, further comprising: a communication chip coupled to the board (see Bomberger, Fig. 10 and [0137]).
Regarding claim 19, the combination of BAE and Bomberger discloses the computing device of claim 16, further comprising: a battery coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 20, the combination of BAE and Bomberger discloses the computing device of claim 16, wherein the component is a packaged integrated circuit die (see Bomberger, Fig.11 and [0142-0144]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818