DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on January 16th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on January 16th, 2026 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 8-12, with respect to the rejections of claims under 35 U.S.C 102 (a)(1) and/or 35 U.S.C 103(a) have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6 and 8-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (Pub. No.: US 2023/0100189 A1), hereinafter as Kim.
Regarding claim 1, Kim discloses an integrated circuit structure in Figs. 1-2, comprising: a vertical arrangement of nanowires (a plurality of channel layers 141, 142, 143 and 144) (see Fig. 2 and [0019]); a gate stack (gate structure 160) over the vertical arrangements of nanowires (see [0020]); a first epitaxial source or drain structure (left source/drain region 150) at a first end of the vertical arrangement of nanowires (left end) (see Fig. 2 and [0020]); a second epitaxial source or drain structure (right source/drain 150) at a second end of the vertical arrangement of nanowires (right end), wherein one or both of the first or second epitaxial source or drain structures has a central portion (second epitaxial layer 150B) within an outer portion (first epitaxial layer 150A), and an interface (interface between layers 150A and 150B) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion (outermost sidewall of first epitaxial layer 150A) is in contact with but does not vertically overlap with the vertical arrangement of nanowires (see Fig. 2), a first conductive contact (left contact plug 180) on the first epitaxial source or drain structure, the first conductive contact vertically over a top surface of the central portion (top surface of second epitaxial layer 150B of left source/drain 150) but not vertically over a top surface of the outer portion of the first epitaxial source or drain structure (top surface of first epitaxial layer 150A of left source/drain 150) and a second conductive contact (right contact plug 180) on the second epitaxial source or drain structure, the second conductive contact vertically over a top surface of the central portion (top surface of first epitaxial layer 150A of right source/drain 150) but not vertically over a top surface of the outer portion of the second epitaxial source or drain structure (top surface of second epitaxial layer 150B of left source/drain 150) (see Fig. 2 and [0020], [0035]).
Regarding claim 3, Kim discloses the integrated circuit structure of claim 1, wherein the central portion and the outer portion comprise a same semiconductor material (see [0039-0040]).
Regarding claim 4, Kim discloses the integrated circuit structure of claim 1,
wherein the vertical arrangement of nanowires comprises silicon (see [0028]), and the first and second epitaxial source or drain structures comprise silicon and germanium (see [0039-0040]).
Regarding claim 5, Kim discloses the integrated circuit structure of claim 1,
wherein the vertical arrangement of nanowires comprises silicon and germanium (see [0028]), and the first and second epitaxial source or drain structures comprise silicon and germanium (see [0039-0040]).
Regarding claim 6, Kim discloses an integrated circuit structure in Figs. 1-2, comprising: a fin (one of a plurality of channel layers 141, 142, 143 and 144) (see Fig. 2 and [0019]); a gate stack (gate structure 160) over the fin (see [0020]); a first epitaxial source or drain structure (left source/drain region 150) at a first end of the fin (left end) (see Fig. 2 and [0020]); a second epitaxial source or drain structure (right source/drain 150) at a second end of the fin (right end), wherein one or both of the first or second epitaxial source or drain structures has a central portion (second epitaxial layer 150B) within an outer portion (first epitaxial layer 150A), and an interface (interface between layers 150A and 150B) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion (outermost sidewall of first epitaxial layer 150A) is in contact with but does not vertically overlap with the fin (see Fig. 2), a first conductive contact (left contact plug 180) on the first epitaxial source or drain structure, the first conductive contact vertically over a top surface of the central portion (top surface of second epitaxial layer 150B of left source/drain 150) but not vertically over a top surface of the outer portion of the first epitaxial source or drain structure (top surface of first epitaxial layer 150A of left source/drain 150) and a second conductive contact (right contact plug 180) on the second epitaxial source or drain structure, the second conductive contact vertically over a top surface of the central portion (top surface of first epitaxial layer 150A of right source/drain 150) but not vertically over a top surface of the outer portion of the second epitaxial source or drain structure (top surface of second epitaxial layer 150B of left source/drain 150) (see Fig. 2 and [0020], [0035]).
Regarding claim 8, Kim discloses the integrated circuit structure of claim 6, wherein the central portion and the outer portion comprise a same semiconductor material (see [0039-0040]).
Regarding claim 9, Kim discloses the integrated circuit structure of claim 6,
wherein the vertical arrangement of nanowires comprises silicon (see [0028]), and the first and second epitaxial source or drain structures comprise silicon and germanium (see [0039-0040]).
Regarding claim 10, Kim discloses the integrated circuit structure of claim 6,
wherein the vertical arrangement of nanowires comprises silicon and germanium (see [0028]), and the first and second epitaxial source or drain structures comprise silicon and germanium (see [0039-0040]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Pub. No.: US 2023/0100189 A1), hereinafter as Kim, as applied to claims 1 and 6 above, and further in view of Park et al. (Pub. No.: US 2022/0406919 A1), hereinafter as Park.
Regarding claim 2, Kim discloses the integrated circuit structure of claim 1, but fails to disclose wherein the central portion has an uppermost surface co-planar with an uppermost surface of the outer portion.
PARK discloses an integrated circuit in Fig. 4 comprising a first and second epitaxial source or drain structure (source/drain regions 150A) comprising a central portion (second epitaxial layer 150A2) and an outer portion (first epitaxial layer 150A1) (see [0038] and [0051]), wherein the central portion has an uppermost surface co-planar with an uppermost surface of the outer portion (uppermost surfaces of first and second epitaxial layers 150A1 and 150A2 are coplanar) (see Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the central portion and the outer portion of Kim to have the uppermost surface co-planar with the uppermost surface of the outer portion as same as the integrated circuit of Park because the modified structure would improve the electrical functionality of the semiconductor device with more uniform surfaces for forming better inter-dielectric layer and higher quality device contacts.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Pub. No.: US 2023/0100189 A1), hereinafter as Kim in view of BOMBERGER et al. (Pub. No.: US 2020/0303502 A1), hereinafter as Bomberger.
Regarding claim 11, Kim discloses an integrated circuit structure in Figs. 1-2, comprising: a vertical arrangement of nanowires (a plurality of channel layers 141, 142, 143 and 144) (see Fig. 2 and [0019]); a gate stack (gate structure 160) over the vertical arrangements of nanowires (see [0020]); a first epitaxial source or drain structure (left source/drain region 150) at a first end of the vertical arrangement of nanowires (left end) (see Fig. 2 and [0020]); a second epitaxial source or drain structure (right source/drain 150) at a second end of the vertical arrangement of nanowires (right end), wherein one or both of the first or second epitaxial source or drain structures has a central portion (second epitaxial layer 150B) within an outer portion (first epitaxial layer 150A), and an interface (interface between layers 150A and 150B) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion (outermost sidewall of first epitaxial layer 150A) is in contact with but does not vertically overlap with the vertical arrangement of nanowires (see Fig. 2), a first conductive contact (left contact plug 180) on the first epitaxial source or drain structure, the first conductive contact vertically over a top surface of the central portion (top surface of second epitaxial layer 150B of left source/drain 150) but not vertically over a top surface of the outer portion of the first epitaxial source or drain structure (top surface of first epitaxial layer 150A of left source/drain 150) and a second conductive contact (right contact plug 180) on the second epitaxial source or drain structure, the second conductive contact vertically over a top surface of the central portion (top surface of first epitaxial layer 150A of right source/drain 150) but not vertically over a top surface of the outer portion of the second epitaxial source or drain structure (top surface of second epitaxial layer 150B of left source/drain 150) (see Fig. 2 and [0020], [0035]).
Kim fails to disclose the integrated circuit structure is included in a component as part of a computing device comprising a board and the component coupled to the board; a memory coupled to the board, a communication chip coupled to the board and a battery coupled to the board.
Bomberger discloses a computing device (computing device 1000) comprising a board (motherboard 1002) (see Fig. 10 and [0135]); and a component including an integrated circuit structure (gate all around integrated circuit structure of processor 1004) coupled to the board, wherein the component including an integrated circuit structure (gate all around integrated circuit structure) (see [0138]); a memory (DRAM/ROM) coupled to the board (see [0136]); a communication chip (communication chip 1006) coupled to the board and a battery coupled to the board (see Fig. 10 and [0136-0137]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply and modify the integrated circuit of Kim for making a computing device for having the same structure as Bomberger ‘s computing device including a board, a memory, a communication chip, and a battery with the component, the memory, communication chip and the battery coupled to the board because the modified structure would create a fully functional computing device for display and communication applications with low manufacturing cost.
Regarding claim 12, the combination of Kim and Bomberger discloses the computing device of claim 11, further comprising: a memory (DRAM/ROM) coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 13, the combination of Kim and Bomberger discloses the computing device of claim 11, further comprising: a communication chip coupled to the board (see Bomberger, Fig. 10 and [0137]).
Regarding claim 14, the combination of Kim and Bomberger discloses the computing device of claim 11, further comprising: a battery coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 15, the combination of Kim and Bomberger discloses the computing device of claim 11, wherein the component is a packaged integrated circuit die (see Bomberger, Fig.11 and [0142-0144]).
Regarding claim 16, Kim discloses an integrated circuit structure in Figs. 1-2, comprising: a fin (one of a plurality of channel layers 141, 142, 143 and 144) (see Fig. 2 and [0019]); a gate stack (gate structure 160) over the fin (see [0020]); a first epitaxial source or drain structure (left source/drain region 150) at a first end of the fin (left end) (see Fig. 2 and [0020]); a second epitaxial source or drain structure (right source/drain 150) at a second end of the fin (right end), wherein one or both of the first or second epitaxial source or drain structures has a central portion (second epitaxial layer 150B) within an outer portion (first epitaxial layer 150A), and an interface (interface between layers 150A and 150B) between the central portion and the outer portion, and wherein an outermost sidewall of the outer portion (outermost sidewall of first epitaxial layer 150A) is in contact with but does not vertically overlap with the fin (see Fig. 2), a first conductive contact (left contact plug 180) on the first epitaxial source or drain structure, the first conductive contact vertically over a top surface of the central portion (top surface of second epitaxial layer 150B of left source/drain 150) but not vertically over a top surface of the outer portion of the first epitaxial source or drain structure (top surface of first epitaxial layer 150A of left source/drain 150) and a second conductive contact (right contact plug 180) on the second epitaxial source or drain structure, the second conductive contact vertically over a top surface of the central portion (top surface of first epitaxial layer 150A of right source/drain 150) but not vertically over a top surface of the outer portion of the second epitaxial source or drain structure (top surface of second epitaxial layer 150B of left source/drain 150) (see Fig. 2 and [0020], [0035]).
Kim fails to disclose the integrated circuit structure is included in a component as part of a computing device comprising a board and the component coupled to the board; a memory coupled to the board, a communication chip coupled to the board and a battery coupled to the board.
Bomberger discloses a computing device (computing device 1000) comprising a board (motherboard 1002) (see Fig. 10 and [0135]); and a component including an integrated circuit structure (gate all around integrated circuit structure of processor 1004) coupled to the board, wherein the component including an integrated circuit structure (gate all around integrated circuit structure) (see [0138]); a memory (DRAM/ROM) coupled to the board (see [0136]); a communication chip (communication chip 1006) coupled to the board and a battery coupled to the board (see Fig. 10 and [0136-0137]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply and modify the integrated circuit of Kim for making a computing device for having the same structure as Bomberger ‘s computing device including a board, a memory, a communication chip, and a battery with the component, the memory, communication chip and the battery coupled to the board because the modified structure would create a fully functional computing device for display and communication applications with low manufacturing cost.
Regarding claim 17, the combination of Kim and Bomberger discloses the computing device of claim 16, further comprising: a memory (DRAM/ROM) coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 18, the combination of Kim and Bomberger discloses the computing device of claim 16, further comprising: a communication chip coupled to the board (see Bomberger, Fig. 10 and [0137]).
Regarding claim 19, the combination of Kim and Bomberger discloses the computing device of claim 16, further comprising: a battery coupled to the board (see Bomberger, Fig. 10 and [0136]).
Regarding claim 20, the combination of Kim and Bomberger discloses the computing device of claim 16, wherein the component is a packaged integrated circuit die (see Bomberger, Fig.11 and [0142-0144]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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