DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 212A as shown in Fig 4B. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without 1) a description of the process to form the recessed sacrificial layers 210A and 206 so they are a smaller width than patterned layers 208A, 2) subsequently forming gate spacer layer 212 to the shape disclosed in Fig 2B and 3) recessing gate spacer 212 to form 212A as shown in Fig 4B, which are critical or essential to the practice of the invention but not included in the claims. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). Claim 1 recites the limitations, “forming gate spacers over the vertical arrangement of nanowires; subsequent to forming the gate spacers, forming a permanent gate stack over the vertical arrangements of nanowires and within the gate spacers, the permanent gate stack comprising a high-k gate dielectric layer and a metal gate electrode; and subsequent to forming the permanent gate stack, forming a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires”. Claim 6 recites the limitations, “forming gate spacers over the fin; subsequent to forming the gate spacers, forming a permanent gate stack over the fin and within the gate spacers vertical arrangements of nanowires, the permanent gate stack comprising a high-k gate dielectric layer and a metal gate electrode; and subsequent to forming the permanent gate stack, forming a first epitaxial source or drain structure at a first end of the fin, and forming a second epitaxial source or drain structure at a second end of the fin”.
The Specification of the instant application states in Para [0033] of the instant application, “the stack of the plurality of nanowires 208A and patterned sacrificial material 210A may be formed...as a result of an over etch or epi undercut etch…” and then “A recess process may be performed to recess the patterned sacrificial material210A relative to the plurality of nanowires 208A”. Para [0033] additionally states, “A gate spacer 212, such as a silicon nitride spacer, may then be formed along sides of the dummy gate structure 206 and along sides of the recessed the patterned sacrificial material 210A” and Para [0035] states, “It is to be appreciated that dummy gate removal (e.g., by a wet clean process) and hi-k preclean can lead to some spacer 212 reduction”. The Specification fails to disclose essential subject matter to disclose the process steps leading to the dummy gate layer 206 and 210A being the same width and that width being less than 208A. During an over etch process, the layers 201A and 208A would be etched to the same width as the dummy gate 206. Without describing how to create the layer (208A, 210A) shapes, the Specification fails to disclose essential subject matter to disclose the process for how the spacer 212 can achieve the shape of Fig 2B. The Specification further fails to disclose essential subject matter to disclose the process for how the gate spacer layer is processed to create the shape of 212A as shown in Fig 4B.
Regarding Claims 1 and 6 there is a lack of detail in the claims and the specification to enable one of ordinary skill in the art to reproduce the invention. The creation of the functional device requires that the patterned layers 208A extend to the ends of the gate spacer (212) so they can contact the source/drain structures (216) and the enabling description to achieve that formation, shown in Fig 4B, is missing. The claims 1 and 6 and the specification of the instant application do not disclose how the patterned layers 208A are wider than the sacrificial layers 210A and the dummy gate 206. In the over etch process disclosed in Para [0033] the layers 208A and 210A would be etched to the same width as 206 as the dummy gate 206 appears to be the only masking feature for the stacked layers, but Fig 2B of the instant application shows the layers 208A as wider than 210A and 206 after the etch process so there is a lack of written description to show how to form wider layers 210A. Without the detail of how the stack layer widths are formed, it then becomes unclear how gate spacer 212 is deposited and formed to the shape disclosed in Fig 2B. The claims and the specification of the instant application also omit the process for narrowing the spacer layer 212 to form the shape of spacer layer 212A. Para [0035] merely states that “It is to be appreciated that dummy gate removal (e.g., by a wet clean process) and hi-k preclean can lead to some spacer 212 reduction”. If the dummy gate removal and hi-k clean process can lead to “some space 212 reduction” essential subject matter on removing enough of the spacer 212 to enable patterned layers 208A to extend to the edges of spacer 212, as shown in Fig 4B of the instant application, is missing. Without the missing information on how the over etch process results in a wider layer 208A than the dummy gate and the sacrificial gates 210A, how the gate spacer 212 is deposited to the form shown in Fig 2B and how the gate spacer 212 is thinned to form gate spacer 212A, one of ordinary skill in the art is not enabled to reproduce the invention of the instant application as claimed.
Claims 2-5 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, based on their dependency of independent claim 1.
Claims 7-10 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, based on their dependency of independent claim 6.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: 1) a description of the process to form the recessed sacrificial layers 210A and 206 so they are a smaller width than patterned layers 208A, 2) subsequently forming gate spacer layer 212 to the shape disclosed in Fig 2B and 3) recessing gate spacer 212 to form 212A as shown in Fig 4B. The Examiner considers these steps to be critical to the invention as their formation to create the shape as disclosed in Fig 4B is critical to creating a functional device. The specification states in Para [0033] an over etch process to pattern the fin 204 of Fig 2A. The specification also states in Para [0035] a process to create “some space 212 reduction”.
The specification fails to provide a description of steps to etch the fin 204 to get the device from Fig 2A to Fig 2B. In Fig 2B the layers 2208A are shown with a greater width than the layers 210A and the dummy gate structure 206 but the steps to get that arrangement are omitted. However, the dummy gate structure is the only feature to mask the layers 208A and 210A during an over etch so layers 208A and 210A would have the same width as dummy gate 206. Steps to get from a stack of equal widths of layers 208A and 210A after the etch to the form where dummy gate 206 and 210A are the same width and are smaller than the width of layer 208A are omitted from the claims and specification. It therefore follows that the steps to create the gate spacer 212 in the shape shown in Fig 2B are omitted as the disclosed shape can not be created without a process step to create the different widths of 208A and 210A or to disclose a process step that will enable the gate spacer 212 to create the shape of the recessed layers during the gate spacer layer. Finally, process steps to reduce the width of gate spacer to the configuration shown in Fig 4B, beyond the disclosed “some space 212 reduction” to allow the patterned layers 208A to contact the epitaxy source drain regions, have been omitted.
Claims 2-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, based on their dependency of independent claim 1.
Claims 7-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, based on their dependency of independent claim 6.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898