DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/06/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw et al. (US 20210366536 A1) hereinafter “Liaw” in view of Xie et al. (US 20210391222 A1) hereinafter “Xie.”
Regarding Claim 1, Figure 3 of Liaw teaches: An integrated circuit structure (Paragraph 0018), comprising: a sub-fin (22) in a shallow trench isolation (STI) structure (203); a plurality of vertically stacked nanowires (242; Paragraph 0030) over the sub-fin; a gate dielectric material layer (244) surrounding the vertically stacked nanowires; a gate electrode structure (262) over the gate dielectric material layer; a dielectric structure (231) laterally spaced apart (left/right) from the plurality of vertically stacked nanowires, the dielectric structure having a bottommost surface (bottom vertically of 231) below an uppermost surface (top vertically of 203) of the STI structure; and a dielectric gate plug (252) on the dielectric structure, wherein the dielectric gate plug has an uppermost surface (uppermost surface of 252) above an uppermost surface (uppermost surface of 244) of the gate dielectric layer
Liaw does not teach: wherein the gate dielectric material layer is along a sidewall of the dielectric structure
Figures 16B and 17B of Xie teach: a nanosheet stack (200a) comprising nanosheets (208a-c) and a gate dielectric material layer (1002) and a dielectric structure (402), wherein the gate dielectric material layer is along a sidewall of the dielectric structure
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric material layer be along a sidewall of the dielectric structure because Xie teaches a conformal gate dielectric is utilized to wrap around active layers as well as the gaps between the active layers (Xie Paragraph 0052).
Regarding Claim 2, Figure 3 of Liaw teaches: the dielectric structure (231) has an uppermost surface (top vertically of 231) below an uppermost surface (top vertically of uppermost 242) of the plurality of vertically stacked nanowires (242).
Regarding Claim 4, Figure 3 of Liaw teaches: the gate dielectric material layer (244) is a high-k gate dielectric layer (Paragraph 0037), and wherein the gate electrode structure (262) comprises a work-function metal layer and a conductive gate fill material (Paragraph 0037).
Regarding Claim 5, Figure 3 of Liaw teaches: the gate dielectric material layer (244) is not along sides of the dielectric gate plug (252), and wherein the gate electrode structure (262) is in contact with the sides of the dielectric gate plug.
Regarding Claim 6, Figure 3 of Liaw teaches: An integrated circuit structure (Paragraph 0018), comprising: a fin (combination of 22 and 242) having a portion (242) protruding above a shallow trench isolation (STI) structure (203); a gate dielectric material layer (244) over the protruding portion of the fin; a gate electrode structure (262) over the gate dielectric material layer; a dielectric structure (231) laterally spaced apart from the fin, the dielectric structure having a bottommost surface (bottom vertically of 231) below an uppermost surface (top vertically of 203) of the STI structure; and a dielectric gate plug (252) on the dielectric structure, wherein the dielectric gate plug has an uppermost surface (uppermost surface of 252) above an uppermost surface (uppermost surface of 244) of the gate dielectric layer
Liaw does not teach: wherein the gate dielectric material layer is along a sidewall of the dielectric structure
Figures 16B and 17B of Xie teach: a nanosheet stack (200a) comprising nanosheets (208a-c) and a gate dielectric material layer (1002) and a dielectric structure (402), wherein the gate dielectric material layer is along a sidewall of the dielectric structure
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric material layer be along a sidewall of the dielectric structure because Xie teaches a conformal gate dielectric is utilized to wrap around active layers as well as the gaps between the active layers (Xie Paragraph 0052).
Regarding Claim 7, Figure 3 of Liaw teaches: the dielectric structure (231) has an uppermost surface (top vertically of 231) below an uppermost surface (top vertically of uppermost 242) of the fin (combination of 22 and 242).
Regarding Claim 9, Figure 3 of Liaw teaches: the gate dielectric material layer (244) is a high-k gate dielectric layer (Paragraph 0037), and wherein the gate electrode structure (262) comprises a work-function metal layer and a conductive gate fill material (Paragraph 0037).
Regarding Claim 10, Figure 3 of Liaw teaches: the gate dielectric material layer (244) is not along sides of the dielectric gate plug (252), and wherein the gate electrode structure (262) is in contact with the sides of the dielectric gate plug.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw et al. (US 20210366536 A1) hereinafter “Liaw” in view of Xie et al. (US 20210391222 A1) hereinafter “Xie” and Hsieh et al. (US 20220415888 A1) hereinafter “Hsieh”.
Regarding Claim 3, the combination of Liaw and Xie teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: the dielectric gate plug is horizontally offset from the dielectric structure.
Figure 3 of Hsieh teaches: a semiconductor structure (300) with a semiconductor fin structures (114a), a dielectric structure (130) and a dielectric gate plug (210) is horizontally offset from the dielectric structure
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric gate plug be horizontally offset from the dielectric structure because Hsieh teaches the gate cut can be aligned or misaligned with the dielectric structure and still be utilized as a gate line-end definition structure (Hsieh Paragraph 0092).
Regarding Claim 8, the combination of Liaw and Xie teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: the dielectric gate plug is horizontally offset from the dielectric structure.
Figure 3 of Hsieh teaches: a semiconductor structure (300) with a semiconductor fin structures (114a), a dielectric structure (130) and a dielectric gate plug (210) is horizontally offset from the dielectric structure
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric gate plug be horizontally offset from the dielectric structure because Hsieh teaches the gate cut can be aligned or misaligned with the dielectric structure and still be utilized as a gate line-end definition structure (Hsieh Paragraph 0092).
Regarding Claim 8, Liaw teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: the dielectric gate plug is horizontally offset from the dielectric structure.
Figure 3 of Hsieh teaches: a semiconductor structure (300) with a semiconductor fin structures (114a), a dielectric structure (130) and a dielectric gate plug (210) is horizontally offset from the dielectric structure
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric gate plug be horizontally offset from the dielectric structure because Hsieh teaches the gate cut can be aligned or misaligned with the dielectric structure and still be utilized as a gate line-end definition structure (Hsieh Paragraph 0092).
Claims 11- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw et al. (US 20210366536 A1) hereinafter “Liaw” in view of Xie et al. (US 20210391222 A1) hereinafter “Xie” and Ma et al. (US 20200185501 A1) hereinafter “Ma.”
Regarding Claim 11, Figure 3 of Liaw teaches: a component (Paragraph 0018; SRAM) including an integrated circuit structure (Paragraph 0018), comprising: a sub-fin (22) in a shallow trench isolation (STI) structure (203); a plurality of vertically stacked nanowires (242; Paragraph 0030) over the sub-fin; a gate dielectric material layer (244) surrounding the vertically stacked nanowires; a gate electrode structure (262) over the gate dielectric material layer; a dielectric structure (231) laterally spaced apart from the plurality of vertically stacked nanowires, the dielectric structure having a bottommost surface (bottom vertically of 231) below an uppermost surface (top vertically of 203) of the STI structure; and a dielectric gate plug (252) on the dielectric structure wherein the dielectric gate plug has an uppermost surface (uppermost surface of 252) above an uppermost surface (uppermost surface of 244) of the gate dielectric layer
Liaw does not teach: A computing device, comprising: a board; and a component coupled to the board
Figure 21 of Ma teaches: A computing device (1400), comprising a board (Paragraph 0144) that utilizes components (Paragraph 0143) comprising integrated circuits (Paragraph 0143).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a computing device, comprising a board and a component coupled to the board because Ma teaches integrated circuit devices are commonly used in computing devices that include boards and one or more components (Ma Paragraph 0143).
Liaw does not teach: wherein the gate dielectric material layer is along a sidewall of the dielectric structure
Figures 16B and 17B of Xie teach: a nanosheet stack (200a) comprising nanosheets (208a-c) and a gate dielectric material layer (1002) and a dielectric structure (402), wherein the gate dielectric material layer is along a sidewall of the dielectric structure
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric material layer be along a sidewall of the dielectric structure because Xie teaches a conformal gate dielectric is utilized to wrap around active layers as well as the gaps between the active layers (Xie Paragraph 0052).
Regarding Claim 12, the combination of Liaw, Xie, and Ma and teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: a memory coupled to the board.
Figure 21 of Ma teaches: a memory (1404) coupled to the board (Paragraph 0144)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a memory coupled to the board because Ma teaches a memory device is commonly used in computing devices as suitable for the application (Ma Paragraph 0144).
Regarding Claim 13, the combination of Liaw, Xie, and Ma teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: a communication chip coupled to the board.
Figure 21 of Ma teaches: a communication chip (1412) coupled to the board (Paragraph 0144)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a communication chip coupled to the board because Ma teaches a communication chip is commonly used in computing devices as suitable for the application (Ma Paragraph 0144).
Regarding Claim 14, the combination of Liaw, Xie, and Ma teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: the component is a packaged integrated circuit die
Figure 20 of Ma teaches: a component is a packaged integrated circuit die (Paragraph 0139)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the component be a packaged integrated circuit die because Ma teaches a package integrated circuit die is a common component in computing devices (Ma Paragraph 0140).
Regarding Claim 15, the combination of Liaw, Xie, and Ma teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Figure 21 of Ma teaches: the component (Paragraph 0144) is selected from a group consisting of a processor (Paragraph 0146), a communications chip (Paragraph 0147), and a digital signal processor (Paragraph 0146).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor because Ma teaches processors, communication chips, and digital signal processors are commonly used in computing devices as suitable for the application (Ma Paragraph 0144).
Regarding Claim 16, Figure 3 of Liaw teaches: a component (Paragraph 0018; SRAM) including an integrated circuit structure (Paragraph 0018), comprising: a fin (combination of 22 and 242) having a portion (242) protruding above a shallow trench isolation (STI) structure (203); a gate dielectric material layer (244) over the protruding portion of the fin; a gate electrode structure (262) over the gate dielectric material layer; a dielectric structure (231) laterally spaced apart from the fin, the dielectric structure having a bottommost surface (bottom vertically of 231) below an uppermost surface (top vertically of 203) of the STI structure; and a dielectric gate plug (252) on the dielectric structure, wherein the dielectric gate plug has an uppermost surface (uppermost surface of 252) above an uppermost surface (uppermost surface of 244) of the gate dielectric layer
Liaw does not teach: A computing device, comprising: a board; and a component coupled to the board
Figure 21 of Ma teaches: A computing device (1400), comprising a board (Paragraph 0144) that utilizes components (Paragraph 0143) comprising integrated circuits (Paragraph 0143).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a computing device, comprising a board and a component coupled to the board because Ma teaches integrated circuit devices are commonly used in computing devices that include boards and one or more components (Ma Paragraph 0143).
Liaw does not teach: wherein the gate dielectric material layer is along a sidewall of the dielectric structure
Figures 16B and 17B of Xie teach: a nanosheet stack (200a) comprising nanosheets (208a-c) and a gate dielectric material layer (1002) and a dielectric structure (402), wherein the gate dielectric material layer is along a sidewall of the dielectric structure
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric material layer be along a sidewall of the dielectric structure because Xie teaches a conformal gate dielectric is utilized to wrap around active layers as well as the gaps between the active layers (Xie Paragraph 0052).
Regarding Claim 17, the combination of Liaw, Xie, and Ma teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: a memory coupled to the board.
Figure 21 of Ma teaches: a memory (1404) coupled to the board (Paragraph 0144)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a memory coupled to the board because Ma teaches a memory device is commonly used in computing devices as suitable for the application (Ma Paragraph 0144).
Regarding Claim 18, the combination of Liaw, Xie, and Ma teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: a communication chip coupled to the board.
Figure 21 of Ma teaches: a communication chip (1412) coupled to the board (Paragraph 0144)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a communication chip coupled to the board because Ma teaches a communication chip is commonly used in computing devices as suitable for the application (Ma Paragraph 0144).
Regarding Claim 19, the combination of Liaw, Xie, and Ma teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: the component is a packaged integrated circuit die.
Figure 20 of Ma teaches: a component is a packaged integrated circuit die (Paragraph 0139)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the component be a packaged integrated circuit die because Ma teaches a package integrated circuit die is a common component in computing devices (Ma Paragraph 0140).
Regarding Claim 20, the combination of Liaw, Xie, and Ma teaches all of the limitations of the claimed invention as stated above.
Liaw does not teach: the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Figure 21 of Ma teaches: the component (Paragraph 0144) is selected from a group consisting of a processor (Paragraph 0146), a communications chip (Paragraph 0147), and a digital signal processor (Paragraph 0146).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor because Ma teaches processors, communication chips, and digital signal processors are commonly used in computing devices as suitable for the application (Ma Paragraph 0144).
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 11/06/2025, with respect to the rejections of Claims 1 and 6 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Liaw and Xie.
Applicant’s arguments, see Applicant’s Remarks, filed 11/06/2025, with respect to the rejections of Claims 11 and 16 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Liaw, Xie, and Ma.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891