DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 8-13, 17-18 and 20-29 are pending in this application. Claims 1, 3, 8-9, 17-18, 20, 22, 26 and 29 are currently amended; claims 13, 21, 23-25 and 27-28 are previously presented; claims 10-12 are original; claims 2, 4-7, 14-16 and 19 are canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 8-10, 12-13, 17-18, 20-23, 25-27 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chih et al. (NPL – “16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications”), hereinafter Chih.
Regarding claim 1, Chih teaches a computing method configured to perform bit-serial multiplication in a compute-in memory (CIM) device, the computing method comprising (Chih page 252 left col second paragraph):
determining at least one input according to a type of an application (Chih page 252 left col second paragraph);
receiving the at least one input by an input driver circuit (Chih Fig. 16.4.1)
determining at least one weight according to a training result or a configuration of a user (Chih page 252 left col second paragraph; right col second and fourth paragraphs);
storing the at least one weight in a memory cell of a memory array (Chih Fig. 16.4.1; page 252 left col third paragraph);
outputting, by the input driver circuit, respective bits of the at least one input in successive multiplication cycles from a most significant bit (MSB) of the at least one input toward a least significant bit (LSB) of the at least one input (Chi Figs. 16.4.1 and 16.4.2 and page 252 left col fourth paragraph);
performing the bit-serial multiplication based on the respective bits of the at least one input and the at least one weight, by a multiply circuit, to generate a plurality of partial- products (Chih page 252 left col second and fourth paragraphs; Fig. 16.4.1 and 16.4.2; multiply circuit – multipliers; plurality of partial-products – output of the multipliers/adder tree);
sequentially storing the plurality of partial-products in a second register connected in a partial- product path from an output terminal of the multiply circuit to a second input terminal of an adder circuit (Chih page 252 left col fourth paragraph; Fig. 16.4.1 and 16.4.2; a second register – bottom left register; adder circuit – 20b adder);
storing successive partial- sums generated by the adder circuit in a first register connected to an output terminal of the adder circuit (Chih page 252 left col fourth paragraph; Fig. 16.4.2; first register – register left of the shifter);
left-shifting by a shifter circuit connected in a feedback path from an output terminal of the first register to a first input terminal of the adder circuit, each successive partial- sum received from the first register by one bit and supplying the left-shifted successive partial-sum to the first input terminal of the adder circuit (Chih page 252 left col fourth paragraph; Fig. 16.4.2);
during each multiplication cycle after a first multiplication cycle:
receiving, by the adder circuit through the feedback path, a one-bit-left-shifted partial-sum generated during an immediately preceding multiplication cycle (Chih page 252 left col fourth paragraph; Fig. 16.4.2);
receiving, by the adder circuit through the partial-product path, a partial-product corresponding to an input bit immediately lower in significance than an input bit processed during the immediately preceding multiplication cycle (Chih page 252 left col fourth paragraph; Fig. 16.4.2);
adding, by the adder circuit, the one-bit-left-shifted partial-sum and the partial-product to generate a next partial-sum (Chih page 252 left col fourth paragraph; Fig. 16.4.2);
storing the next partial-sum in the first register (Chih page 252 left col fourth paragraph; Fig. 16.4.2); and
performing, by the shifter circuit, each partial-sum shifting operation used by the adder circuit to accumulate the plurality of partial-products (Chih page 252 left col fourth paragraph; Fig. 16.4.2).
Regarding claim 3, Chih teaches all the limitations of claim 1 as stated above. Further, Chih teaches wherein the input comprises a plurality of inputs, and wherein performing the bit-serial multiplication comprises: generating respective pluralities of partial-products corresponding to the plurality of inputs (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2 plurality of inputs – input activation).
Regarding claim 22, Chih teaches all the limitations of claim 1 as stated above. Further, Chih teaches further comprising storing a final accumulated result output by the adder circuit in a third register after accumulating the plurality of partial-products (Chih Fig. 16.4.2; third register – register right of the adder).
Regarding claim 23, Chih teaches all the limitations of claim 1 as stated above. Further, Chih teaches wherein performing the bit-serial multiplication includes a logic NOR operation (Chih page 252 left col third paragraph; Fig. 16.4.2).
Regarding claim 25, Chih teaches all the limitations of claim 1 as stated above. Further, Chih teaches wherein the memory cell is a static random access memory (SRAM) memory cell (Chih page 252 left col third paragraph; Fig. 16.4.1).
Regarding claim 26, Chih teaches all the limitations of claim 1 as stated above. Further, Chih teaches wherein each successive partial sum generated by the adder circuit is stored in the first register and thereafter supplied through the shifter circuit to the adder circuit during a subsequent multiplication cycle (Chih page 252 left col fourth paragraph; Fig. 16.4.2).
Regarding claim 8, Chih teaches a device, comprising:
an adder having a first input terminal, a second input terminal, and an output terminal (Chih Fig. 16.4.2 adder – 20b adder);
a shifter having an output terminal operably connected to the first input terminal of the adder (Chih Fig. 16.4.2 shifter - shifter block left of the adder);
a first register having an input terminal operably connected to the output terminal of the adder and configured to store successive partial-sums generated by the adder wherein the shifter is connected in a feedback path from an output terminal of the first register to the first input terminal of the adder, the shifter being configured to left-shift by one bit each successive partial-sum received from the first register and supply the left-shifted successive partial-sum to the first input terminal of the adder (Chih Fig. 16.4.2 first register - register left of the shifter);
a second register configured to sequentially store partial-products and supply each stored partial-product to the second input terminal of the adder (Chih Fig. 16.4.2 second register - register receiving and outputting PSUM<11:0>);
a multiplier configured to perform a bit-serial multiplication based on an input signal and a weight signal in successive multiplication cycles from a most significant bit (MSB) of the input signal toward a least significant bit (LSB) of the input signal to generate a plurality of partial-products, wherein the second register is operably connected in a partial-product path from an output terminal of the multiplier to the second input terminal of the adder (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2; multiplier - multipliers; input signal – input activation; weight signal - weights);
wherein during each multiplication cycle after a first multiplication cycle, the adder is configured to receive through the feedback path a one-bit-left-shifted partial-sum generated during an immediately preceding multiplication cycle, receive through the partial- product path a partial-product corresponding to an input bit immediately lower in significance than an input bit processed during the immediately preceding multiplication cycle, and output a next partial-sum for storage in the first register (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2); and
wherein the shifter is configured to perform each partial-sum shifting operation used by the adder to accumulate the plurality of partial-products (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2).
Regarding claim 9, Chih teaches all the limitations of claim 8 as stated above. Further, Chih teaches further comprising a third register having an input terminal that is operably connected to the output terminal of the adder and configured to store a final accumulated result generated after accumulation of the plurality of partial-products (Chih Fig. 16.4.2; third register – register on the right of the adder).
Regarding claim 10, Chih teaches all the limitations of claim 8 as stated above. Further, Chih teaches wherein the multiplier comprises a NOR gate (Chih page 252 left col third paragraph; Figs. 16.4.1-2).
Regarding claim 12, Chih teaches all the limitations of claim 8 as stated above. Further, Chih teaches further comprising a memory array configured to store the weight signal (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2; memory array – array of memory cells).
Regarding claim 13, Chih teaches all the limitations of claim 12 as stated above. Further, Chih teaches wherein the memory array includes a plurality of static random access memory (SRAM cells) (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2).
Regarding claim 17, Chih teaches all the limitations of claim 8 as stated above. Further, Chih teaches wherein the second register is positioned in the partial-product path such that each partial product generated by the multiplier is stored in the second register before being supplied to the adder for addition to a partial sum received through the feedback path (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.2).
Regarding claim 18, Chih teaches a device, comprising:
a memory array storing a weight signal (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2; memory array – array of memory cells);
an input driver configured to output respective bits of an input signal in successive multiplication cycles from a most significant bit (MSB) of the input signal toward a least significant bit (LSB) of the input signal(Chih Fig. 16.4.1 input driver - input driver);
a multiplier configured to perform a bit-serial multiplication of the input signal and the weight signal to generate a plurality of partial-products corresponding to the respective bits of the input signal (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2; multiplier – multipliers);
an adder having a first input terminal, a second input terminal, and an output terminal (Chih Fig. 16.4.2; adder – 20b adder);
a first register having an input terminal operably connected to the output of the adder and configured to store successive partial sums generated by the adder (Chih Fig. 16.4.2; first register – register to the left of the shifter block);
a shifter operably connected in a feedback path from an output of the first register and an output terminal operably connected to the first input terminal of the adder, the shifter being configured to left-shift by one bit each successive partial sum received from the first input terminal of the adder (Chih Fig. 16.4.2; shifter - shifter);
a second register operably connected in a partial-product path from an output terminal of the multiplier to the second input terminal of the adder, the second register configured to sequentially store the plurality of partial products and supply each stored partial-product to the second input terminal of the adder(Chih Fig. 16.4.2 second register - register receiving and outputting PSUM<11:0>);
wherein, during each multiplication cycle after a first multiplication cycle, the adder is configured to receive through the feedback path a one-bit-left-shifted partial-sum generated during an immediately preceding multiplication cycle, receive through the partial-product path a partial-product corresponding to an input bit immediately lower in significance than an input bit processed during the immediately preceding multiplication cycle, and output a next partial-sum for storage in the first register (Chih page 252 left col fourth paragraph; Fig. 16.4.2);
wherein the shifter is configured to perform each partial-sum shifting operation used by the adder to accumulate the plurality of partial-products (Chih page 252 left col fourth paragraph; Fig. 16.4.2).
Regarding claim 20, Chih teaches all the limitations of claim 18 as stated above. Further, Chih teaches further comprising a third register having an input terminal that is operably connected to the output terminal of the adder and configured to store a final accumulated result generated after accumulation of the plurality of partial-products (Chih Fig. 16.4.2; third register – register on the right of the adder).
Regarding claim 21, Chih teaches all the limitations of claim 18 as stated above. Further, Chih teaches wherein the memory array includes a plurality of static random access memory (SRAM cells) (Chih page 252 left col second-fourth paragraphs; Figs. 16.4.1-2).
Regarding claim 27, Chih teaches all the limitations of claim 18 as stated above. Further, Chih teaches wherein the multiplier comprises a NOR gate (Chih page 252 left col third paragraph; Fig. 16.4.2).
Regarding claim 29, Chih teaches all the limitations of claim 18 as stated above. Further, Chih teaches wherein the second register is positioned in the partial-product path such that each partial product generated by the multiplier is stored in the second register before being supplied to the adder for addition to a partial sum received through the feedback path (Chih Fig. 16.4.2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 24 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Chih as applied to claims 8, 1 and 18 above, and further in view of Liu et al. (US 10853066 B1), hereinafter Liu.
Regarding claim 11, Chih teaches all the limitations of claim 8 as stated above.
Chih does not explicitly teach wherein the multiplier comprises an AND gate.
However, on the same field of endeavor, Liu discloses a multiplier that comprises an AND gate (Liu Figs. 5-6 and col 6 lines 6-10; AND gate – AND circuitry).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Chih using Liu by replacing the NOR gates with AND gates for performing the bit-wise multiplication and generating the partial products. One of ordinary skill in the art could have substituted the NOR gates/circuitry for AND gates/circuitry, and the results of the substitution would have been predictable because both logic gates are able to generate partial products for performing a multiplication of two input operands. See MPEP 2141 III (B) for more information.
Therefore, the combination of Chih as modified in view of Liu teaches wherein the multiplier comprises an AND gate.
Regarding claim 24, Chih teaches all the limitations of claim 1 as stated above.
Chih does not explicitly teach wherein performing the bit-serial multiplication includes a logic AND operation.
However, on the same field of endeavor, Liu discloses performing a bit-serial multiplication using a logic AND operation (Liu Figs. 5-6 and col 6 lines 6-10).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Chih using Liu by replacing the NOR gates with AND gates for performing the bit-wise multiplication and generating the partial products. One of ordinary skill in the art could have substituted the NOR gates/circuitry for AND gates/circuitry, and the results of the substitution would have been predictable because both logic gates are able to generate partial products for performing a multiplication of two input operands. See MPEP 2141 III (B) for more information.
Therefore, the combination of Chih as modified in view of Liu teaches wherein performing the bit-serial multiplication includes a logic AND operation.
Regarding claim 28, Chih teaches all the limitations of claim 18 as stated above.
Chih does not explicitly teach wherein the multiplier comprises an AND gate.
However, on the same field of endeavor, Liu discloses a multiplier that comprises an AND gate (Liu Figs. 5-6 and col 6 lines 6-10; AND gate – AND circuitry).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Chih using Liu by replacing the NOR gates with AND gates for performing the bit-wise multiplication and generating the partial products. One of ordinary skill in the art could have substituted the NOR gates/circuitry for AND gates/circuitry, and the results of the substitution would have been predictable because both logic gates are able to generate partial products for performing a multiplication of two input operands. See MPEP 2141 III (B) for more information.
Therefore, the combination of Chih as modified in view of Liu teaches wherein the multiplier comprises an AND gate.
Response to Arguments
In view of amendments made, the 35 U.S.C. 112(b) rejection of claims 1, 3, 18 and 20-29 has been withdrawn.
In view of amendments made, the 35 U.S.C. 103 rejection of claims 1, 3, 8-13, 17-18 and 20-29 over Liu in view of various references has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2182 (571)272-5767
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