CTNF 17/558,291 CTNF 79362 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Applicant’s Amendment and Arguments 07-38-02 AIA Applicant’s arguments, see remarks on page 11, line 12 to page 16, line 4 , filed February 17 th , 2026 , with respect to the rejection(s) of claim(s) 1 and 21 under 102(a)(1) as being anticipated by Malik (U.S. Pub. 2021/0035881) and the rejection of claims 10 and 18 under 103 as being unpatentable over Malik in view of Lau et al. (U.S. Pub. 2010/0213600) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly discovered reference to Anderson et al. (U.S. Pub. 2012/0119296). Claims 1-30 are pending in the present application in which claims 9 and 22-24 have been withdrawn from further consideration as being drawn to non-elected invention . Claim Objections Claims 26-30 are objected to under 37 CFR 1.75 as being a substantial duplicate of claims 2-6, respectively. Appropriate correction is required. 12-256 New Ground of Rejection Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-7, 21, and 25-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (U.S. Pub. 2021/0035881) in view of Anderson et al. (U.S. Pub. 2012/0119296) . In re claim 1, Mallik discloses a semiconductor subassembly, comprising: a first layer including one or more dies 221/222 (see paragraph [0024] and figs. 2B-F), and an encapsulation material 250 encapsulating the one or more dies 221/222 (see paragraph [0025] and figs. 2B-F); a second layer 210 adjacent the first layer and electrically coupled thereto, the second layer including a substrate 203 (see paragraph [0034] and figs. 2E-F); a solid component 270 disposed on the first layer; and an interface layer disposed between and mechanically bonding the solid component 270 and the first layer, the interface layer providing a direct dielectric-to-dielectric bond including a first dielectric sublayer 260 directly adjacent the first layer (see paragraph [0027] and figs. 2E-F), and a second dielectric sublayer 275 directly adjacent the first dielectric sublayer 260 (see paragraph [0031] and figs. 2E-F, note that the second dielectric sublayer 275 can be made of SiO 2 ). PNG media_image1.png 434 670 media_image1.png Greyscale Malik discloses that the second dielectric sublayer 275 can be formed of SiO 2 (see paragraph [0031]) but is silent to wherein the second dielectric sublayer including an amorphous material. However, Anderson discloses in a same field of endeavor, a semiconductor subassembly, including, inter-alia, wherein the second dielectric sublayer (104,114) including silicon dioxide (SiO 2 ) or an amorphous material (see paragraph [0059]). Anderson further discloses that these low-k materials may operate to reduce the capacitance of the interconnect structure. Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Anderson into the semiconductor subassembly of Malik in order to have the second dielectric sublayer in Malik to include an amorphous material since Anderson suggested that SiO 2 and amorphous material are interchangeable for using as the second dielectric sublayer in the semiconductor assembly in order to reduce the capacitance of the interconnect structure. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re claim 2, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the solid component 270 includes a silicon (Si) material or a silicon carbide (SiC) material (see paragraph [0031] of Malik, note that the solder component can be made of a silicon material) . In re claim 3, as applied to claim 1 above, since Mallik discloses that the solid component is a heat spreader 280 that includes a bulk substrate 270 and a bond material 275 and the bond material may have any of the compositions of (e.g., solder, Cu, Au, SiO 2 , polymer) (see paragraph [0031]), it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to select Cu or Au as a material of the solid component in order to improve heat dissipation for the semiconductor subassembly because of its high thermal conductivity. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re claim 4, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the interface layer includes at least one of a Si material or a SiC material (see paragraphs [0027], [0031] of Malik). In re claim 5, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the second dielectric sublayer includes siloxane bonds (see paragraphs [0022], [0030], [0031] of Malik and paragraph [0059] of Anderson). In re claim 6, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the first dielectric sublayer 260 includes at least one of a SiN material, a SiO 2 material, or a SiCN material (see paragraph [0027] of Malik, note that the first dielectric sublayer 260 can be of SiO 2 ). In re claim 7, as applied to claim 1 above, Mallik discloses that the interface layer ha a thickness of less than 10 µm or even less than 1 µm (see paragraph [0031]) but is silent to wherein the interface layer has a thickness between about 1 micron and about 2 microns, and the second dielectric sublayer has a thickness between about 4 nm and about 12 nm. However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art during routine experimentation to optimize the thickness range of the interface layer to be between about 1 micron and about 2 microns and the second dielectric sublayer to be between about 4 nm and about 12 nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. “It is not inventive to discover optimum or workable ranges by routine experimentation”, In re Aller, 105 USPQ 233, 235 . In re claim 21, Mallik discloses a method to form a semiconductor subassembly of a semiconductor package, the semiconductor subassembly including: providing a plurality of first dies (221,222) (see paragraph [0023] and figs. 2B-F); providing an encapsulation layer 250 on the plurality of first dies (221,222) to form a first layer of the semiconductor subassembly (see paragraph [0025] and figs. 2B-F); providing a first dielectric layer 260 over the first layer to form a first-layer-and-first-dielectric-layer-subassembly; providing a solid component 270; providing a second dielectric layer 275 on the solid component 270 to form a solid-component-and-second-dielectric-layer-subassembly (see paragraph [0031]] and fig. 2E-F); forming an interface layer between and mechanically bonding the solid component 270 and the first layer, the interface layer providing a direct dielectric-to-dielectric bond including a first dielectric sublayer 260 directly adjacent the first layer and formed from the first dielectric layer, and a second dielectric sublayer 275 directly adjacent the first dielectric sublayer, formed from the second dielectric layer (see paragraph [0031] and figs. 2E-F); providing a second layer including a substrate 203; and electrically coupling the substrate203 to the plurality of first dies (221,222) (see paragraphs [0021], [0023], [0034] and figs. 2E-F). Malik discloses that the second dielectric sublayer 275 can be formed of SiO 2 (see paragraph [0031]) but is silent to wherein the second dielectric sublayer including an amorphous material. However, Anderson discloses in a same field of endeavor, a semiconductor subassembly, including, inter-alia, wherein the second dielectric sublayer (104,114) including silicon dioxide (SiO 2 ) or an amorphous material (see paragraph [0059]). Anderson further discloses that these low-k materials may operate to reduce the capacitance of the interconnect structure. Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Anderson into the semiconductor subassembly of Malik in order to have the second dielectric sublayer in Malik to include an amorphous material since Anderson suggested that SiO 2 and amorphous material are interchangeable for using as the second dielectric sublayer of the semiconductor subassembly in order to reduce the capacitance of the interconnect structure. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re claim 25, as applied to claim 21 above, Mallik in combination with Anderson discloses wherein the solid component 270 includes a silicon (Si) material or a silicon carbide (SiC) material (see paragraph [0031] of Malik, note that the solid component 270 can be made of silicon ). In re claim 26, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the solid component 270 includes a silicon (Si) material or a silicon carbide (SiC) material (see paragraph [0031] of Malik, note that the solder component can be made of a silicon material) . In re claim 27, as applied to claim 1 above, since Mallik discloses that the solid component is a heat spreader 280 that includes a bulk substrate 270 and a bond material 275 and the bond material may have any of the compositions of (e.g., solder, Cu, Au, SiO 2 , polymer) (see paragraph [0031]), it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to select Cu or Au as a material of the solid component in order to improve heat dissipation for the semiconductor subassembly because of its high thermal conductivity. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re claim 28, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the interface layer includes at least one of a Si material or a SiC material (see paragraphs [0027], [0031] of Malik). In re claim 29, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the second dielectric sublayer includes siloxane bonds (see paragraphs [0022], [0030], [0031] of Malik and paragraph [0059] of Anderson). In re claim 30, as applied to claim 1 above, Mallik in combination with Anderson discloses wherein the first dielectric sublayer 260 includes at least one of a SiN material, a SiO 2 material, or a SiCN material (see paragraph [0027] of Malik, note that the first dielectric sublayer 260 can be of SiO 2 ) . 07-21-aia AIA Claim (s) 10-13, 15, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (U.S. Pub. 2021/0035881) in view of Anderson et al. (U.S. Pub. 2012/0119296) and Lau et al. (U.S. Pub. 2010/0213600) . In re claim 10, Mallik discloses a semiconductor package including: a package substrate 203 (see paragraph [0021] and figs. 2B-F); and a semiconductor subassembly disposed on the package substrate 203 and including: a first layer including one or more first dies 221 (see paragraph [0024] and figs. 2B-F), and an encapsulation material 250 encapsulating the one or more first dies 221 ; a second layer 210 adjacent the first layer and electrically coupled thereto, the second layer including a substrate 203 (see paragraph [0021] and figs. 2B-F); a solid component 270 disposed on the first layer; and an interface layer disposed between and mechanically bonding the solid component 270 and the first layer, the interface layer providing a direct dielectric-to-dielectric bond including a first dielectric sublayer 260 directly adjacent the first layer (see paragraph [0027] and figs. 2E-F), and a second dielectric sublayer 275 directly adjacent the first dielectric sublayer 260 (see paragraph [0031] and figs. 2E-F); one or more second dies 222 disposed on the package substrate 203 adjacent the semiconductor subassembly (see paragraph [0024] and figs. 2B-F). Malik discloses that the second dielectric sublayer 275 can be formed of SiO 2 (see paragraph [0031]) but is silent to wherein the second dielectric sublayer including an amorphous material. However, Anderson discloses in a same field of endeavor, a semiconductor subassembly, including, inter-alia, wherein the second dielectric sublayer (104,114) including silicon dioxide (SiO 2 ) or an amorphous material (see paragraph [0059]). Anderson further discloses that these low-k materials may operate to reduce the capacitance of the interconnect structure. Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Anderson into the semiconductor subassembly of Malik in order to have the second dielectric sublayer in Malik to include an amorphous material since Anderson suggested that SiO 2 and amorphous material are interchangeable for using as the second dielectric sublayer in the semiconductor package in order to reduce the capacitance of the interconnect structure. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Mallik is further silent to wherein a heat spreader disposed over the semiconductor subassembly and the one or more second dies; and a thermal interface material (TIM) layer coupled to the heat spreader at one side thereof, and to respective ones of the semiconductor subassembly and the one or more dies at another side thereof. However, Lau discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a heat spreader 114 disposed over the semiconductor subassembly and the one or more second dies 118A (see paragraph [0038] and fig. 1); and a thermal interface material (TIM) layer 116 coupled to the heat spreader 114 at one side thereof, and to respective ones of the semiconductor subassembly and the one or more dies 118A at another side thereof (see paragraph [0038] and fig. 1) in order to provide further cooling for the high power chips. Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Lau into the semiconductor package of Mallik in order to enable a heat spreader disposed over the semiconductor subassembly and the one or more second dies; and a thermal interface material (TIM) layer coupled to the heat spreader at one side thereof, and to respective ones of the semiconductor subassembly and the one or more dies at another side thereof in Mallik to be formed in order to provide further cooling for the one or more first dies and one or more second dies. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR) , 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 11, as applied to claim 10 above, Mallik in combination with Anderson and Lau discloses wherein the TIM layer extends between a bottom surface of the heat spreader and top surfaces of the solid component and top surfaces of the one or more second dies (see paragraph [0031] and fig. 2E of Mallik and paragraph [0038] and fig. 1 of Lau). Note that, when the heat spreader and the TIM layer of Lau is incorporate into the semiconductor package of Mallik, the TIM layer would be extending between the bottom surface of the heat spreader and the top surfaces of the solid component and the top surfaces of the one or more second dies. In re claim 12, as applied to claim 11 above, Mallik in combination with Anderson and Lau discloses wherein the top surfaces of the solid component and the top surfaces of the one or more first dies are substantially coplanar (see paragraph [0031] and fig. 2E of Mallik). In re claim 13, as applied to claim 10 above, Mallik in combination with Anderson and Lau discloses wherein the heat spreader includes a lid 102 and a plurality of legs 106, wherein the lid 102 of the heat spreader is directly on a top surface of the TIM layer 116, and wherein the plurality of legs 106 of the heat spreader are directly on a top surface of the package substrate 108 (see paragraphs [0038], [0044] and fig. 1 of Lau). In re claim 15, as applied to claim 10 above, Mallik in combination with Anderson and Lau discloses wherein the one or more second dies include high-bandwidth memory (HBM) dies (see paragraph [0023] of Mallik). In re claim 17, as applied to claim 10 above, Mallik in combination with Anderson and Lau discloses wherein the semiconductor subassembly includes a plurality of semiconductor subassemblies, and the solid component 270 includes a plurality of solid components individual ones of which are disposed on respective first layers of the plurality of semiconductor subassemblies (see paragraph [0031] and figs. 2E-F of Mallik). In re claim 18, Mallik discloses an integrated circuit (IC) device assembly including: a plurality of integrated circuit components, individual ones of the plurality of integrated circuit components including one or more semiconductor packages, individual ones of the one or more semiconductor packages including: a package substrate 203 (see paragraph [0021] and figs. 2A-F); and a semiconductor subassembly disposed on the package substrate 203 and including: a first layer including one or more first dies 221 (see paragraph [0023] and figs. 2B-F), and an encapsulation material 250 encapsulating the one or more first dies 221 (see paragraph [0025] and figs. 2B-F); a second layer 210 adjacent the first layer and electrically coupled thereto (see paragraph [0021] and figs. 2B-F), the second layer including a substrate 203; a solid component 270 disposed on the first layer (see paragraph [0031] and figs. 2B-F); and an interface layer disposed between and mechanically bonding the solid component 270 and the first layer, the interface layer providing a direct dielectric-to-dielectric bond including a first dielectric sublayer 260 directly adjacent the first layer, and a second dielectric sublayer 275 directly adjacent the first dielectric sublayer (see paragraph [0031] and figs. 2E-F); one or more second dies 222 disposed on the package substrate 203 adjacent the semiconductor subassembly (see paragraph [0025] and figs. 2E-F). Malik discloses that the second dielectric sublayer 275 can be formed of SiO 2 (see paragraph [0031]) but is silent to wherein the second dielectric sublayer including an amorphous material. However, Anderson discloses in a same field of endeavor, a semiconductor subassembly, including, inter-alia, wherein the second dielectric sublayer (104,114) including silicon dioxide (SiO 2 ) or an amorphous material (see paragraph [0059]). Anderson further discloses that these low-k materials may operate to reduce the capacitance of the interconnect structure. Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Anderson into the semiconductor subassembly of Malik in order to have the second dielectric sublayer in Malik to include an amorphous material since Anderson suggested that SiO 2 and amorphous material are interchangeable for using as the second dielectric sublayer in the integrated circuit device assembly in order to reduce the capacitance of the interconnect structure. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Mallik is further silent to wherein the integrated circuit (IC) device assembly including: a printed circuit board; and a plurality of integrated circuit components coupled to the printed circuit board and a heat spreader disposed over the semiconductor subassembly and the one or more second dies; a thermal interface material (TIM) layer coupled to the heat spreader at one side thereof, and to respective ones of the semiconductor subassembly and the one or more first dies at another side thereof. However, Lau discloses in a same field of endeavor, an integrated circuit (IC) device assembly including: a printed circuit board 112; and a plurality of integrated circuit components (124A,124B) coupled to the printed circuit board 112 and a heat spreader 102 disposed over the semiconductor subassembly and the one or more second dies 118A; a thermal interface material (TIM) layer 116 coupled to the heat spreader 102 at one side thereof, and to respective ones of the semiconductor subassembly and the one or more first dies 118B at another side thereof (see paragraphs [0032], [0038] and fig. 1). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Lau into the semiconductor package of Mallik in order to enable wherein the integrated circuit (IC) device assembly including: a printed circuit board; and a plurality of integrated circuit components coupled to the printed circuit board and a heat spreader disposed over the semiconductor subassembly and the one or more second dies; a thermal interface material (TIM) layer coupled to the heat spreader at one side thereof, and to respective ones of the semiconductor subassembly and the one or more first dies at another side thereof in Mallik to be formed in order to provide further cooling for the one or more first dies and the one or more second dies. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR) , 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 19, as applied to claim 18 above, Mallik in combination with Anderson and Lau discloses wherein the TIM layer extends between a bottom surface of the heat spreader and top surfaces of the solid component and top surfaces of the one or more first dies (see paragraph [0031] and fig. 2E of Mallik and paragraph [0038] and fig. 1 of Lau). Note that, when the heat spreader and the TIM layer of Lau is incorporate into the integrated circuit of Mallik, the TIM layer would be extending between the bottom surface of the heat spreader and the top surfaces of the solid component and the top surfaces of the one or more first dies. In re claim 20, as applied to claim 19 above, Mallik in combination with Lau discloses wherein the top surfaces of the solid component and the top surfaces of the one or more first dies are substantially coplanar (see paragraph [0031] and fig. 2E of Mallik) . 07-22-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (U.S. Pub. 2021/0035881) in view of Anderson et al. (U.S. Pub. 2012/0119296) and Lau et al. (U.S. Pub. 2010/0213600) , as applied to claim 10 above, and further in view of Renavikar et al. (U.S. Pub. 2007/0131737) . In re claim 16, as applied to claim 10 above, Mallik, Anderson and Lau are silent to wherein the TIM layer includes a solder TIM (STIM), and wherein the solid component coupled to the TIM layer with a backside metallization (BSM) layer. However, Renavikar discloses in a same field of endeavor, a semiconductor package, including, inter-alia, wherein the TIM layer 112 includes a solder TIM (STIM), and wherein the solid component 110 coupled to the TIM layer 112 with a backside metallization (BSM) layer 128 (see paragraphs [0017], [0018], [0019] and fig. 1). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Renavikar into the semiconductor package of Mallik in order to enable wherein the TIM layer includes a solder TIM (STIM), and wherein the solid component coupled to the TIM layer with a backside metallization (BSM) layer in Mallik to be formed in order to facilitating in transferring heat away from the semiconductor package . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 8 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Primary Examiner, Art Unit 2892 Application/Control Number: 17/558,291 Page 2 Art Unit: 2892 Application/Control Number: 17/558,291 Page 3 Art Unit: 2892 Application/Control Number: 17/558,291 Page 4 Art Unit: 2892 Application/Control Number: 17/558,291 Page 5 Art Unit: 2892 Application/Control Number: 17/558,291 Page 6 Art Unit: 2892 Application/Control Number: 17/558,291 Page 7 Art Unit: 2892 Application/Control Number: 17/558,291 Page 8 Art Unit: 2892 Application/Control Number: 17/558,291 Page 9 Art Unit: 2892 Application/Control Number: 17/558,291 Page 10 Art Unit: 2892 Application/Control Number: 17/558,291 Page 11 Art Unit: 2892 Application/Control Number: 17/558,291 Page 12 Art Unit: 2892 Application/Control Number: 17/558,291 Page 13 Art Unit: 2892 Application/Control Number: 17/558,291 Page 14 Art Unit: 2892 Application/Control Number: 17/558,291 Page 15 Art Unit: 2892 Application/Control Number: 17/558,291 Page 16 Art Unit: 2892 Application/Control Number: 17/558,291 Page 17 Art Unit: 2892 Application/Control Number: 17/558,291 Page 18 Art Unit: 2892
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