DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
This Office Action is in response to Applicant’s reply filed 21 July 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 2, 5, 6 and 8-10 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Izuha et al. (U.S. Pub. 2004/0113209) in view of Michael et al. (U.S. Patent 6,146,978) in view of Ishikawa (U.S. Pub. 2005/0017303).
Claim 1: Izuha et al. discloses an integrated circuit structure, in Fig. 1 and in paragraphs 23-27, comprising:
a gate electrode (5) above a portion of a substrate (1), the substrate comprising silicon;
a first source or drain region (SO) adjacent a first side (left side) of the gate electrode;
a second source or drain region (DR) adjacent a second side (right side) of the gate electrode, the second side opposite the first side;
a first sidewall spacer (left 8) along the first side (left side) of the gate electrode (5), and a second sidewall spacer (right 8) along the second side (right side) of the gate electrode (8);
a silicide layer (10a on the left) on the first source or drain region;
a trench contact (13-1 and 14-1) on the silicide layer, the trench contact in a dielectric layer (12) and laterally adjacent the gate electrode, wherein the trench contact has a width (width of 13-1 and 14-1), the width entirely within a footprint (width of SO) of the first source or drain region, and wherein the trench contact comprises:
a barrier layer (13-1) on the silicide layer, the barrier layer comprising titanium and nitrogen; and
a conductive material (14-1) on the barrier layer;
wherein the dielectric layer is over the gate electrode, and wherein a top surface (top surface of 12) of the dielectric layer is substantially co-planar with a top surface of the trench contact (top surface of 13-1 and 14-1);
a via connector (16-1) on the trench contact.
Izuha et al. appears not to explicitly disclose the silicide layer comprising titanium,
wherein the trench contact has a length greater than the width.
Michael et al, however, discloses titanium is a suitable material for a silicide layer (column 6, lines 35-47), and
the trench contact (462) has a length (length of 462 in vertical direction) greater than a width (width of 462 in horizontal direction) in order to increase surface area coupling (Fig. 6; column 6, lines 48-65).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Izuha et al. with the disclosure of Michael et al. to have made the silicide comprise titanium because the selection of a known material based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein); and to have made the trench contact has a length greater than the width in order to increase surface area coupling (column 6, lines 48-65 of Michael et al.).
Izuha et al. also appears not to explicitly disclose the conductive material comprising cobalt, and
a metallization layer on the via connector, the metallization layer extending laterally beyond outmost sides of the via connector along a direction from the first source or drain region to the second source or drain region, and the metallization layer vertically overlapping with the first sidewall spacer.
Ishikawa, however, in Fig. 6E and in paragraph 117, discloses cobalt is a suitable material for a conductive material for a trench contact (317); and in Fig. 6E and in paragraphs 111, 112, and 117, a metallization layer (horizontal portion of 320 on the left) on the via connector (vertical portion of 320 on the left), the metallization layer (horizontal portion of 320 on the left) extending laterally beyond outmost sides (left and right sides of the vertical portion of 320 on the left) of the via connector (vertical portion of 320 on the left) along a direction (horizontal direction) from the first source or drain region (left 310) to the second source or drain region (right 310), and the metallization layer (horizontal portion of 320 on the left) vertically overlapping with the first sidewall spacer (second 308 from the right).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Izuha et al. with the disclosure of Ishikawa to have made the conductive material comprising cobalt because the selection of a known material based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein); and to have made a metallization layer on the via connector, the metallization layer extending laterally beyond outmost sides of the via connector along a direction from the first source or drain region to the second source or drain region, and the metallization layer vertically overlapping with the first sidewall spacer in order provide an electrical connection to the via connector.
Claim 2: Izuha et al. in view of Michael et al. in view of Ishikawa discloses the integrated circuit structure of claim 1, and Izuha et al., in Fig. 1 and in paragraph 26, discloses further comprising:
a gate contact (14-3) on the gate electrode (5), the gate contact having a top surface (top surface of 14-3) co-planar with the top surface (top surface of 12) of the dielectric layer (12).
Claim 5: Izuha et al. in view of Michael et al. in view of Ishikawa discloses the integrated circuit structure of claim 1, and Izuha et al., in Fig. 1 and in paragraph 26, discloses further comprising:
a second silicide layer (10a on the right) on the second source or drain region (DR); and
a second trench contact (13-2 and 14-2) on the second silicide layer.
Claim 6: Izuha et al. in view of Michael et al. in view of Ishikawa discloses the integrated circuit structure of claim 5, and Izuha et al., in Fig. 1 and in paragraph 27, discloses further comprising:
a via connector (16-2) on the second trench contact (13-2 and 14-2).
Claim 8: Izuha et al. in view of Michael et al. in view of Ishikawa discloses the integrated circuit structure of claim 1.
Izuha et al. in view of Michael et al. in view of Ishikawa, as applied to claim 1, appears not to explicitly disclose wherein the trench contact length extends along an entirety of a length of the first source or drain region.
Michael et al., however, in Fig 6, column 6, lines 48-65, further discloses the trench contact length (length of 462 in vertical direction) extends along an entirety of a length (length of 422 in vertical direction) of the first source or drain region (422) in order to increase surface area coupling.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Izuha et al. in view of Michael et al. in view of Ishikawa, as applied to claim 1, with the further disclosure of Michael et al. to have made the trench contact length extends along an entirety of a length of the first source or drain region in order to increase surface area coupling (column 6, lines 48-65 of Michael et al.).
Claim 9: Izuha et al. in view of Michael et al. in view of Ishikawa discloses integrated circuit structure of claim 1, and Izuha et al., in Fig. 1, further discloses wherein an entirety of the trench contact width (width of 13-1 and 14-1 in the horizontal direction) is vertically over the first source or drain region (SO).
Claim 10: Izuha et al. in view of Michael et al. in view of Ishikawa discloses integrated circuit structure of claim 1, and Izuha et al., in Fig. 1, further discloses wherein the first source or drain region (SO) extends laterally (laterally in the horizontal direction) beyond the trench contact (13-1 and 14-1).
Response to Arguments
Applicant's arguments filed 21 July 2025 have been fully considered but they are not persuasive.
Applicant contends Michael et al. does not disclose the metallization vertically overlapping with the first sidewall spacer.
Examiner notes that Ishikawa is relied upon for the disclosure. Ishikawa, discloses, in Fig. 6E and in paragraphs 111, 112, and 117, a metallization layer (horizontal portion of 320 on the left) on the via connector (vertical portion of 320 on the left), the metallization layer (horizontal portion of 320 on the left) extending laterally beyond outmost sides (left and right sides of the vertical portion of 320 on the left) of the via connector (vertical portion of 320 on the left) along a direction (horizontal direction) from the first source or drain region (left 310) to the second source or drain region (right 310), and the metallization layer (horizontal portion of 320 on the left) vertically overlapping with the first sidewall spacer (second 308 from the right).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.L/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815