Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4 – 12, and 14 – 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20050091627A1 (Satapathy) in view of US20110004857A1 (Hopkins) in view of US20200134108A1 (Possignolo) and further in view of US20110047521A1 (Binder).
In regards to claim 1, (Satapathy) shows a method, comprising:
determining primary cuts of a first network of a netlist and secondary cuts of an engineering change order (ECO) circuit network; Satapathy [0019] teaches comparing a reference netlist 44, which corresponds to the claimed first network, to a modified netlist 48, which corresponds to the claimed ECO circuit network. Paragraphs 21 and 22 teach that the netlists 44 and 48 are divided into hierarchical modules, each module including any number of design elements. The modules of the reference netlist 44 are interpreted as the claimed primary cuts, and the modules of the modified netlist 48 are interpreted as the claimed secondary cuts.
wherein the primary cuts are at least a portion of the first network, and include one or more logic elements of the first network, and an output at a top level of the first network; Satapathy [0021] teaches that the original design is divided into modules, like building blocks. These modules include things like cells, wires, and pins, which match the idea of primary cuts that contain important parts of the network. Satapathy [0021] specifically mentions that the top module "foo" includes two inputs (A1 and A2) and an output (Z), which aligns with the claim's description of an output at the top level of the first network. In Figure 4B, Satapathy shows specific cells like foo.ul, foo.u2, and foo.u4.u5. These cells represent parts of the primary cuts, with logic elements inside them. For example, flip-flop u5 in Figure 4B shows a specific logic element that would be part of a primary cut.
the secondary cuts are a least a portion of the ECO circuit network, and include one or more logic elements of the ECO circuit network, and an output at a top level of the ECO circuit network; Satapathy [0020] teaches comparing a reference netlist 44, which corresponds to the claimed first network, to a modified netlist 48, which corresponds to the claimed ECO circuit network. Paragraphs 21 and 22 teach that the netlists 44 and 48 are divided into hierarchical modules, each module including any number of design elements. The modules of the reference netlist 44 are interpreted as the claimed primary cuts, and the modules of the modified netlist 48 are interpreted as the claimed secondary cuts.
updating the netlist based on the downward frontier; Satapathy [0044 - 0048] teaches that when the system finds a change (like a new wire or a change in hierarchy), it determines how far down the design that change impacts other parts of the netlist. This is referred to as determining the downward frontier, which outlines the extent to which the changes affect the modified design Satapathy [0044]. Once the downward frontier is established, the system updates the netlist accordingly. Satapathy [0047] illustrates this process by explaining how certain parts are disconnected (e.g., disconnect foo.u4.u5 D), and [0048] describes how nets are renamed (e.g., rename_net foo.u4.u5 D foo.u4.n_n) to reflect these changes. The system ensures that all relevant parts of the modified design are updated, aligning with the concept of updating the netlist based on the downward frontier as described in the claim.
Satapathy differs from the claimed invention in that it does not explicitly disclose generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts, wherein the difference corresponds to the first primary cut including a buffer; determining that a first cut of the second primary cuts and a second cut of the secondary cuts are matching cuts based on a comparison of a first truth table of the first cut with a second truth table of the second cut; determining, by a processor, a downward frontier of the ECO circuit network from the matching cuts by including at least one logic element of the one or more logic elements of the ECO circuit network within the second cut based on a comparison of the first truth table with an updated second truth table of the second cut, wherein the updated second truth table is based on the at least one logic element.
Hopkins teaches determining that a first cut of the second primary cuts and a second cut of the secondary cuts are matching cuts based on a comparison of a first truth table of the first cut with a second truth table of the second cut; Hopkins [0063-0064] teaches finding permutations of inputs where Boolean functions F and F* are equivalent which serves as determining matching cuts between circuits. Hopkins [0072] teaches truth tables are computed for both subcircuits and Boolean matching is done with manipulations on the truth table bitsets which provides direct comparison of first and second truth tables. Hopkins [0077] teaches checking if F* equals F to determine if subcircuits are matched based on truth table comparison.
Hopkins teaches determining, by a processor, a downward frontier of the ECO circuit network from the matching cuts by including at least one logic element of the one or more logic elements of the ECO circuit network within the second cut based on a comparison of the first truth table with an updated second truth table of the second cut, wherein the updated second truth table is based on the at least one logic element; Hopkins [0080] teaches recursively extending Boolean matching along sub branches of matched subcircuits to derive maximal size subcircuits which represents determining a downward frontier by including additional logic elements. Hopkins [0082-0083] teaches that when subcircuits like D and D* are matched, the algorithm is recursively called on corresponding inputs which updates the truth table comparison as more elements are included in the frontier.
Hopkins differs from the claimed invention in that it does not explicitly disclose generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts, wherein the difference corresponds to the first primary cut including a buffer;
Possignolo teaches generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts; Possignolo [0063 - 0065] and Possignolo Table 1 teaches comparing each component of a second structural netlist against a corresponding component of a first structural netlist, identifying components where a difference exists between the two netlists, and removing those differing components to produce a refined set of matching components. This teaches generating second primary cuts from primary cuts by removing a first primary cut based on a difference between that cut and a second primary cut.
Possignolo differs from the claimed invention in that it does not explicitly disclose wherein the difference corresponds to the first primary cut including a buffer;
Binder teaches wherein the difference corresponds to the first primary cut including a buffer; Binder [0020] explicitly identifies buffers as a specific and recognizable gate type that creates a difference when comparing netlist path representations, teaching that the presence of a buffer in one path versus another is an identifiable distinction. This maps directly to the limitation requiring that the difference between the first primary cut and the second primary cut corresponds to the first primary cut including a buffer.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to improve the efficiency and accuracy of identifying matching subcircuits by using truth table-based Boolean matching techniques. Hopkins' approach provides a more precise method for determining functional equivalence between circuit portions, allowing for better identification of matching cuts that can be leveraged in Satapathy's ECO generation process. This combination enhances the ability to identify and isolate changes between netlist versions, resulting in more targeted and efficient ECO implementations.
The motivation to combine Satapathy, Hopkins, and Possignolo at the effective filing date of the invention is to reduce the number of candidate cuts requiring truth table-based Boolean matching by first applying Possignolo's structural component-removal technique to filter differing components from the primary cuts. This improves the scalability and efficiency of Satapathy's ECO generation process when applied to large netlists.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder at the effective filing date of the invention is to provide a specific technical basis for Possignolo's cut-filtering step by identifying cuts whose distinguishing difference corresponds to the presence of a buffer. Binder teaches that buffers are a recognizable gate type that creates an identifiable difference between netlist paths, enabling more precise filtering of primary cuts prior to Boolean matching.
In regards to claim 2, (Satapathy) shows the method of claim 1:
Wherein determining the matching cuts comprises reducing a number of at least one of the primary cuts and the secondary cuts: Satapathy [0038] teaches that when mismatches are found, the system reduces the number of unmatched cuts by comparing and generating ECOs, which aligns with Claim 2's requirement of reducing the number of primary and secondary cuts.
In regards to claim 4, (Satapathy) does not show the method of claim 1: wherein determining the matching cuts comprises matching the first cut with the second cut based on the first cut and the second cut having a same size parameter.
Hopkins teaches wherein determining the matching cuts comprises matching the first cut with the second cut based on the first cut and the second cut having a same size parameter; Hopkins [0074] teaches checking whether number of inputs in both functions is the same and checking sizes of symmetry classes which represents matching based on size parameters.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to enhance the matching process by incorporating size-based parameters, which provides a more structured approach to comparing circuit cuts. Hopkins' technique of matching based on input counts and symmetry class sizes allows for more efficient initial filtering of potential matching candidates, reducing the computational overhead of the truth table comparison process used in Satapathy's ECO generation.
In regards to claim 5, (Satapathy) shows the method of claim 1:
wherein determining the downward frontier of the ECO circuit network comprises identifying an input of the ECO circuit network to include in the downward frontier. Satapathy [0020] teaches how the system identifies hierarchical design elements like cells, nets, and pins as part of the comparison process, ensuring that inputs in the ECO circuit network are included in the downward frontier to determine necessary updates and modifications.
In regards to claim 6, (Satapathy) shows the method of claim 5:
wherein the identifying the input of the ECO circuit network comprises determining a functionality of the second cut is unchanged by the input. Satapathy [0043] teaches the original and modified netlists to detect changes in functionality. The comparator tool 52 compares the net map of the modified netlist (ECO circuit network) with the reference netlist, looking for any changes. Satapathy [0044] teaches that there are two scenarios, one where a new net is added, and another where a change in net hierarchies is detected.
In regards to claim 7, (Satapathy) shows the method of claim 5:
wherein identifying the input of the ECO circuit network to include in the downward frontier generates an updated downward frontier, and wherein the netlist is updated based on the updated downward frontier based on a comparison of the downward frontier to the first cut. Satapathy [0044] and [0047] teaches how the design is updated based on differences found during the comparison of the original (first cut) and modified designs.
In regards to claim 8, (Satapathy) does not show the method of claim 1: wherein determining the matching cuts comprises determining the first truth table for the first cut and the second truth table for the second cut;
Hopkins teaches wherein determining the matching cuts comprises determining the first truth table for the first cut and the second truth table for the second cut; Hopkins [0072] teaches truth tables are computed for both subcircuits and Boolean matching is done with manipulations on the truth table bitsets which directly addresses generating and comparing first and second truth tables.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to introduce a more robust method for determining functional equivalence between circuit portions. Hopkins' truth table computation approach provides a mathematical foundation for comparing circuit functionality that complements Satapathy's structural comparison methods. This combination enables more accurate identification of matching cuts even when the structural implementations differ, improving the overall quality of the ECO process.
In regards to claim 9, (Satapathy) shows the method of claim 8:
wherein, based on a determination that the first truth table does not match the second truth table, functional permutations of one or more of the first cut and the second cut are determined, and the matching cuts are determined based on the functional permutations; Satapathy [0035] and [0038] - [0039] teaches comparing the reference netlist 44 (first cut) and the modified netlist 48 (second cut) to identify differences and generate Engineering Change Orders (ECOs) when mismatches are found.
Satapathy differs from the claimed invention in that it does not explicitly disclose truth tables or functional permutations.
Hopkins [0072] teaches using truth tables to compare circuits and resolve mismatches through Boolean matching and functional permutations, which can be applied when mismatches are found.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to incorporate advanced Boolean matching techniques that can identify functional equivalence even when input ordering or structural implementation differs. Hopkins' approach to truth table manipulation and functional permutation extends Satapathy's comparison capabilities beyond simple structural matching, allowing the system to identify more complex relationships between circuit implementations and generate more comprehensive ECOs.
In regards to claim 10, (Satapathy) shows the method of claim 1:
wherein updating the netlist based on the downward frontier comprises updating the netlist with the ECO circuit network excluding the downward frontier; Satapathy [0047 - 0048] teaches how the system selectively updates the design based on detected differences, excluding certain parts (the downward frontier) that don’t require changes. The overall update process is triggered based on the system's identification of changes, Satapathy describes how the system selectively updates the design based on detected differences, excluding certain parts (the downward frontier) that don’t require changes. The overall update process is triggered based on the system's identification of changes.
In regards to claim 11 (Satapathy) shows a system comprising:
a memory storing instructions; a processor, coupled with the memory to execute the instructions, the instructions when executed cause the processor to: Satapathy [0016]-[0018] teaches design engineers executing multiple design automation tools on computers which implies memory storing instructions and processors executing those instructions. Satapathy [0006] teaches computer implementation of the design process which further supports the presence of memory and processor components. Satapathy [0042 - 0044] teaches automated generation of ECOs which requires processor execution of stored instructions to perform the comparison and generation process.
determining primary cuts of a first network of a netlist and secondary cuts of an engineering change order (ECO) circuit network; Satapathy [0019] teaches comparing a reference netlist 44, which corresponds to the claimed first network, to a modified netlist 48, which corresponds to the claimed ECO circuit network. Paragraphs 21 and 22 teach that the netlists 44 and 48 are divided into hierarchical modules, each module including any number of design elements. The modules of the reference netlist 44 are interpreted as the claimed primary cuts, and the modules of the modified netlist 48 are interpreted as the claimed secondary cuts.
wherein the primary cuts are at least a portion of the first network, and include one or more logic elements of the first network, and an output at a top level of the first network; Satapathy [0021] teaches that the original design is divided into modules, like building blocks. These modules include things like cells, wires, and pins, which match the idea of primary cuts that contain important parts of the network. Satapathy [0021] specifically mentions that the top module "foo" includes two inputs (A1 and A2) and an output (Z), which aligns with the claim's description of an output at the top level of the first network. In Figure 4B, Satapathy shows specific cells like foo.ul, foo.u2, and foo.u4.u5. These cells represent parts of the primary cuts, with logic elements inside them. For example, flip-flop u5 in Figure 4B shows a specific logic element that would be part of a primary cut.
the secondary cuts are a least a portion of the ECO circuit network, and include one or more logic elements of the ECO circuit network, and an output at a top level of the ECO circuit network; Satapathy [0020] teaches comparing a reference netlist 44, which corresponds to the claimed first network, to a modified netlist 48, which corresponds to the claimed ECO circuit network. Paragraphs 21 and 22 teach that the netlists 44 and 48 are divided into hierarchical modules, each module including any number of design elements. The modules of the reference netlist 44 are interpreted as the claimed primary cuts, and the modules of the modified netlist 48 are interpreted as the claimed secondary cuts.
updating the netlist based on the downward frontier; Satapathy [0044 - 0048] teaches that when the system finds a change (like a new wire or a change in hierarchy), it determines how far down the design that change impacts other parts of the netlist. This is referred to as determining the downward frontier, which outlines the extent to which the changes affect the modified design Satapathy [0044]. Once the downward frontier is established, the system updates the netlist accordingly. Satapathy [0047] illustrates this process by explaining how certain parts are disconnected (e.g., disconnect foo.u4.u5 D), and [0048] describes how nets are renamed (e.g., rename_net foo.u4.u5 D foo.u4.n_n) to reflect these changes. The system ensures that all relevant parts of the modified design are updated, aligning with the concept of updating the netlist based on the downward frontier as described in the claim.
Satapathy differs from the claimed invention in that it does not explicitly disclose generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts, wherein the difference corresponds to the first primary cut including a buffer; determining that a first cut of the second primary cuts and a second cut of the secondary cuts are matching cuts based on a comparison of a first truth table of the first cut with a second truth table of the second cut; determining a downward frontier of the ECO circuit network from the matching cuts by including at least one logic element of the one or more logic elements of the ECO circuit network within the second cut based on a comparison of the first truth table with an updated second truth table of the second cut, wherein the updated second truth table is based on the at least one logic element.
Hopkins teaches determining that a first cut of the second primary cuts and a second cut of the secondary cuts are matching cuts based on a comparison of a first truth table of the first cut with a second truth table of the second cut; Hopkins [0063-0064] teaches finding permutations of inputs where Boolean functions F and F* are equivalent which serves as determining matching cuts between circuits. Hopkins [0072] teaches truth tables are computed for both subcircuits and Boolean matching is done with manipulations on the truth table bitsets which provides direct comparison of first and second truth tables. Hopkins [0077] teaches checking if F* equals F to determine if subcircuits are matched based on truth table comparison.
Hopkins teaches determining a downward frontier of the ECO circuit network from the matching cuts by including at least one logic element of the one or more logic elements of the ECO circuit network within the second cut based on a comparison of the first truth table with an updated second truth table of the second cut, wherein the updated second truth table is based on the at least one logic element; Hopkins [0080] teaches recursively extending Boolean matching along sub branches of matched subcircuits to derive maximal size subcircuits which represents determining a downward frontier by including additional logic elements. Hopkins [0082-0083] teaches that when subcircuits like D and D* are matched, the algorithm is recursively called on corresponding inputs which updates the truth table comparison as more elements are included in the frontier.
Hopkins differs from the claimed invention in that it does not explicitly disclose generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts, wherein the difference corresponds to the first primary cut including a buffer;
Possignolo teaches generate second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts; Possignolo [0063 - 0065] and Possignolo Table 1 teaches comparing each component of a second structural netlist against a corresponding component of a first structural netlist, identifying components where a difference exists between the two netlists, and removing those differing components to produce a refined set of matching components. This teaches generating second primary cuts from primary cuts by removing a first primary cut based on a difference between that cut and a second primary cut.
Possignolo differs from the claimed invention in that it does not explicitly disclose wherein the difference corresponds to the first primary cut including a buffer;
Binder teaches wherein the difference corresponds to the first primary cut including a buffer; Binder [0020] explicitly identifies buffers as a specific and recognizable gate type that creates a difference when comparing netlist path representations, teaching that the presence of a buffer in one path versus another is an identifiable distinction. This maps directly to the limitation requiring that the difference between the first primary cut and the second primary cut corresponds to the first primary cut including a buffer.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to enhance the ECO generation process with more sophisticated functional comparison methods. Hopkins' truth table-based approach provides a systematic way to determine when two circuit portions perform the same function, even if their implementations differ structurally. This functional equivalence detection complements Satapathy's hierarchical comparison method, enabling more precise identification of which portions of the circuit need to be modified in the ECO process.
The motivation to combine Satapathy, Hopkins, and Possignolo at the effective filing date of the invention is to reduce the number of candidate cuts requiring truth table-based Boolean matching by first applying Possignolo's structural component-removal technique to filter differing components from the primary cuts. This improves the scalability and efficiency of Satapathy's ECO generation process when applied to large netlists.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder at the effective filing date of the invention is to provide a specific technical basis for Possignolo's cut-filtering step by identifying cuts whose distinguishing difference corresponds to the presence of a buffer. Binder teaches that buffers are a recognizable gate type that creates an identifiable difference between netlist paths, enabling more precise filtering of primary cuts prior to Boolean matching.
In regards to claim 12, (Satapathy) shows the system of claim 11:
wherein determining the matching cuts comprises reducing a number of at least one of the primary cuts and the secondary cuts: Satapathy [0038] teaches that when mismatches are found, the system reduces the number of unmatched cuts by comparing and generating ECOs, which aligns with claim 12's requirement of reducing the number of primary and secondary cuts.
In regards to claim 14, (Satapathy) shows the system of claim 11:
wherein determining the downward frontier of the ECO circuit network comprises determining an input of the ECO circuit network to include in the downward frontier. Satapathy [0020] teaches how the system identifies hierarchical design elements like cells, nets, and pins as part of the comparison process, ensuring that inputs in the ECO circuit network are included in the downward frontier to determine necessary updates and modifications.
In regards to claim 15, (Satapathy) does not show the system of claim 11: wherein determining the matching cuts comprises determining the first truth table for the first cut and the second truth table for the second cut;
Hopkins teaches wherein determining the matching cuts comprises determining the first truth table for the first cut and the second truth table for the second cut; Hopkins [0072] teaches truth tables are computed for both subcircuits and Boolean matching is done with manipulations on the truth table bitsets which directly addresses generating and comparing first and second truth tables.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to improve the accuracy of matching cuts by incorporating functional verification through truth table analysis. Hopkins' method provides a mathematical basis for determining equivalence between circuit portions that goes beyond structural comparison, enabling Satapathy's ECO generation process to more precisely identify which portions of the circuit are functionally equivalent despite potential structural differences.
In regards to claim 16, (Satapathy) shows the system of claim 15:
wherein, based on a determination that the first truth table does not match the second truth table, functional permutations of one or more of the first cut and the second cut are determined, and the matching cuts are determined based on the functional permutations; Satapathy [0035], [0038] - [0039] teaches comparing the reference netlist 44 (first cut) and the modified netlist 48 (second cut) to identify differences and generate Engineering Change Orders (ECOs) when mismatches are found.
Satapathy differs from the claimed invention in that it does not explicitly disclose truth tables or functional permutations.
Hopkins [0072] teaches using truth tables to compare circuits and resolve mismatches through Boolean matching and functional permutations, which can be applied when mismatches are found.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to address the challenge of identifying functionally equivalent circuits with different input orderings or internal implementations. Hopkins' approach to functional permutations and truth table manipulation extends Satapathy's comparison capabilities, allowing the system to recognize when two cuts perform the same function despite having different structures, thus improving the accuracy and efficiency of the ECO generation process.
In regards to claim 17 Satapathy shows:
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to: Satapathy [0016]-[0018] teaches design engineers executing design automation tools on computers which implies a non-transitory computer readable medium with instructions executed by a processor. Satapathy [0006] teaches computer implementation of the design process which further supports the presence of stored instructions executed by a processor. Satapathy [0042]-[0044] teaches automated generation of ECOs which requires processor execution of stored instructions to perform the comparison and generation process.
determine primary cuts of a first network of a netlist and secondary cuts of an Engineering Change Order (ECO) circuit network based on a size parameter corresponding to a number of input nodes; Satapathy [0019] teaches comparing a reference netlist 44, which corresponds to the claimed first network, to a modified netlist 48, which corresponds to the claimed ECO circuit network. Paragraphs 21 and 22 teach that the netlists 44 and 48 are divided into hierarchical modules, each module including any number of design elements. The modules of the reference netlist 44 are interpreted as the claimed primary cuts, and the modules of the modified netlist 48 are interpreted as the claimed secondary cuts.
wherein the primary cuts include at least one logic element of the first network, and an output at a top level of the first network, and the secondary cuts include at least one logic element of the ECO circuit network, and an output at a top level of the ECO circuit network; Satapathy [0021] teaches that the original design is divided into modules, like building blocks. These modules include things like cells, wires, and pins, which match the idea of primary cuts that contain important parts of the network. Satapathy [0021] specifically mentions that the top module "foo" includes two inputs (A1 and A2) and an output (Z), which aligns with the claim's description of an output at the top level of the first network. In Figure 4B, Satapathy shows specific cells like foo.ul, foo.u2, and foo.u4.u5. These cells represent parts of the primary cuts, with logic elements inside them. For example, flip-flop u5 in Figure 4B shows a specific logic element that would be part of a primary cut.
update the netlist based on the downward frontier; Satapathy [0044 - 0048] teaches that when the system finds a change (like a new wire or a change in hierarchy), it determines how far down the design that change impacts other parts of the netlist. This is referred to as determining the downward frontier, which outlines the extent to which the changes affect the modified design Satapathy [0044]. Once the downward frontier is established, the system updates the netlist accordingly. Satapathy [0047] illustrates this process by explaining how certain parts are disconnected (e.g., disconnect foo.u4.u5 D), and [0048] describes how nets are renamed (e.g., rename_net foo.u4.u5 D foo.u4.n_n) to reflect these changes. The system ensures that all relevant parts of the modified design are updated, aligning with the concept of updating the netlist based on the downward frontier as described in the claim.
Satapathy differs from the claimed invention in that it does not explicitly disclose generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts, wherein the difference corresponds to the first primary cut including a buffer; determine that a first cut of the second primary cuts and a second cut of the secondary cuts are matching cuts based on a comparison of truth table of the first cut with a second truth table of the second cut; determine a downward frontier of the ECO circuit network by increasing a volume of the second cut and based on a comparison of the first truth table and an updated second truth table of the second cut; wherein the volume of the second cut corresponds to a number of gates of the second cut and the updated second truth table is based on the increased volume.
Hopkins teaches determine that a first cut of the second primary cuts and a second cut of the secondary cuts are matching cuts based on a comparison of truth table of the first cut with a second truth table of the second cut; Hopkins [0063-0064] teaches finding permutations of inputs where Boolean functions F and F* are equivalent which serves as determining matching cuts between circuits. Hopkins [0072] teaches truth tables are computed for both subcircuits and Boolean matching is done with manipulations on the truth table bitsets which provides direct comparison of first and second truth tables. Hopkins [0077] teaches checking if F* equals F to determine if subcircuits are matched based on truth table comparison.
Hopkins teaches determine a downward frontier of the ECO circuit network by increasing a volume of the second cut and based on a comparison of the first truth table and an updated second truth table of the second cut; wherein the volume of the second cut corresponds to a number of gates of the second cut and the updated second truth table is based on the increased volume; Hopkins [0080] teaches recursively extending Boolean matching along sub branches of matched subcircuits which represents increasing the volume of the second cut by including more logic elements. Hopkins [0082-0083] teaches when subcircuits are matched, the algorithm is recursively called on corresponding inputs, effectively increasing the volume by adding more gates to the cut. Hopkins [0072] teaches truth tables are computed for both subcircuits and comparison is performed as the matching extends deeper, which addresses comparing the first truth table with an updated second truth table as volume increases.
Hopkins differs from the claimed invention in that it does not explicitly disclose generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts, wherein the difference corresponds to the first primary cut including a buffer;
Possignolo teaches generate second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts; Possignolo [0063 - 0065] and Possignolo Table 1 teaches comparing each component of a second structural netlist against a corresponding component of a first structural netlist, identifying components where a difference exists between the two netlists, and removing those differing components to produce a refined set of matching components. This teaches generating second primary cuts from primary cuts by removing a first primary cut based on a difference between that cut and a second primary cut.
Possignolo differs from the claimed invention in that it does not explicitly disclose wherein the difference corresponds to the first primary cut including a buffer;
Binder teaches wherein the difference corresponds to the first primary cut including a buffer; Binder [0020] explicitly identifies buffers as a specific and recognizable gate type that creates a difference when comparing netlist path representations, teaching that the presence of a buffer in one path versus another is an identifiable distinction. This maps directly to the limitation requiring that the difference between the first primary cut and the second primary cut corresponds to the first primary cut including a buffer.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to introduce a more comprehensive method for determining and expanding circuit equivalence. Hopkins' recursive approach to Boolean matching allows for incrementally building larger equivalent circuits from smaller matched portions, which complements Satapathy's hierarchical comparison by providing a systematic way to determine the full extent of functional equivalence between different netlists. This results in more precise identification of the downward frontier and more efficient ECO generation.
The motivation to combine Satapathy, Hopkins, and Possignolo at the effective filing date of the invention is to reduce the number of candidate cuts requiring truth table-based Boolean matching by first applying Possignolo's structural component-removal technique to filter differing components from the primary cuts. This improves the scalability and efficiency of Satapathy's ECO generation process when applied to large netlists.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder at the effective filing date of the invention is to provide a specific technical basis for Possignolo's cut-filtering step by identifying cuts whose distinguishing difference corresponds to the presence of a buffer. Binder teaches that buffers are a recognizable gate type that creates an identifiable difference between netlist paths, enabling more precise filtering of primary cuts prior to Boolean matching.
In regards to claim 20 Satapathy does not show the non-transitory computer readable medium of claim 17: wherein determining the matching cuts comprises determining the first truth table for the first cut and the second truth table for the second cut.
Hopkins teaches wherein determining the matching cuts comprises determining the first truth table for the first cut and the second truth table for the second cut; Hopkins [0072] teaches truth tables are computed for both subcircuits and Boolean matching is done with manipulations on the truth table bitsets which directly addresses generating and comparing first and second truth tables.
The motivation to combine Satapathy and Hopkins at the effective filing date of the invention is to incorporate a mathematically rigorous approach to functional verification through truth table analysis. Hopkins' truth table computation and comparison methods provide a solid foundation for determining when two circuit portions are functionally equivalent, enhancing Satapathy's structural comparison approach with functional verification capabilities that improve the accuracy and reliability of the ECO generation process.
Claims 3, 13, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US20050091627A1 (Satapathy) in view of US20110004857A1 (Hopkins) in view of US20200134108A1 (Possignolo) and in view of US20110047521A1 (Binder) as applied in claims 1, 11, and 17 above, respectively, and further in view of US6668362B1 (McIlwain).
In regards to claim 3, (Satapathy modified by Hopkins and Binder) shows the method of claim 1:
Wherein the size parameter is decremented based on a determination that a match between the primary cuts and the secondary cuts does not exist; Satapathy [0039] teaches comparing primary and secondary cuts to identify differences and generate ECOS when mismatches are found but does not disclose using a size parameter to identify cuts or decrementing the size when no match is found.
Satapathy, Hopkins, Possignolo, and Binder differs from the claimed invention in that it does not explicitly disclose primary cuts and the secondary cuts are identified based on a size parameter corresponding to a number of nodes.
McIlwain teaches wherein the primary cuts and the secondary cuts are identified based on a size parameter corresponding to a number of nodes; McIlwain teaches partitioning designs based on a size parameter McIlwain (Column 6, lines 1-7) and decrementing it when mismatches are detected McIlwain (Column 9, lines 38-43), where cut points are selectively removed to reduce the size during verification.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder at the effective filing date of the invention is to provide a specific technical basis for Possignolo's cut-filtering step by identifying cuts whose distinguishing difference corresponds to the presence of a buffer. Binder teaches that buffers are a recognizable gate type that creates an identifiable difference between netlist paths, enabling more precise filtering of primary cuts prior to Boolean matching.
The motivation to combine Satapathy, Hopkins, Possignolo, Binder, and McIlwain at the effective filing date of the invention is to introduce adaptive partitioning techniques that can dynamically adjust based on the success of matching operations. McIlwain's approach to size-based partitioning and refinement complements Satapathy's hierarchical comparison, Hopkins' functional verification, Possignolo's component-removal filtering, and Binder's buffer-identification methods by providing a systematic way to manage the complexity of large designs and focus computational resources on appropriately sized circuit portions.
In regards to claim 13 (Satapathy modified by Hopkins and Binder) shows the system of claim of Claim 11:
wherein the primary cuts and the secondary cuts are identified based on a size parameter corresponding to a number of input nodes; Satapathy [0039] teaches comparing primary and secondary cuts to identify differences and generate ECOS when mismatches are found but does not disclose using a size parameter to identify cuts or decrementing the size when no match is found.
wherein the size parameter is decremented based on a determination that a match between the primary cuts and the secondary cuts does not exist; Satapathy [0039] teaches comparing primary and secondary cuts to identify differences and generate ECOS when mismatches are found but does not disclose using a size parameter to identify cuts or decrementing the size when no match is found.
Satapathy, Hopkins, Possignolo, and Binder differs from the claimed invention in that it does not explicitly disclose the use of a size parameter to organize or identify the primary and secondary cuts.
McIlwain, Column 6, lines 1-7, teaches that the design is partitioned into top-level partitions based on size, where any of a number of known partitioning methods can be used to manage the design’s complexity and reduce memory requirements and processor load. These partitions correspond to the primary and secondary cuts, and are identified based on their size parameter (number of nodes). McIlwain [Column 6, lines 16-18] teaches that the system compares the flat reference design to the flat implementation design to determine equivalence. This process involves identifying mismatches and adjusting the size parameter by decrementing it when there is no match between the primary and secondary cuts.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder at the effective filing date of the invention is to provide a specific technical basis for Possignolo's cut-filtering step by identifying cuts whose distinguishing difference corresponds to the presence of a buffer. Binder teaches that buffers are a recognizable gate type that creates an identifiable difference between netlist paths, enabling more precise filtering of primary cuts prior to Boolean matching.
The motivation to combine Satapathy, Hopkins, Possignolo, Binder, and McIlwain at the effective filing date of the invention is to introduce adaptive partitioning techniques that can dynamically adjust based on the success of matching operations. McIlwain's approach to size-based partitioning and refinement complements Satapathy's hierarchical comparison, Hopkins' functional verification, Possignolo's component-removal filtering, and Binder's buffer-identification methods by providing a systematic way to manage the complexity of large designs and focus computational resources on appropriately sized circuit portions.
In regards to claim 18 (Satapathy modified by Hopkins and Binder) shows the non-transitory computer readable medium of claim 17:
Wherein the size parameter is decremented based on a determination that a match between the primary cuts and the secondary cuts does not exist; Satapathy [0039] teaches comparing primary and secondary cuts to identify differences and generate ECOS when mismatches are found but does not disclose using a size parameter to identify cuts or decrementing the size when no match is found.
Satapathy, Hopkins, Possignolo, and Binder differs from the claimed invention in that it does not explicitly disclose the use of a size parameter to organize or identify the primary and secondary cuts.
McIlwain, Column 6, lines 1-7, teaches that the design is partitioned into top-level partitions based on size, where any of a number of known partitioning methods can be used to manage the design’s complexity and reduce memory requirements and processor load. These partitions correspond to the primary and secondary cuts, and are identified based on their size parameter (number of nodes). McIlwain [Column 6, lines 16-18] teaches that the system compares the flat reference design to the flat implementation design to determine equivalence. This process involves identifying mismatches and adjusting the size parameter by decrementing it when there is no match between the primary and secondary cuts.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder at the effective filing date of the invention is to provide a specific technical basis for Possignolo's cut-filtering step by identifying cuts whose distinguishing difference corresponds to the presence of a buffer. Binder teaches that buffers are a recognizable gate type that creates an identifiable difference between netlist paths, enabling more precise filtering of primary cuts prior to Boolean matching.
The motivation to combine Satapathy, Hopkins, Possignolo, Binder, and McIlwain at the effective filing date of the invention is to introduce adaptive partitioning techniques that can dynamically adjust based on the success of matching operations. McIlwain's approach to size-based partitioning and refinement complements Satapathy's hierarchical comparison, Hopkins' functional verification, Possignolo's component-removal filtering, and Binder's buffer-identification methods by providing a systematic way to manage the complexity of large designs and focus computational resources on appropriately sized circuit portions.
In regards to claim 19 (Satapathy modified by Hopkins and Binder) shows the non-transitory computer readable medium of claim 17:
wherein increasing the volume of the second cut includes identifying an input node of the ECO circuit network to include in the second cut, and determining that functionality of the second cut is unchanged by the input node; Satapathy [0013] and [0021] teaches how to select important parts (input nodes) to include in the design changes. This helps ensure that the system stays updated and that the most critical parts of the design are accounted for when comparing the original and modified designs. Satapathy talks about choosing these input nodes to ensure that design updates are accurate,
Satapathy, Hopkins, Possignolo, and Binder differs from the claimed invention in that it does not explicitly disclose increasing the volume of cuts.
McIlwain [Column 6, lines 1-7] teaches that the design is partitioned into top-level partitions, and by doing so, it allows each partition to be processed separately. This reduces memory requirements and processor load, which is particularly useful when dealing with larger designs. This approach can be adapted to managing input nodes and adjusting the volume of the cuts, as it emphasizes the importance of efficient partitioning.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder at the effective filing date of the invention is to provide a specific technical basis for Possignolo's cut-filtering step by identifying cuts whose distinguishing difference corresponds to the presence of a buffer. Binder teaches that buffers are a recognizable gate type that creates an identifiable difference between netlist paths, enabling more precise filtering of primary cuts prior to Boolean matching.
The motivation to combine Satapathy, Hopkins, Possignolo, Binder, and McIlwain at the effective filing date of the invention is to introduce adaptive partitioning techniques that can dynamically adjust based on the success of matching operations. McIlwain's approach to size-based partitioning and refinement complements Satapathy's hierarchical comparison, Hopkins' functional verification, Possignolo's component-removal filtering, and Binder's buffer-identification methods by providing a systematic way to manage the complexity of large designs and focus computational resources on appropriately sized circuit portions.
Response to Argument
Applicant's arguments filed on December 5, 2024 have been fully considered but they are not persuasive.
The RCE amendment adds the limitation "generating second primary cuts from the primary cuts by removing a first primary cut of the primary cuts based on a difference between the first primary cut and a second primary cut of the primary cuts, wherein the difference corresponds to the first primary cut including a buffer." However, this limitation does not distinguish over the prior art.
Applicant appears to argue that the newly added limitation introduces a distinct preprocessing step in which two primary cuts are compared, a difference is identified, and a cut is removed where that difference corresponds to the presence of a buffer — and that none of the cited references teach this combination of steps.
However, the examiner respectfully disagrees. The newly added limitation is taught by the combination of Satapathy, Hopkins, Possignolo, and Binder. Specifically, Possignolo [0063 - 0065] and Possignolo Table 1 teaches comparing each component of a second structural netlist against a corresponding component of a first structural netlist, identifying components where a difference exists between the two netlists, and removing those differing components to produce a refined set of matching components. This teaching directly corresponds to removing a first primary cut based on a difference between that cut and a second primary cut, as claimed. Further, Binder [0020] explicitly identifies buffers as a specific and recognizable gate type that creates a difference when comparing netlist path representations, teaching that the presence of a buffer in one path versus another is an identifiable distinction. This teaching directly corresponds to the claimed requirement that the difference between the first primary cut and the second primary cut corresponds to the first primary cut including a buffer.
The motivation to combine Satapathy, Hopkins, Possignolo, and Binder is to improve ECO generation efficiency by first filtering candidate primary cuts through Possignolo's structural component-removal technique before subjecting them to Hopkins' computationally intensive truth table-based Boolean matching, with Binder providing the specific technical basis for identifying which cuts to remove based on the presence of a buffer. This combination enables more accurate identification of matching cuts while reducing processing overhead on large netlists.
Therefore, the amended claims remain unpatentable over the cited prior art combination, and the rejections are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851