DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I was elected.
Amendment filed on July 10, 2026 is acknowledged. Claims 1 and 18 have been amended. Claim 4 has been cancelled. Non-elected Invention, Group II, claims 9-17 have been withdrawn from consideration. Claims 1, 3, 5-7 and 9-21 are pending.
Action on merits of elected Invention, Group I, claims 1, 3, 5-7 and 18-21 follows.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, 5-7 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over XIE et al. (US. Pub. No. 2017/0141211) in view of JUN et al. (US. Pub. No. 2018/0261596) both of record.
With respect to claim 1, XIE teaches a reduced diffusion break (RDB) structure substantially as claimed including:
a first sidewall spacer positioned between a first gate terminal (150B, left) and a first source/drain terminal (116) of a first active device (110A), wherein the first sidewall spacer includes a first L-shaped spacer (150A/110X) and a first outer spacer (114), the first L-shaped spacer (150A/110X) and the first outer spacer (114) being in direct contact, the first L-shaped spacer having a base portion (110x) horizontally extended from the first gate terminal (150B) to the first source/drain terminal (116) and positioned directly below the first outer spacer (114), and a vertical portion (150A, vertical) vertically extended, parallel to the first outer spacer (114), to a top portion of a first inter dielectric layer (IDL, 118);
a second sidewall spacer positioned between a second gate terminal (150B, right) and a second source/drain terminal (116) of a second active device (110C), wherein the second sidewall spacer includes a second L-shaped spacer (150A/110X) and a second outer spacer (114), the second L-shaped spacer (150A/110X) and the first outer spacer (114) being in direct contact, the second L-shaped spacer having a base portion (110x) horizontally extended from the second gate terminal (150B, right) to the second source/drain terminal (116) and positioned directly below the first outer spacer (114) and a vertical portion (150A, vertical) vertically extended parallel to the second outer spacer (114), to a top portion of a second inter dielectric layer (IDL, 118); and
a RDB dielectric structure (162), located between the first gate terminal (150B) and the second gate terminal (150B), having a first reduced width, vertically extended from the top portion of the first IDL into a substrate (102), wherein the RDB dielectric structure (162) is separated from the first source/drain terminal (116) by a first RDB spacer (), the first RDB spacer having a first upper spacer (114), wherein the first RDB spacer has a second reduced width less than a width of the first sidewall spacer (150A+114), and the RDB dielectric structure is separated from the second source/drain terminal (116) by a second RDB spacer, the second RDB spacer having a second upper spacer (114), wherein the second RDB spacer has a third reduced width less than a width of the second sidewall spacer (150A+114), wherein a combined width of the RDB dielectric structure (162), the first RDB spacer and the second RDB spacer and a combined width of the first gate terminal,
wherein the first RDB spacer further includes a first base spacer (110) positioned directly beneath the first upper spacer (114) and extending along the substrate (102) from the first source/drain terminal (116) to the RDB dielectric structure (162), and the second RDB spacer further includes a second base spacer (110) positioned directly beneath the second upper spacer (114) and extending along the substrate (102) from the second source/drain terminal (116) to the RDB dielectric structure (162), wherein each of the first base spacer (110) and the second base spacer (110) is positioned at a same vertical level as the base portion (110) of the corresponding L-shaped spacer (150A-110) and is laterally spaced from the base portion (110) of the L-shaped spacer (150A-110), wherein the first base spacer (110) and the first L-shaped spacer (150A-110) comprise a first spacer liner material, and wherein the first upper spacer (114) and the first outer spacer (114) comprise a second spacer liner material different from the first spacer liner material. (See FIG. 2S).
Thus XIE is shown to teach all the features of the claim with the exception of explicitly disclosing the first reduced width being less than the width of the first gate terminal and the second gate terminal; and a combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer being less than a combined width of the first gate terminal.
However, JUN teaches a RDB structure including:
a RDB dielectric structure (FS2), located between the first gate terminal (GL, left) and the second gate terminal (GL, right), having a first reduced width that is less than a width (FS) of each of the first gate terminal and the second gate terminal, vertically extended from the top portion of the first IDL into a substrate (110), wherein the RDB dielectric structure (FS2) is separated from the first source/drain terminal (172) by a first RDB spacer (126, left), the first RDB spacer (126, left) having a first upper spacer, wherein the first RDB spacer (126, left) has a second reduced width less than a width of first sidewall spacer (118+162), and the RDB dielectric structure (FS2) is separated from a second source/drain terminal (172) by a second RDB spacer (126, right), the second RDB spacer (126, right) having a second upper spacer, wherein the second RDB spacer (126, right) has a third reduced width less than a width of a second sidewall spacer (118+162), wherein a combined width of the RDB dielectric structure (FS2), the first RDB spacer (126, left) and the second RDB spacer (126, right) is less than a combined width of the first gate terminal (FS). (See FIG. 2A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the RDB of XIE having the first reduced width being less than the width of the first gate terminal and the combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer being less than a combined width of the first gate terminal as taught by JUN for the same intended purpose of isolating adjacent devices.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to optimize the width of the RDB through routine experimentation to provide isolation between the devices.
With respect to claim 3, in view of JUN, the RDB dielectric structure (128) vertically extends from the top portion of the second IDL (180) into the substrate (110).
With respect to claim 5, a material of the first base spacer (110X) and a material of the L-shaped spacer (110X) of XIE are a same material.
With respect to claim 6, the base portion (110X) of the first L-shaped spacer of XIE is positioned directly beneath the first outer spacer (114) and above the substrate.
With respect to claim 7, a material of the first outer spacer (114) and a material of the first upper spacer (114) of XIE are a same material.
With respect to claim 21, the RDB dielectric structure (162) of XIE or JUN is located between the first source/drain terminal and the second source/drain terminal.
With respect to claim 18, XIE ‘211 teaches a semiconductor device substantially as claimed including:
a reduced diffusion break (RDB) structure having a RDB dielectric structure (162) vertically extended into a substrate (102) from a top portion of an inter dielectric layer (IDL) (118), wherein the RDB dielectric structure (162) is configured between a first RDB spacer and a second RDB spacer;
a first sidewall spacer positioned between a first gate terminal (150B, left) and a first source/drain terminal (116) of a first active device (110A), wherein the first sidewall spacer includes a first L-shaped spacer (150A-110X) and a first outer spacer (114), the first L-shaped spacer and the first outer spacer being in direct contact, the first L-shaped spacer having a base portion (110X) horizontally extended from the first gate terminal (150B, left) to the first source/drain terminal (116) and positioned directly beneath the first outer spacer, and a vertical portion (150A, vertical) vertically extended parallel to the first outer spacer (114) to the top portion of the IDL (118); and
a second sidewall spacer positioned between a second gate terminal (150B, right) and a second source/drain terminal (116) of a second active device (110C), wherein the second sidewall spacer includes a second L-shaped spacer (150A-110X) and a second outer spacer, the second L-shaped spacer and the second outer spacer being in direct contact, the second L-shaped spacer having a base portion (110X) horizontally extended from the second gate terminal (150B, right) to the second source/drain terminal (116) and positioned directly beneath the second outer spacer, and a vertical portion (150A, vertical) vertically extended parallel to the second outer spacer (114) to the top portion of the IDL (118),
wherein the RDB dielectric structure (162), the first RDB spacer and the second RDB spacer are located between the first gate terminal (150B, left) and the second gate terminal (150B, right), the first RDB spacer having a first upper spacer (114), the RDB dielectric structure has a first reduced width, and a combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer has a combined width, and a combined width of the first gate terminal,
wherein the first RDB spacer (left) further includes a first base spacer (110X) positioned directly above the substrate (102) beneath the first RDB spacer (114), and the second RDB spacer (right) further includes a second base spacer (110X) positioned directly above the substrate (102) beneath the second RDB spacer (114), wherein the first base spacer (110X) and the second base spacer (110X) each extend laterally from a corresponding source/drain terminal (116) toward the RDB dielectric structure (162), wherein each base spacer (110X) is positioned at a same vertical level as the base portion (110X) of the corresponding L-shaped spacer and is laterally separated from the base portion of the L-shaped spacer, wherein the first base spacer (110X) and the first L-shaped spacer comprise a first spacer liner material (SiO), and wherein the first upper spacer (114) and the first outer spacer (114) comprise a second spacer liner material (SiN) different from the first spacer liner material (SiO). (See FIG. 2S).
Thus, XIE is shown to teach all the features of the claim with the exception of explicitly disclosing the first reduced width of the RDB dielectric structure being less than a width of each of the first gate terminal and the second gate terminal, and a combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer being less than a combined width of the first gate terminal.
However, JUN teaches a semiconductor device including:
a reduced diffusion break (RDB) structure (FS2) having a RDB dielectric structure (FR2) vertically extended into a substrate (FA) from a top portion of an inter dielectric layer (180), wherein the RDB dielectric structure (FR2) is configured between a first RDB spacer (126, left) and a second RDB spacer (126, right),
wherein the RDB dielectric structure (FR2), the first RDB spacer (126, left) and the second RDB spacer (126, right) are located between first gate terminal (GL, left) and the second gate terminal (GL, right), the first RDB spacer (126, left) having a first upper spacer (126), the RDB dielectric structure (FR2) has a first reduced width that is less than a width of each of the first gate terminal (GL, left) and the second gate terminal (GL, right), and a combined width of the RDB dielectric structure (FR2), the first RDB spacer (126, left) and the second RDB spacer (126, right) is less than a combined width of the first gate terminal (GL, left). (See FIG. 2A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form RDB dielectric structure having the first reduced width being less than the width of each of the first gate terminal and the second gate terminal, and the combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer being less than a combined width of the first gate terminal as taught by JUN for the same intended purpose of isolating adjacent devices.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to optimize the width of the RDB through routine experimentation to provide isolation between the devices.
With respect to claim 19, in view of JUN, the first RDB spacer (126, left) and the second RDB spacer (126, right) each have a second reduced width less than a width of the first sidewall spacer (162).
With respect to claim 20, the RDB structure (162) of XIE has a total reduced width that is less than a total width of the first active device (110A).
Response to Arguments
Applicant's arguments filed July 10, 2026 have been fully considered but they are not persuasive.
Applicant argues:
Claim 1 is amended herein to recite, in part: "...wherein the first RDB spacer further includes a first base spacer positioned directly beneath the first upper spacer and extending along the substrate from the first source/drain terminal to the RDB dielectric structure, and the second RDB spacer further includes a second base spacer positioned directly beneath the second upper spacer and extending along the substrate from the second source/drain terminal to the RDB dielectric structure, wherein each of the first base spacer and the second base spacer is positioned at a same vertical level as the base portion of the corresponding L-shaped spacer and is laterally spaced from the base portion of the L-shaped spacer, wherein the first base spacer and the first L- shaped spacer comprise a first spacer liner material, and wherein the first upper spacer and the first outer spacer comprise a second spacer liner material different from the first spacer liner material." The Office Action did not address the features added to claim 1 by the amendment herein.
However, XIE, FIG. 2S, explicitly teaches: “… wherein the first RDB spacer further
includes a first base spacer (110X) positioned directly beneath the first upper spacer (114) and extending along the substrate (102) from the first source/drain terminal (116, left) to the RDB dielectric structure (162), and the second RDB spacer further includes a second base spacer (110X) positioned directly beneath the second upper spacer (114) and extending along the substrate (102) from the second source/drain terminal (116, right) to the RDB dielectric structure (162), wherein each (110X) of the first base spacer and the second base spacer is positioned at a same vertical level as the base portion (110X) of the corresponding L-shaped spacer (150A-110X) and is laterally spaced from the base portion (110X) of the L-shaped spacer, wherein the first base spacer (110X) and the first L- shaped spacer (150A-110X) comprise a first spacer liner material (SiO), and wherein the first upper spacer (114) and the first outer spacer (114) comprise a second spacer liner material (SiN) different from the first spacer liner material (SiO)". (See FIG. 2S).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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