DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 05, 2026 has been entered.
Status of the Claims
Group I was elected.
Amendment filed on May 05, 2026 is acknowledged. Claims 1 and 18-19 have been amended. Non-elected Invention, Group II, claims 9-17 have been withdrawn from consideration. Claims 1, 3-7 and 9-21 are pending.
Action on merits of elected Invention, Group I, claims 1, 3-7 and 18-21 follows.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-8 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over XIE et al. (US. Pub. No. 2017/0141211) in view of JUN et al. (US. Pub. No. 2018/0261596) both of record.
With respect to claim 1, XIE teaches a reduced diffusion break (RDB) structure substantially as claimed including:
a first sidewall spacer positioned between a first gate terminal (150B, left) and a first source/drain terminal (116) of a first active device (110A), wherein the first sidewall spacer includes a first L-shaped spacer (150A/110X) and a first outer spacer (114), the first L-shaped spacer (150A/110X) and the first outer spacer (114) being in direct contact, the first L-shaped spacer having a base portion (110x) horizontally extended from the first gate terminal (150B, left) to the first source/drain terminal (116) and positioned directly below the first outer spacer (114), and a vertical portion (150A, vertical) vertically extended, parallel to the first outer spacer (114), to a top portion of a first inter dielectric layer (IDL, 118);
a second sidewall spacer positioned between a second gate terminal (150B, right) and a second source/drain terminal (116) of a second active device (110C), wherein the second sidewall spacer includes a second L-shaped spacer (150A/110X) and a second outer spacer (114), the second L-shaped spacer (150A.110X) and the first outer spacer (114) being in direct contact, the second L-shaped spacer having a base portion (110x) horizontally extended from the second gate terminal (150B, right) to the second source/drain terminal (116) and positioned directly below the first outer spacer (114) and a vertical portion (150A, vertical) vertically extended parallel to the second outer spacer (114), to a top portion of a second inter dielectric layer (IDL, 118); and
a RDB dielectric structure (162), located between the first gate terminal (150B, left) and the second gate terminal (150B, right), having a first reduced width, vertically extended from the top portion of the first IDL (118) into a substrate (102), wherein the RDB dielectric structure (162) is separated from the first source/drain terminal (116) by a first RDB spacer (114, left), the first RDB spacer (114, left) having a first upper spacer, wherein the first RDB spacer (114) has a second reduced width less than a width of the first sidewall spacer (150A/114), and the RDB dielectric structure (162) is separated from the second source/drain terminal (116) by a second RDB spacer (114, right), the second RDB spacer (114, right) having a second upper spacer, wherein the second RDB spacer (114, right) has a third reduced width less than a width of the second sidewall spacer (150A/114), wherein the RDB dielectric structure (162), the first RDB spacer (114, left) and the second RDB spacer (114, right) has a combined width, wherein the RDB dielectric structure (162) extends into the substrate (102) to a depth greater than a bottom surface of each of the first source/drain terminal (116) and the second source/drain terminal (116). (See FIG. 2S).
Thus XIE is shown to teach all the features of the claim with the exception of explicitly disclosing the RDB dielectric structure having the first reduced width being less than the width of the first gate terminal and the second gate terminal; and a combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer is less than a combined width of the first gate terminal.
However, JUN teaches a RDB structure including:
a RDB dielectric structure (128), located between first gate terminal (GL, left) and second gate terminal (GL, right), having a first reduced width less than a width of the first gate terminal (GL, left) and second gate terminal (GL, right), vertically extended from the top portion of the first IDL (180) into a substrate (110), wherein the RDB dielectric structure (128) is separated from first source/drain terminal (CA1) by a first RDB spacer (126), left), the first RDB spacer (126, left) having a first upper spacer, wherein the first RDB spacer (126, left) has a second reduced width less than a width of the first sidewall spacer (162/118), and the RDB dielectric structure (128) is separated from the second source/drain terminal (CA1, right) by a second RDB spacer (126, right), the second RDB spacer (126, right) having a second upper spacer, wherein the second RDB spacer (126, right) has a third reduced width less than a width of the second sidewall spacer (162/118), wherein a combined width (FS2) of the RDB dielectric structure (128), the first RDB spacer (126, left) and the second RDB spacer (126, right) is less than a combined width of the first gate terminal (GL, left), wherein the RDB dielectric structure (128) extends into the substrate (110) to a depth greater than a bottom surface (R1) of each of the first source/drain terminal (172) and the second source/drain terminal (172). (See FIG. 2A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the RDB of XIE having the first reduced width being less than the width of the first gate terminal and the combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer being less than a combined width of the first gate terminal as taught by JUN for the same intended purpose of isolating adjacent devices.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to optimize the width of the RDB through routine experimentation to provide isolation between the devices.
With respect to claim 3, in view of JUN, the RDB dielectric structure (128) vertically extends from the top portion of the second IDL (180) into the substrate (110).
With respect to claim 4, the first RDB spacer of XIE further includes a first base spacer (110X) positioned directly beneath the first upper spacer (114) of the first RDB spacer and extends from the first source/drain terminal (116) to the RDB dielectric structure (162) directly above the substrate.
With respect to claim 5, a material of the first base spacer (110X) and a material of the L-shaped spacer (110X) of XIE are a same material.
With respect to claim 6, the base portion (110X) of the first L-shaped spacer of XIE is positioned directly beneath the first outer spacer (114) and above the substrate.
With respect to claim 7, a material of the first outer spacer (114) and a material of the first upper spacer (114) of XIE are a same material.
With respect to claim 21, the RDB dielectric structure (162) of XIE or JUN is located between the first source/drain terminal (116, left) and the second source/drain terminal (116, right).
With respect to claim 18, XIE ‘211 teaches a semiconductor device substantially as claimed including:
a reduced diffusion break (RDB) structure having a RDB dielectric structure (162) vertically extended into a substrate (102) from a top portion of an inter dielectric layer (IDL) (118), wherein the RDB dielectric structure (162) is configured between a first RDB spacer (114, left) and a second RDB spacer (114, right);
a first sidewall spacer positioned between a first gate terminal (150B, left) and a first source/drain terminal (116) of a first active device (110A), wherein the first sidewall spacer includes a first L-shaped spacer (150A/110X) and a first outer spacer (114), the first L-shaped spacer and the first outer spacer (114) being in direct contact, the first L-shaped spacer having a base portion (110X) horizontally extended from the first gate terminal (150B, left) to the first source/drain terminal (116) and positioned directly beneath the first outer spacer (114), and a vertical portion (150A, vertical) vertically extended parallel to the first outer spacer (114) to the top portion of the IDL (118); and
a second sidewall spacer positioned between a second gate terminal (150B, right) and a second source/drain terminal (116) of a second active device (110C), wherein the second sidewall spacer includes a second L-shaped spacer (150A/110X) and a second outer spacer (114), the second L-shaped spacer and the second outer spacer being in direct contact, the second L-shaped spacer having a base portion (110X) horizontally extended from the second gate terminal (150B, right) to the second source/drain terminal (116) and positioned directly beneath the second outer spacer (114), and a vertical portion (150A, vertical) vertically extended parallel to the second outer spacer (114) to the top portion of the IDL (118),
wherein the RDB dielectric structure (162), the first RDB spacer (114, left) and the second RDB spacer (114, right) are located between the first gate terminal (150B, left) and the second gate terminal (150B, right), the RDB dielectric structure has a first reduced width, wherein the RDB dielectric structure extends into the substrate to a depth greater than a bottom surface of each of the first source/drain terminal and the second source/drain terminal. (See FIG. 2S).
Thus, XIE is shown to teach all the features of the claim with the exception of explicitly disclosing the first reduced width of the RDB dielectric structure being less than a width of each of the first gate terminal and the second gate terminal, and a combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer being less than a combined width of the first gate terminal.
However, JUN teaches a semiconductor device including:
a reduced diffusion break (RDB) structure (FR2) having a RDB dielectric structure (FR2) vertically extended into a substrate (FA) from a top portion of an inter dielectric layer (180), wherein the RDB dielectric structure (FR2) is configured between a first RDB spacer (126, left) and a second RDB spacer (126, right),
wherein the RDB dielectric structure (FR2), the first RDB spacer (126, left) and the second RDB spacer (126, right) are located between first gate terminal (GL, left) and the second gate terminal (GL, right), the RDB dielectric structure (FR2) has a first reduced width that is less than a width of each of the first gate terminal (GL, left) and the second gate terminal (GL, right), and a combined width of the RDB dielectric structure (FR2), the first RDB spacer (126, left) and the second RDB spacer (126, right) is less than a combined width of the first gate terminal (GL, left), wherein the RDB dielectric structure (128) extends into the substrate (110) to a depth greater than a bottom surface (R1) of each of the first source/drain terminal (172) and the second source/drain terminal (172). (See FIG. 2A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form RDB dielectric structure having the first reduced width being less than the width of each of the first gate terminal and the second gate terminal, and the combined width of the RDB dielectric structure, the first RDB spacer and the second RDB spacer being less than a combined width of the first gate terminal as taught by JUN for the same intended purpose of isolating adjacent devices.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to optimize the width of the RDB through routine experimentation to provide isolation between the devices.
With respect to claim 19, in view of JUN, the first RDB spacer (126, left) and the second RDB spacer (126, right) each have a second reduced width less than a width of the first sidewall spacer (162).
With respect to claim 20, the RDB structure (162) of XIE has a total reduced width that is less than a total width of the first active device (110A).
Response to Arguments
Applicant did not submit an argument pointing out disagreements with the examiner’s contentions.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893
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