DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 23-35 are rejected under 35 U.S.C. 103 as being obvious over US 2020/0176597 A1 to Vellianitis et al. (hereinafter “Vellianitis” – previously cited reference).
Regarding claim 1, Vellianitis discloses an integrated circuit device, comprising:
a first source or drain semiconductor of a first conductivity type coupled to a plurality of first channel layers of a first gate-all-around transistor and a first gate dielectric adjacent each of the plurality of first channel layers (IC device having boron-doped first source/drain 60 coupled to semiconductor layers 20 of n-type GAA FET Fn, where first portion of gate dielectric 82 is adjacent layers 20; Figs. 2, 9A, 13A, 15A and 15C; paragraphs [0041], [0043], [0063], [0077]-[0080], [0099]; claim 13);
a second source or drain semiconductor of a second conductivity type coupled to a plurality of second channel layers of a second gate-all-around transistor and a second gate dielectric adjacent each of the plurality of second channel layers (phosphorous and/or arsenic-doped second source/drain 65 coupled to semiconductor layers 25 of p-type GAA FET Fp, where second portion of gate dielectric 82 is adjacent layers 25; Figs. 2, 9A, 13A, 15A and 15C; paragraphs [0041], [0043], [0063], [0072], [0075], [0077]-[0080], [0099]; claim 13), the second source or drain laterally adjacent the first source or drain semiconductor (source/drain 65 disposed laterally adjacent source/drain 60 as shown in Fig. 15A); and
a portion of a dielectric layer extending between the first source or drain semiconductor and the second source or drain semiconductor (portion of ILD 50, highlighted in red box in annotated Fig. 7 below, disposed between source/drains 60 and source/drains 65 as shown in Figs. 7 and 15A; paragraphs [0057]-[0058]), wherein the portion of the dielectric layer is over an isolation material between the first and second gate-all-around transistors (ILD 50 disposed over STI layer 30 and between n-type GAA FET Fn and p-type GAA FET Fp as shown in 15A; paragraphs [0048], [0050]), an entirety of the portion of the dielectric layer is laterally between the first source or drain semiconductor and the second source or drain semiconductor such that the portion of the dielectric layer does not extend above or below top and bottom surfaces of the first source or drain semiconductor and the second source or drain semiconductor (portion of ILD 50 disposed between left, right, top and bottom sides of far right source/drain 60 and far left source/drain 65 as shown in Figs. 7 and 15A; paragraphs [0057]-[0058]), and the portion of the dielectric layer has a first thickness at a first position adjacent the first source or drain semiconductor and a second thickness, less than the first thickness, at a second position between the first position and the second source or drain semiconductor (portion of ILD 50 having a first vertical thickness potion at a first position adjacent a lower right side of left source/drain 60 beyond spacer and a second vertical thickness portion less than the first at a second position adjacent an upper right side of left source/drain 60 above spacer and between first position and source/drains 65 at least as shown in Figs. 7 and 15A).
Vellianitis fails to explicitly disclose the isolation material has a top surface between top and bottom surfaces of the first source or drain semiconductor and the second source or drain semiconductor, respectively.
However, Vellianitis already discloses the STI layer 30 comprising a top surface that is horizontally aligned with the bottom surface of the source/drain 60 and source/drain 65; Fig. 15A. Further, the bottom fin layer 11 may be made from Si and Ge which are the same materials utilized in source/drain 60 and source/drain 65 (see paragraphs [0043], [0063] and [0071]) and therefore could be considered to be an extension of source/drain 60 and source/drain 65 which would mean the top surface of the STI layer 30 is between bottom and top surfaces of source/drain 60 and source/drain 65.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Vellianitis to have the STI layer 30 extend to any degree above the bottom surfaces of the source/drain 60 and source/drain 65 in order to potentially provide better isolation and reduced leakage paths, improved structural support and reduced defects, and control of strain and electrostatics.
Regarding claim 2, Vellianitis discloses the integrated circuit device of claim 1, wherein the second thickness is not more than half the first thickness (top of spacer adjacent left source/drain 60 is located above thickness midpoint of portion of ILD 50 and lower right side of left source/drain 60 located at terminus of ILD 50, therefore second thickness is not more than half the first thickness; Fig. 7).
Regarding claim 3, Vellianitis discloses the integrated circuit device of claim 1, wherein the isolation material comprises silicon and oxygen, and the portion of the dielectric layer comprises silicon and at least one of oxygen, carbon, or nitrogen (STI layer 30 may include silicon oxide and ILD 50 may comprise oxygen; paragraphs [0048], [0057], [0078]).
Regarding claim 4, Vellianitis discloses the integrated circuit device of claim 1, wherein the portion of the dielectric layer comprises a third thickness, greater than the second thickness, at a third position between the second position and the second source or drain (portion of ILD 50 comprises third vertical thickness greater than second vertical thickness at lower left side of left source/drain 60 beyond spacer between upper right side of left source/drain 60 and the source/drains 65; Figs. 7 and 15A).
Regarding claim 5, Vellianitis discloses the integrated circuit device of claim 4, wherein the first position and the third position are not more than 10 nm apart in a direction extending between the first source or drain semiconductor and the second source or drain semiconductor (each source/drain may have a horizontal width of about 5 nanometers, therefore lower right side position of left source/drain 60 and lower left side position of left source/drain 60 are not more than 10 nanometers apart in the horizontal direction; Fig. 7; paragraph [0045]).
For purposes of claims 6-7, a second interpretation of Vellianitis discloses all the limitation described in claim 1 above, except the last portion of the claim which will have the following interpretation: the portion of the dielectric layer has a first thickness at a first position adjacent the first source or drain semiconductor and a second thickness, less than the first thickness, at a second position between the first position and the second source or drain semiconductor (portion of ILD 50 having a first vertical thickness potion at a first position adjacent a lower left side of left source/drain 60 beyond spacer and a second vertical thickness portion less than the first at a second position adjacent an upper right side of right source/drain 65 above spacer and between first position and source/drains 65 at least as shown in Figs. 7 and 15A).
Regarding claim 6, the second interpretation of Vellianitis discloses the integrated circuit device of claim 1, wherein the portion of the dielectric layer comprises a third thickness, less than the first thickness, at a third position between the first position and the first source or drain semiconductor (portion of ILD 50 comprises third vertical thickness less than the first vertical thickness at upper left side of left source/drain 60 above spacer between lower left side of left source/drain 60 beyond spacer and the right source/drain 60; Figs. 7 and 15A).
Regarding claim 7, the second interpretation of Vellianitis discloses the integrated circuit device of claim 6, wherein the first position and the third position are not more than 10 nm apart in a direction extending between the first source or drain semiconductor and the second source or drain semiconductor (each source/drain may have a horizontal width of about 5 nanometers, therefore upper left side of left source/drain 60 above spacer and lower left side of left source/drain 60 are not more than 10 nanometers apart in the horizontal direction; Fig. 7; paragraph [0045]).
Regarding claim 8, Vellianitis discloses the integrated circuit device of claim 1, wherein the portion of the dielectric layer comprises a same material as a gate spacer of the first and second gate-all-around transistors (sidewall spacers 48 and ILD 50 may comprise SiN; paragraphs [0055], [0057]).
Regarding claim 9, Vellianitis discloses the integrated circuit device of claim 1, wherein the portion of the dielectric layer is in contact with the first source or drain semiconductor, the second source or drain semiconductor, and the isolation material (ILD 50 contacts source/drain 60, source/drain 65, and STI 30; Fig. 15C; paragraph [0057]).
Regarding claim 23, Vellianitis discloses the integrated circuit device of claim 1, wherein the first and second gate-all- around transistors are in a monolithic die, the integrated circuit device further comprising a power supply coupled to the monolithic die (p-type GAA FET and n-type GAA FET fabricated out of single structure with a power supply coupled thereto; Fig. 1; paragraphs [0002], [0029], [0038]).
Regarding claim 24, Vellianitis discloses an integrated circuit device, comprising:
a first source or drain semiconductor of a first conductivity type coupled to a plurality of first channel layers of a first gate-all-around transistor and a first gate dielectric adjacent each of the plurality of first channel layers (IC device having boron-doped first source/drain 60 coupled to semiconductor layers 20 of n-type GAA FET Fn, where first portion of gate dielectric 82 is adjacent layers 20; Figs. 2, 9A, 13A, 15A and 15C; paragraphs [0041], [0043], [0063], [0077]-[0080], [0099]; claim 13);
a second source or drain semiconductor of a second conductivity type coupled to a plurality of second channel layers of a second gate-all-around transistor and a second gate dielectric adjacent each of the plurality of second channel layers (phosphorous and/or arsenic-doped second source/drain 65 coupled to semiconductor layers 25 of p-type GAA FET Fp, where second portion of gate dielectric 82 is adjacent layers 25; Figs. 2, 9A, 13A, 15A and 15C; paragraphs [0041], [0043], [0063], [0072], [0075], [0077]-[0080], [0099]; claim 13), the second source or drain laterally adjacent the first source or drain semiconductor (source/drain 65 disposed laterally adjacent source/drain 60 as shown in Fig. 15A); and
a portion of a dielectric layer extending between the first source or drain semiconductor and the second source or drain semiconductor (portion of ILD 50 disposed between source/drain 60 and source/drain 65 as shown in Fig. 15A; paragraphs [0057]-[0058]), wherein the portion of the dielectric layer is over an isolation material between the first and second gate-all-around transistors (ILD 50 disposed over STI layer 30 and between n-type GAA FET Fn and p-type GAA FET Fp as shown in 15A; paragraphs [0048], [0050]), an entirety of the portion of the dielectric layer is laterally between the first source or drain semiconductor and the second source or drain semiconductor such that the portion of the dielectric layer does not extend above or below top and bottom surfaces of the first source or drain semiconductor and the second source or drain semiconductor (portion of ILD 50 disposed between left, right, top and bottom sides of far right source/drain 60 and far left source/drain 65 as shown in Figs. 7 and 15A; paragraphs [0057]-[0058]), and the portion of the dielectric layer has a first thickness at a first position adjacent the first source or drain semiconductor, a second thickness, less than the first thickness, at a second position between the first position and the second source or drain semiconductor (portion of ILD 50 having a first vertical thickness at a first position adjacent a lower right side of left source/drain 60 and a second vertical thickness portion less than the first at a second position adjacent an upper right side of left source/drain 60 above spacer and between first position and source/drains 65 at least as shown in Figs. 7 and 15A), and a third thickness, substantially the same as the first thickness, at a third position between the second position and the second source or drain semiconductor (portion of ILD 50 comprises third vertical thickness equal to the first thickness adjacent a lower left side of left source/drain 60 between upper right side of left source/drain 60 and source/drains 65; Figs. 7 and 15A).
Vellianitis fails to explicitly disclose the isolation material has a top surface between top and bottom surfaces of the first source or drain semiconductor and the second source or drain semiconductor, respectively.
However, Vellianitis already discloses the STI layer 30 comprising a top surface that is horizontally aligned with the bottom surface of the source/drain 60 and source/drain 65; Fig. 15A. Further, the bottom fin layer 11 may be made from Si and Ge which are the same materials utilized in source/drain 60 and source/drain 65 (see paragraphs [0043], [0063] and [0071]) and therefore could be considered to be an extension of source/drain 60 and source/drain 65 which would mean the top surface of the STI layer 30 is between bottom and top surfaces of source/drain 60 and source/drain 65.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Vellianitis to have the STI layer 30 extend to any degree above the bottom surfaces of the source/drain 60 and source/drain 65 in order to potentially provide better isolation and reduced leakage paths, improved structural support and reduced defects, and control of strain and electrostatics.
Regarding claim 25, Vellianitis discloses the integrated circuit device of claim 24, wherein the second thickness is not more than half the first thickness (top of spacer adjacent left source/drain 60 is located above thickness midpoint of portion of ILD 50 and lower right side of left source/drain 60 located at terminus of ILD 50, therefore second thickness is not more than half the first thickness; Fig. 7).
Regarding claim 26, Vellianitis discloses the integrated circuit device of claim 24, wherein the isolation material comprises silicon and oxygen, and the portion of the dielectric layer comprises silicon and at least one of oxygen, carbon, or nitrogen (STI layer 30 may include silicon oxide and ILD 50 may comprise oxygen; paragraphs [0048], [0057], [0078]).
Regarding claim 27, Vellianitis discloses the integrated circuit device of claim 24, wherein the first position and the third position are not more than 10 nm apart in a direction extending between the first source or drain semiconductor and the second source or drain semiconductor (each source/drain may have a horizontal width of about 5 nanometers, therefore bottom left side of left source/drain 60 and bottom right side of left source/drain 60 are not more than 10 nanometers apart in the horizontal direction; Fig. 7; paragraph [0045]).
Regarding claim 28, Vellianitis discloses the integrated circuit device of claim 24, wherein the portion of the dielectric layer comprises a same material as a gate spacer of the first and second gate-all-around transistors (sidewall spacers 48 and ILD 50 may comprise SiN; paragraphs [0055], [0057]).
Regarding claim 29, Vellianitis discloses the integrated circuit device of claim 24, wherein the first and second gate-all-around transistors are in a monolithic die, the integrated circuit device further comprising a power supply coupled to the monolithic die (p-type GAA FET and n-type GAA FET fabricated out of single structure with a power supply coupled thereto; Fig. 1; paragraphs [0002], [0029], [0038]).
Regarding claim 30, Vellianitis discloses an integrated circuit device, comprising:
a first source or drain semiconductor of a first conductivity type coupled to a plurality of first channel layers of a first gate-all-around transistor and a first gate dielectric adjacent each of the plurality of first channel layers (IC device having boron-doped first source/drain 60 coupled to semiconductor layers 20 of n-type GAA FET Fn, where first portion of gate dielectric 82 is adjacent layers 20; Figs. 2, 9A, 13A, 15A and 15C; paragraphs [0041], [0043], [0063], [0077]-[0080], [0099]; claim 13);
a second source or drain semiconductor of a second conductivity type coupled to a plurality of second channel layers of a second gate-all-around transistor and a second gate dielectric adjacent each of the plurality of second channel layers (phosphorous and/or arsenic-doped second source/drain 65 coupled to semiconductor layers 25 of p-type GAA FET Fp, where second portion of gate dielectric 82 is adjacent layers 25; Figs. 2, 9A, 13A, 15A and 15C; paragraphs [0041], [0043], [0063], [0072], [0075], [0077]-[0080], [0099]; claim 13), the second source or drain laterally adjacent the first source or drain semiconductor (source/drain 65 disposed laterally adjacent source/drain 60 as shown in Fig. 15A); and
a portion of a dielectric layer extending between the first source or drain semiconductor and the second source or drain semiconductor (portion of ILD 50 disposed between source/drain 60 and source/drain 65 as shown in Fig. 15A; paragraphs [0057]-[0058]), wherein the portion of the dielectric layer is over an isolation material between the first and second gate-all-around transistors (ILD 50 disposed over STI layer 30 and between n-type GAA FET Fn and p-type GAA FET Fp as shown in 15A; paragraphs [0048], [0050]), an entirety of the portion of the dielectric layer is laterally between the first source or drain semiconductor and the second source or drain semiconductor such that the portion of the dielectric layer does not extend above or below top and bottom surfaces of the first source or drain semiconductor and the second source or drain semiconductor (portion of ILD 50 disposed between left, right, top and bottom sides of far right source/drain 60 and far left source/drain 65 as shown in Figs. 7 and 15A; paragraphs [0057]-[0058]), and the portion of the dielectric layer has a first thickness at a first position adjacent the first source or drain semiconductor, a second thickness, less than the first thickness, at a second position between the first position and the second source or drain semiconductor (portion of ILD 50 having a first vertical thickness potion at a first position adjacent a lower left side of left source/drain 60 and a second thickness portion less than the first at a second position adjacent an upper right side of right source/drain 65 above spacer and between first position and source/drains 65 at least as shown in Figs. 7 and 15A), and a third thickness, substantially the same as the second thickness, at a third position between the first position and the first source or drain semiconductor (portion of ILD 50 comprises third thickness equal to the second thickness adjacent an upper left side of left source/drain 60 above spacer between lower left side of left source/drain 60 and the source/drains 60; Figs. 7 and 15A).
Vellianitis fails to explicitly disclose the isolation material has a top surface between top and bottom surfaces of the first source or drain semiconductor and the second source or drain semiconductor, respectively.
However, Vellianitis already discloses the STI layer 30 comprising a top surface that is horizontally aligned with the bottom surface of the source/drain 60 and source/drain 65; Fig. 15A. Further, the bottom fin layer 11 may be made from Si and Ge which are the same materials utilized in source/drain 60 and source/drain 65 (see paragraphs [0043], [0063] and [0071]) and therefore could be considered to be an extension of source/drain 60 and source/drain 65 which would mean the top surface of the STI layer 30 is between bottom and top surfaces of source/drain 60 and source/drain 65.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Vellianitis to have the STI layer 30 extend to any degree above the bottom surfaces of the source/drain 60 and source/drain 65 in order to potentially provide better isolation and reduced leakage paths, improved structural support and reduced defects, and control of strain and electrostatics.
Regarding claim 31, Vellianitis discloses the integrated circuit device of claim 30, wherein the second thickness is not more than half the first thickness (top of spacer adjacent right source/drain 65 is located above thickness midpoint of portion of ILD 50 and lower left side of left source/drain 60 located at terminus of ILD 50, therefore second thickness is not more than half the first thickness; Fig. 7).
Regarding claim 32, Vellianitis discloses the integrated circuit device of claim 30, wherein the isolation material comprises silicon and oxygen, and the portion of the dielectric layer comprises silicon and at least one of oxygen, carbon, or nitrogen (STI layer 30 may include silicon oxide and ILD 50 may comprise oxygen; paragraphs [0048], [0057], [0078]).
Regarding claim 33, Vellianitis discloses the integrated circuit device of claim 30, wherein the first position and the third position are not more than 10 nm apart in a direction extending between the first source or drain semiconductor and the second source or drain semiconductor (each source/drain may have a horizontal width of about 5 nanometers, therefore upper left side position of left source/drain 60 and lower left side position of left source/drain 60 are not more than 10 nanometers apart in the horizontal direction; Fig. 7; paragraph [0045]).
Regarding claim 34, Vellianitis discloses the integrated circuit device of claim 30, wherein the portion of the dielectric layer comprises a same material as a gate spacer of the first and second gate-all-around transistors (sidewall spacers 48 and ILD 50 may comprise SiN; paragraphs [0055], [0057]).
Regarding claim 35, Vellianitis discloses the integrated circuit device of claim 30, wherein the first and second gate-all-around transistors are in a monolithic die, the integrated circuit device further comprising a power supply coupled to the monolithic die (p-type GAA FET and n-type GAA FET fabricated out of single structure with a power supply coupled thereto; Fig. 1; paragraphs [0002], [0029], [0038]).
Response to Arguments
Applicant's arguments filed February 27, 2026 have been fully considered. Applicant presents amendment to claims 1, 24 and 30 with corresponding arguments that these amendments overcome the 35 USC 102 rejection using Vellianitis. Examiner agrees that Vellianitis does not explicitly disclose the amended limitation. However, Vellianitis already discloses the STI layer 30 comprising a top surface that is horizontally aligned with the bottom surface of the source/drain 60 and source/drain 65 and suggests that the bottom fin structure 11 could be an extension of the source/drains 60, 65 given the overlap in similar materials and structural continuity and so a new ground of rejection that was necessitated by the amendments has been made under 35 USC 103 using Vellianitis as outlined above. Further, Applicant argues that Fig. 7 shows the ILD 50 having uniform thickness, but it is clear from Fig. 7 that the ILD 50 cannot possibly have uniform thickness given the irregular vertical dimensions of the source/drains 60, 65 which are disposed within the ILD 50. Applicant does not address the full analysis provided in regards to this limitation of the independent claims which specifically state the areas of ILD 50 which have non-uniform relative thickness.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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