DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 2/3/2026. Claims 1-10 and 12-25 are pending and have been examined. Claims 1, 7, 13 and 19 have been amended. Claim 11 has been canceled. Claim 25 has been added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 13-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carey, PGPUB No. 2019/0187966, Maidee, USPAT No. 11,886,854 and further in view of NPL reference, “Offload Annotations: Bringing Heterogeneous Computing to Existing Libraries and Workloads” hereby referred to as Yuan.
In regards to claim 1, Carey discloses A computing system (See Fig. 3, element 300 (see [0042])) comprising: a network controller (See Fig. 3, network interface (element 350) (see [0051])) a processor coupled to the network controller (See Fig. 3: wherein processor (element 310) is coupled to network interface (element 350)) and memory coupled to the processor (See Fig. 3: wherein memory (element 320) is coupled to processor (element 310)) the memory storing instructions which, when executed by the processor ([0047]) cause the computing system to: scan program code to detect a recognizable library code ([0082-0084 and 0087]: wherein a program is analyzed (scanned) to detect a recognizable software library (element 2410) which can be optimized by being implemented in an accelerator (See Figs. 3 and 6, paragraph [0043 and 0066] for further details on accelerator deployment tool that analyzes code to perform method of Fig. 25))
detecting a library signature for a library function that uniquely identifies the library function ([0082-0084]: wherein the detecting includes detecting a function call (library signature, e.g. call L1) for a library function that uniquely identifies the library function (See Figs. 24-25)) and upon detection of the library signature, perform one of: substitute the accelerator call for the library function associated with the library signature ([0083-0084 and 0087]: wherein upon detection of a function call (library signature) accelerator calls are substituted for the library functions (L1-LN) associated with the function calls (See Figs. 25 and 30)) or apply the accelerator tag to the library function associated with the library signature to indicate the accelerator call is to be substituted for the library function, wherein upon the accelerator tag being applied to the library function associated with the library signature, a subsequent scan is to be performed to detect the accelerator tag and substitute the accelerator call for the library function tagged with the accelerator tag.
Carey does not disclose scan program code to detect an accelerator tag to indicate an accelerator call for the library function, the library signature for the library function being generated through applying a hashing algorithm to the library function; and upon detection of the accelerator tag, substitute the accelerator call for the library function tagged with the accelerator tag. Carey discloses scanning code to detect library function calls which uniquely identify library functions, and upon detection of the library function calls accelerator calls for the library functions are substituted. However, Carey does not disclose substituting accelerator calls based on library signatures which are generated by applying a hashing algorithm to the library functions.
Maidee discloses a library signature for a library function that uniquely identifies the library function and the library signature for the library function being generated through applying a hashing algorithm to the library function (Column 6, lines 1-22 and Column 10, lines 64-67 to Column 11, lines 1-25: wherein a compute ID is a library signature which uniquely identifies a library function and is a hash of the function. Wherein the compute ID is used to replace a function with a hardware library function (See Figs. 1-2 and 7))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify library code of Carey to include library signatures as the library code of Maidee. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using library signatures generated by hashing library functions to substitute accelerator calls as taught in Maidee) for another (using generic library signatures to substitute accelerator calls as taught in Carey) to yield predictable results (using library signatures generated by hashing library functions to substitute accelerator calls to perform accelerator functions) (MPEP 2143, Example B). Furthermore, using the unique compute IDs indicates that a software function may have a functionally equivalent hardware accelerator function which can replace it and improve function processing performance (Maidee: Column 6, lines 18-21, Column 11, lines 65-67 and Column 18, lines 5-7).
The combination of Carey and Maidee does not disclose scan program code to detect an accelerator tag to indicate an accelerator call for the library function and upon detection of the accelerator tag, substitute the accelerator call for the library function tagged with the accelerator tag. Carey and Maidee disclose detecting library signatures to software library functions and replacing library functions with accelerator calls to an accelerator as to improve run-time performance of the code. However, Carey and Maidee do not disclose replacing library functions with accelerator calls upon detecting an accelerator tag.
Yuan discloses scan program code to detect an accelerator tag to indicate an accelerator call for the library function (See Abstract and section 1 on page 293: wherein a program is scanned during runtime to detect an offload annotation (accelerator tag) in a CPU function of a CPU library. Wherein the annotation corresponds to an accelerator (for example a GPU, see page 299 section 6 for other examples of accelerators) and specifies a corresponding accelerator function to be called in an accelerator library. Thus, the offload annotation can be considered an accelerator tag (See Fig. 1 and section 5 on pages 295 and 297 for further clarity)) upon detection of the accelerator tag, substitute the accelerator call for a library function tagged with the accelerator tag (See Abstract and section 1 on page 293: wherein upon detection of the offload annotation an accelerator function call is substituted for the CPU library function tagged with the offload annotation (See Fig. 1 and section 5 on pages 295 and 297 for further clarity))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Carey to use offload annotations in the CPU library to replace library functions with calls to accelerator functions as taught in Yuan. It would have been obvious to one of ordinary skill in the art because the offload annotations enable end users to use both CPU libraries and emerging accelerator libraries with few or no changes to code, allow automatic offloading of functions to an accelerator, page large datasets, transfer data across devices automatically, and manage allocations to minimize data transfer for better performance. (Yuan: Abstract, Introduction and Section 3 on pages 293-295)
Claim 13 is similarly rejected on the same basis as claim 1 above as claim 13 is the computer readable storage medium corresponding to the system of claim 1. (See [0053] which discloses a non-transitory computer readable storage medium)
Claim 19 is similarly rejected on the same basis as claim 1 above as claim 19 is the method corresponding to the system of claim 1.
In regards to claim 2, the combination of Carey, Maidee and Yuan discloses The computing system of claim 1 (see rejection of claim 1 above) wherein to substitute the accelerator call comprises to provide a plurality of code segments (Carey [0043-0044 and 0066]: wherein to substitute accelerator calls the accelerators must first be programmed or imaged in order to provide the accelerators used to perform the functions. Thus, substituting the accelerator call comprises deploying accelerator images or HDL (code segments) to each corresponding accelerator (See Figs. 4, 6, 8, 11 for further clarity of accelerator deployment tools used to generate code segments used to image one or more accelerators)) each code segment optimized for a respective one of a plurality of hardware accelerators (Carey [0065-0066, 0082, 0087 and 0089]: wherein each accelerator image or HDL (code segments) is optimized for a respective one of a plurality of accelerators of a programmable device. For example, each accelerator can perform a different function such as compression, graphics, floating-point, etc.; thus, each code segment would be optimized for a different function for each respective hardware accelerator (See Figs. 4, 6, 8, 11 for further clarity of accelerator deployment tools used to generate code segments used to image one or more accelerators of a programmable device)) and wherein one of the plurality of code segments is to be selected based on availability of the respective one of the plurality of hardware accelerators. (Carey [0083 and 0088]: wherein an accelerator image or HDL (code segment) to implement an accelerator is selected based on availability of hardware accelerator resources of a programmable device)
Claim 14 is similarly rejected on the same basis as claim 2 above as claim 14 is the computer readable storage medium corresponding to the system of claim 2.
Claim 20 is similarly rejected on the same basis as claim 2 above as claim 20 is the method corresponding to the system of claim 2.
In regards to claim 3, the combination of Carey, Maidee and Yuan discloses The computing system of claim 1 (see rejection of claim 1 above) wherein to substitute the accelerator call comprises to provide a code segment that interfaces with a plurality of hardware accelerators (Carey [0043-0047]: wherein accelerator deployment tool (code segment as it is software code executed by processor) interfaces with accelerators of programmable device (element 312) as to image and program/re-program accelerators which are used upon substituting accelerator calls(See Figs. 3-4 and 6)) and wherein one of the plurality of hardware accelerators is to be selected based on availability. (Carey [0083 and 0088]: wherein the selected hardware accelerator is selected based on being an available hardware accelerator resource)
Claim 15 is similarly rejected on the same basis as claim 3 above as claim 15 is the computer readable storage medium corresponding to the system of claim 3.
Claim 21 is similarly rejected on the same basis as claim 3 above as claim 21 is the method corresponding to the system of claim 3.
In regards to claim 4, the combination of Carey, Maidee and Yuan discloses The computing system of claim 1 (see rejection of claim 1above) wherein the instructions, when executed, further cause the computing system to: provide an interface between the program code and one or more hardware accelerators (Carey [0043-0044 and Figs. 3-4]: wherein an accelerator deployment tool is an interface between the program code including code portions and one or more accelerators of a programmable device)and perform translation between the program code and a selected one of the one or more hardware accelerators (Carey [0060 and 0067]: wherein code portions of the program code are converted (translated) to code to be implemented on a selected one of hardware accelerators) wherein the selected one of the one or more hardware accelerators is to be selected based on availability. (Carey [0083 and 0088]: wherein the selected hardware accelerator is selected based on being an available hardware accelerator resource)
Claim 16 is similarly rejected on the same basis as claim 4 above as claim 16 is the computer readable storage medium corresponding to the system of claim 4.
Claim 22 is similarly rejected on the same basis as claim 4 above as claim 22 is the method corresponding to the system of claim 4.
In regards to claim 5, the combination of Carey, Maidee and Yuan thus far discloses “The computing system of claim 4 (see rejection of claim 4 above) wherein the instructions, when executed, further cause the computing system (Carey: Fig. 3 and [0047]))
The combination of Carey, Maidee and Yuan thus far does not disclose provide one or more services required by the selected one of the one or more hardware accelerators at run time.
Yuan discloses provide one or more services required by the selected one of the one or more hardware accelerators at run time. (Pages 297-298: wherein data transfer services are provided as to provide data required to execute functions on the accelerator during runtime (See Sections 4.2 and 5) (note: examiner interprets this limitation similarly as in applicant’s specification which indicates that memory allocation is a service as discussed in paragraph [0390]))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Carey, which performs functions in an accelerator to optimize run-time execution of code, to provide a service which would transfer data to an accelerator used to execute an offloaded function as disclosed in Yuan. It would have been obvious to one of ordinary skill in the art because the ability to automatically transfer values is necessary to ensure that values reside on the device (i.e., accelerator) where the operation will run (Yuan: pages 295 and 297).
Claim 17 is similarly rejected on the same basis as claim 5 above as claim 17 is the computer readable storage medium corresponding to the system of claim 5.
Claim 23 is similarly rejected on the same basis as claim 5 above as claim 23 is the method corresponding to the system of claim 5.
In regards to claim 6, the combination of Carey, Maidee and Yuan discloses The computing system of claim 1 (see rejection of claim 1 above) wherein the instructions, when executed, further cause the computing system to determine whether to substitute the accelerator call based at least on one or more of performance, resources, environment, or task priority. (Carey [0068, 0071, 0083 and 0088]: wherein determining whether to substitute the accelerator call is based on run-time performance and available accelerator resources| Yuan, section 5 and page 298: wherein the accelerator function is substituted based on runtime performance calculations. For example, cost estimates are determined for running the function in CPU and on accelerator, and if accelerator has lower cost estimate the function is run on accelerator)
Claim 18 is similarly rejected on the same basis as claim 6 above as claim 18 is the computer readable storage medium corresponding to the system of claim 6. (See [0053] which discloses a computer readable storage medium)
Claim 24 is similarly rejected on the same basis as claim 6 above as claim 24 is the method corresponding to the system of claim 6.
In regards to claim 25, the combination of Carey, Maidee and Yuan discloses The computing system of claim 1 (see rejection of claim 1 above) wherein the accelerator tag corresponds to a hardware accelerator (Yuan: See Abstract and section 1 on page 293: wherein offload annotation corresponds to GPU accelerator) and upon detection of the accelerator tag, the accelerator call for the library function is directed to the hardware accelerator. (Yuan: See Abstract and section 1 on page 293: wherein upon detection of the offload annotation an accelerator call for the function is directed to GPU accelerator to offload the function (See Fig. 1 and section 5 on pages 295 and 297 for further clarity))
Claim(s) 7-10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carey, Yuan, Maidee and further in view of Schluessler, PGPUB No. 2019/0087998 (cited on IDS filed on 7/24/2023).
In regards to claim 1, Carey discloses An apparatus (See Fig. 3, element 300 (see [0042])) comprising: circuit implemented at least partly in hardware logic (See Fig. 3 and [0047]: wherein processor (element 310) is a hardware processor that executes instructions) circuit to: scan program code to detect a recognizable library code ([0082-0084 and 0087]: wherein a program is analyzed (scanned) to detect a recognizable software library (element 2410) which can be optimized by being implemented in an accelerator (See Figs. 3 and 6, paragraph [0043 and 0066] for further details on accelerator deployment tool that analyzes code to perform method of Fig. 25)) detecting a library signature for a library function that uniquely identifies the library function ([0082-0084]: wherein the detecting includes detecting a function call (library signature, e.g. call L1) for a library function that uniquely identifies the library function (See Figs. 24-25)) and upon detection of the library signature, perform one of: substitute the accelerator call for the library function associated with the library signature ([0083-0084 and 0087]: wherein upon detection of a function call (library signature) accelerator calls are substituted for the library functions (L1-LN) associated with the function calls (See Figs. 25 and 30)) or apply the accelerator tag to the library function associated with the library signature to indicate the accelerator call is to be substituted for the library function, wherein upon the accelerator tag being applied to the library function associated with the library signature, a subsequent scan is to be performed to detect the accelerator tag and substitute the accelerator call for the library function tagged with the accelerator tag.
Carey does not disclose semiconductor apparatus comprising: one or more substrates; and circuit coupled to the one or more substrates, the circuit implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the circuit to: scan program code to detect an accelerator tag to indicate an accelerator call for the library function, the library signature for the library function being generated through applying a hashing algorithm to the library function; and upon detection of the accelerator tag, substitute the accelerator call for the library function tagged with the accelerator tag. Carey discloses scanning code to detect library function calls which uniquely identify library functions, and upon detection of the library function calls accelerator calls for the library functions are substituted. However, Carey does not disclose substituting accelerator calls based on library signatures which are generated by applying a hashing algorithm to the library functions.
Maidee discloses a library signature for a library function that uniquely identifies the library function and the library signature for the library function being generated through applying a hashing algorithm to the library function (Column 6, lines 1-22 and Column 10, lines 64-67 to Column 11, lines 1-25: wherein a compute ID is a library signature which uniquely identifies a library function and is a hash of the function. Wherein compute ID is used to replace library function with accelerator function (See Figs. 1-2 and 7))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify library code of Carey to include library signatures as the library code of Maidee. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using library signatures generated by hashing library functions to substitute accelerator calls as taught in Maidee) for another (using generic library signatures to substitute accelerator calls as taught in Carey) to yield predictable results (using library signatures generated by hashing library functions to substitute accelerator calls to perform accelerator functions) (MPEP 2143, Example B). Furthermore, using the unique compute IDs indicates that a software function may have a functionally equivalent hardware accelerator function which can replace it and improve function processing performance (Maidee: Column 6, lines 18-21, Column 11, lines 65-67 and Column 18, lines 5-7).
The combination of Carey and Maidee does not disclose semiconductor apparatus comprising: one or more substrates; and circuit coupled to the one or more substrates, the circuit implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the circuit to: scan program code to detect an accelerator tag to indicate an accelerator call for the library function and upon detection of the accelerator tag, substitute the accelerator call for the library function tagged with the accelerator tag. Carey and Maidee disclose detecting function calls library signatures to software library functions and replacing library functions with accelerator calls to an accelerator as to improve run-time performance of the code. However, Carey and Maidee do not disclose replacing library functions with accelerator calls upon detecting an accelerator tag.
Yuan discloses scan program code to detect an accelerator tag to indicate an accelerator call for the library function (See Abstract and section 1 on page 293: wherein a program is scanned during runtime to detect an offload annotation (accelerator tag) in a CPU function of a CPU library. Wherein the annotation corresponds to an accelerator (for example a GPU, see page 299 section 6 for other examples of accelerators) and specifies a corresponding accelerator function to be called in an accelerator library. Thus, the offload annotation can be considered an accelerator tag (See Fig. 1 and section 5 on pages 295 and 297 for further clarity)) upon detection of the accelerator tag, substitute the accelerator call for a library function tagged with the accelerator tag (See Abstract and section 1 on page 293: wherein upon detection of the offload annotation an accelerator function call is substituted for the CPU library function tagged with the offload annotation (See Fig. 1 and section 5 on pages 295 and 297 for further clarity))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Carey to use offload annotations in the CPU library to replace library functions with calls to accelerator functions as taught in Yuan. It would have been obvious to one of ordinary skill in the art because the offload annotations enable end users to use both CPU libraries and emerging accelerator libraries with few or no changes to code, allow automatic offloading of functions to an accelerator, page large datasets, transfer data across devices automatically, and manage allocations to minimize data transfer for better performance. (Yuan: Abstract, Introduction and Section 3 on pages 293-295)
The overall combination of Carey, Maidee and Yuan does not disclose semiconductor apparatus comprising: one or more substrates; and circuit coupled to the one or more substrates, the circuit implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic.
Schluessler discloses semiconductor apparatus ([0126 and Fig. 11B]) comprising: one or more substrates ([0126]: wherein a substrate (element 1180) is disclosed) and circuit coupled to the one or more substrates, the circuit implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic. ([0126]: wherein circuitry (elements 1172 and 1174) is coupled to the substrate and the circuitry is implemented in configurable logic or fixed-functionality)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Carey to be implemented in an integrated circuit semiconductor apparatus as taught in Schluessler. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (implementing a system as an integrated circuit semiconductor apparatus as taught in Schluessler) for another (implementing a system as a generic apparatus as taught in Carey) to obtain predictable results (implementing an integrated circuit semiconductor apparatus including hardware logic to perform operations) (MPEP 2143, Example B). Furthermore, integrated circuit semiconductor devices can provide improved performance, lower power consumption and be more cost-effective for manufacturing purposes.
In regards to claim 8, the combination of Carey, Maidee, Yuan and Schluessler discloses The semiconductor apparatus of claim 7 (see rejection of claim 7 above) wherein to substitute the accelerator call comprises to provide a plurality of code segments (Carey [0043-0044 and 0066]: wherein to substitute accelerator calls the accelerators must first be programmed or imaged in order to provide the accelerators used to perform the functions. Thus, substituting the accelerator call comprises deploying accelerator images or HDL (code segments) to each corresponding accelerator (See Figs. 4, 6, 8, 11 for further clarity of accelerator deployment tools used to generate code segments used to image one or more accelerators)) each code segment optimized for a respective one of a plurality of hardware accelerators (Carey [0065-0066, 0082, 0087 and 0089]: wherein each accelerator image or HDL (code segments) is optimized for a respective one of a plurality of accelerators of a programmable device. For example, each accelerator can perform a different function such as compression, graphics, floating-point, etc.; thus, each code segment would be optimized for a different function for each respective hardware accelerator (See Figs. 4, 6, 8, 11 for further clarity of accelerator deployment tools used to generate code segments used to image one or more accelerators of a programmable device)) and wherein one of the plurality of code segments is to be selected based on availability of the respective one of the plurality of hardware accelerators. (Carey [0083 and 0088]: wherein an accelerator image or HDL (code segment) to implement an accelerator is selected based on availability of hardware accelerator resources of a programmable device)
In regards to claim 9, the combination of Carey, Maidee, Yuan and Schluessler discloses The semiconductor apparatus of claim 7 (see rejection of claim 7 above) wherein to substitute the accelerator call comprises to provide a code segment that interfaces with a plurality of hardware accelerators (Carey [0043-0047]: wherein accelerator deployment tool (code segment as it is software code executed by processor) interfaces with accelerators of programmable device (element 312) as to image and program/re-program accelerators which are used upon substituting accelerator calls(See Figs. 3-4 and 6)) and wherein one of the plurality of hardware accelerators is to be selected based on availability. (Carey [0083 and 0088]: wherein the selected hardware accelerator is selected based on being an available hardware accelerator resource)
In regards to claim 10, the combination of Carey, Maidee, Yuan and Schluessler discloses The semiconductor apparatus of claim 7 (see rejection of claim 7 above) wherein the circuit is further to: provide an interface between the program code and one or more hardware accelerators (Carey [0043-0044 and Figs. 3-4]: wherein an accelerator deployment tool is an interface between the program code including code portions and one or more accelerators of a programmable device)and perform translation between the program code and a selected one of the one or more hardware accelerators (Carey [0060 and 0067]: wherein code portions of the program code are converted (translated) to code to be implemented on a selected one of hardware accelerators) wherein the selected one of the one or more hardware accelerators is to be selected based on availability. (Carey [0083 and 0088]: wherein the selected hardware accelerator is selected based on being an available hardware accelerator resource)
In regards to claim 12, the combination of Carey, Maidee, Yuan and Schluessler discloses The semiconductor apparatus of claim 7 (see rejection of claim 7 above) wherein the circuit is further to determine whether to substitute the accelerator call based at least on one or more of performance, resources, environment, or task priority. (Carey [0068, 0071, 0083 and 0088]: wherein determining whether to substitute the accelerator call is based on run-time performance and available accelerator resources| Yuan, section 5 and page 298: wherein the accelerator function is substituted based on runtime performance calculations. For example, cost estimates are determined for running the function in CPU and on accelerator, and if accelerator has lower cost estimate the function is run on accelerator)
Response to Arguments
Applicant’s arguments, see pages 8-9 of remarks, filed on 2/3/2026, with respect to the rejection(s) of claim(s) 1, 7, 13 and 19 under 35 USC 103 in view of Carey and Yuan and/or Carey, Yuan and Schluessler have been fully considered and are persuasive. Therefore, the rejection(s) have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Carey, Maidee and Yuan and/or Carey, Maidee, Yuan and Schluessler.
Claims 2-6, 8-10, 12, 14-18 and 20-25 are argued at least based on dependency upon one of the independent claims above and therefore remain rejected at least based upon their respective dependencies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183