Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed August 10, 2026. Claims 1, 3 and 11 are amended. Claims 2 and 4-8 are cancelled. Claims 9-10 and 16-20 remain withdrawn. The Examiner notes that claims 1, 3, and 11-15 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2021/0225839 A1) in view of Cheng (2021/0159124 A1).
With respect to claim 1, Lin teaches in the embodiment of Fig. 19:
An integrated circuit structure, comprising:
a first device (FinFET I/O device structure 206c) comprising a fin (“FinFET” comprising semiconductor layers 220 and 222) above a substrate (substrate 208),
and a first gate structure (gate dielectric layers 250c and gate electrode 272 above 206c) over the fin (220 and 22 of 206c);
the first gate structure (272 +250c) comprising a first gate dielectric (250c) having a first lateral width from a sidewall of the fin;
and a second device (GAA core device structure 206b) comprising a vertical arrangement of horizontal nanowires (semiconductor nanowires 220) above a sub- fin structure (part of 208 laterally between isolation structures 210) above the substrate (208),
and a second gate structure (gate dielectric layers 250b and gate electrode 272 surrounding 206a and 206b) surrounding the vertical arrangement of horizontal nanowires (220 in 206b),
the second gate structure (gate dielectric layers 250b and gate electrode 272 surrounding 206a and 206b) comprising a second gate dielectric (250b) having a second lateral width from a sidewall of a nanowire of the vertical arrangement of horizontal nanowires,
the second lateral width less than the first lateral width (para. 43 “the gate dielectric layer 250b has a second CET thickness which is medium suiting low-power and/or low-leakage application, and the gate dielectric layer 250c has the thickest CET thickness suiting high-voltage application”).
Lin fails to teach:
wherein the fin comprises alternating regions of silicon and silicon germanium, with an uppermost region being a region of silicon germanium
wherein the nanowires are regions of silicon,
wherein the vertical arrangement of horizontal nanowires has an uppermost surface below an uppermost surface of the fin.
Cheng teaches in Figs. 32A-B and 34C-D:
wherein the fin comprises alternating regions of silicon and silicon germanium, with an uppermost region being a region of silicon germanium ([0120] teaches an embodiment in which the second semiconductor (25) is made from SiGe and the first semiconductor wires (20 of Fig. 34D, 22 after etching in Fig. 32B, “In one or more of the foregoing and the following embodiments, the second semiconductor wires are made of Si.sub.1-xGe.sub.x, where 0.45≤x≤0.55, and the first semiconductor wires are made of Si”)
wherein the nanowires are regions of silicon ([120] teaches an embodiment where the first semiconductor wires are made of Si),
wherein the vertical arrangement of horizontal nanowires (nanowires 22 in device on right side of Fig. 32B, which is a cross sectional view of Fig. 32A) has an uppermost surface below an uppermost surface of the fin (fin device shown in 34D which may be combined with the device of Fig. 32A according to para. 107).
Lin discloses the claimed invention except for the uppermost surface of the horizontal nanowires being lower than the uppermost surface of the fin and the top layers of the stack being SiGe that alternates with Si, which makes up the nanowaires. Cheng discloses that it is known in the art to provide a nanowire structure with a lower uppermost surface than a fin. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the uppermost surfaces as claimed for the purpose of improving the performances of the GAA FET through a condensation process. See MPEP 2144. Cheng also teaches that it is known to make a stack that is an arrangement of Si and SiGe with an upper region of SiGe and nanowires of the nanowire device that are Si. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lin by Cheng to have SiGe as the top layer and Si as the other layer and nanowire layer, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416. The ordinary artisan would be motivated to choose those materials so that the nanowire FET made from Si can be a n-FET.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2021/0225839 A1) and Cheng (2021/0159124 A1) as applied to independent claim 1 above and further in view of Py (Journal of Applied Physics, 2011) as evidenced by More (US 10,510,871 B1).
With respect to claim 3, Lin/Cheng teaches all limitations of independent claim 1 upon which claim 3 depends. Lin/Cheng is silent to:
neighboring ones of the regions of silicon and silicon germanium have a diffuse interface.
The Examiner takes the position that although Lin is silent to the nature of the interface of the Si and SiGe layers, a diffuse interface is inherent to the formation of a Si/SiGe superlattice and that Lin inherently teaches “neighboring ones of the regions having a diffuse interface”. As evidence, More teaches a Si/SiGe superlattice and teaches in col. 8, lns. 10-12 that “as the second layer is deposited over the first layer and the materials of the second layer and first layer diffuse into the first layer or second layer.” More teaches that the diffusion interface thickness depends on the deposition process, and that “a Si/SiGe diffusion interface may be controlled to a thickness between about 0.5 nm to about 1.5 nm” (col. 8, lns. 15-17) but in all embodiments of More the interface between Si and SiGe is not perfectly abrupt and a diffuse interface still exists.
The Examiner further notes that the criticality of the diffuse interface is given in para. 30 of the instant application. “Several embodiments are described which remove a superlattice in an I/O transistor by intermixing the Si and SiGe. One embodiment involves using helium (He) implant, only in thick gate oxide regions, after active patterning to intentionally provoke intermixing of the Si and SiGe. Ultimately, the purpose can be to provide a "homogeneous" fin and associated channel region sufficiently homogeneous (e.g., without the discontinuity inherent to a superlattice) that a thick oxide can then be deposited and the device can operate reliably” (emphasis added). Lin teaches that a thick oxide (gate dielectric 250c including thick oxide layer 230) is deposited on the Si/SiGe superlattice fin and that the device operates reliably (para. 43 “the gate dielectric layer 250c has the thickest CET thickness suiting high-voltage application.”). The Examiner determines that as the device of Lin functions reliably after a thick oxide is deposited, it inherently possesses the diffuse interface required to meet the claim limitation.
In the event that the diffuse interface is not inherent to Lin, which the Examiner does not concede, it would be obvious to arrive at a diffuse interface though optimization within prior art conditions or through routine experimentation. The claim directs to the concentration of Ge throughout the superlattice fin and “generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical.” MPEP 2144.05(II)(A). Py teaches in Fig. 2 that annealing an Si/SiGe superlattice leads to diffusion of Ge atoms between the SiGe and Si layers and teaches in Fig. 11 that annealing of the Si/SiGe interface also tunes the stress characteristics of the superlattice.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Py into the device of Lin/Cheng to include a superlattice with a diffuse interface. The ordinary artisan would have been motivated to modify Lin/Cheng in the manner set forth above for the purpose optimizing the stress characteristics of the device within prior art conditions or through routine experimentation.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2021/0225839 A1) in view of Cheng (2021/0159124 A1) and Lilak (US 2020/0006331 A1).
With respect to claim 11, Lin teaches in the embodiment of Fig. 19:
The component including an integrated circuit structure, comprising:
a first device (FinFET I/O device structure 206c) comprising a fin (“FinFET” comprising semiconductor layers 220 and 222) above a substrate (substrate 208),
and a first gate structure (gate dielectric layers 250c and gate electrode 272 above 206c) over the fin (220 and 22 of 206c);
the first gate structure (272 +250c) comprising a first gate dielectric (250c) having a first lateral width from a sidewall of the fin;
and a second device (GAA core device structure 206b) comprising a vertical arrangement of horizontal nanowires (semiconductor nanowires 220) above a sub- fin structure (part of 208 laterally between isolation structures 210) above the substrate (208),
and a second gate structure (gate dielectric layers 250b and gate electrode 272 surrounding 206a and 206b) surrounding the vertical arrangement of horizontal nanowires (220 in 206b),
the second gate structure (gate dielectric layers 250b and gate electrode 272 surrounding 206a and 206b) comprising a second gate dielectric (250b) having a second lateral width from a sidewall of a nanowire of the vertical arrangement of horizontal nanowires,
the second lateral width less than the first lateral width (para. 43 “the gate dielectric layer 250b has a second CET thickness which is medium suiting low-power and/or low-leakage application, and the gate dielectric layer 250c has the thickest CET thickness suiting high-voltage application”).
Lin does not explicitly teach:
A computing device, comprising:
a board; and
a component coupled to the board
wherein the fin comprises alternating regions of silicon and silicon germanium, with an uppermost region being a region of silicon germanium,
wherein the nanowires are regions of silicon,
wherein the vertical arrangement of horizontal nanowires has an uppermost surface below an uppermost surface of the fin.
Cheng teaches in Figs. 32A-B and 34C-D:
wherein the fin comprises alternating regions of silicon and silicon germanium, with an uppermost region being a region of silicon germanium ([0120] teaches an embodiment in which the second semiconductor (25) is made from SiGe and the first semiconductor wires (20 of Fig. 34D, 22 after etching in Fig. 32B, “In one or more of the foregoing and the following embodiments, the second semiconductor wires are made of Si.sub.1-xGe.sub.x, where 0.45≤x≤0.55, and the first semiconductor wires are made of Si”)
wherein the nanowires are regions of silicon ([120] teaches an embodiment where the first semiconductor wires are made of Si),
wherein the vertical arrangement of horizontal nanowires (nanowires 22 in device on right side of Fig. 32B, which is a cross sectional view of Fig. 32A) has an uppermost surface below an uppermost surface of the fin (fin device shown in Fig. 34C or 34D which may be combined with the device of Fig. 32A according to para. 107).
Lin discloses the claimed invention except for the uppermost surface of the horizontal nanowires being lower than the uppermost surface of the fin and the top layers of the stack being SiGe that alternates with Si, which makes up the nanowaires. Cheng discloses that it is known in the art to provide a nanowire structure with a lower uppermost surface than a fin. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the uppermost surfaces as claimed for the purpose of improving the performances of the GAA FET through a condensation process. See MPEP 2144. Cheng also teaches that it is known to make a stack that is an arrangement of Si and SiGe with an upper region of SiGe and nanowires of the nanowire device that are Si. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lin by Cheng to have SiGe as the top layer and Si as the other layer and nanowire layer, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416. The ordinary artisan would be motivated to choose those materials so that the nanowire FET made from Si can be a n-FET.
Lilak teaches in Fig. 5:
A computing device (computing system 1000), comprising:
a board (motherboard 1002); and
a component coupled to the board (The motherboard 1002 may include a number of components)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lilak into the device of Lin and Cheng to attach the integrated circuit to a board with a memory, communication chip, and battery for use in a computing device. The ordinary artisan would have been motivated to modify Lin in the manner set forth above for the purpose of implementing a computing system (para. 60 of Lilak) and/or because the use of boards to incorporate integrated circuits into computing systems is a well-known process in the art.
With respect to claim 12, Lin/Lilak further teaches in Fig. 5 of Lilak:
a memory (DRAM or ROM) coupled to the board (1002).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Cheng and Lilak as explained above.
With respect to claim 13, Lin/Lilak further teaches in Fig. 5 of Lilak:
a communication chip (communication chip 1006) coupled to the board (1002).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Cheng and Lilak as explained above.
With respect to claim 14, Lin/Lilak further teaches in Fig. 5 of Lilak:
a battery (“Battery”) coupled to the board.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Cheng and Lilak as explained above.
With respect to claim 15, Lin/Lilak further teaches in Fig. 5 of Lilak:
wherein the component is a packaged integrated circuit die (para. 61 “The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor”).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Cheng and Lilak as explained above.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
