DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 10/20/2025, responding to the Office action mailed on 6/20/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-15 and new claims 21-25 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshima (US 20030034523 A1) in view of Walker (US 20070029618 A1) and Clifton (US 10872964 B2).
Re Claim 12 Hiroshima teaches a transistor structure comprising a gate electrode (6) around a channel region of the transistor structure (8, FIG. 4C,) [0076], wherein the channel region comprises a first monocrystalline layer (5b, [0081] “…monocrystalline silicon film 5a as the semiconductor thin film 5b…” 5b and 8 are the same part on the chip as shown in Fig. 4C),
a first polycrystalline layer (3a) [0071] in contact with a first side of the first monocrystalline layer (FIG. 4C),
a gate insulator (10, [0075] “silicon oxide film”) between the gate electrode and each of first polycrystalline layer (FIG. 4C);
a source material (7 on left side of 8 in Fig. 8, [0076] “source/drain area 7”) coupled to a first end of the first monocrystalline layer; and
a drain material (7 on right side of 8 in Fig. 8) coupled to a second end of the first monocrystalline layers.
Hiroshima does not teach a second monocrystalline layer or a second polycrystalline layer,
However, the second monocrystalline and the second polycrystalline layer are of the same characteristics as the first monocrystalline and the first polycrystalline layer, and their physical placement has the same relationship as to the placement of first monocrystalline and the first polycrystalline layers. Therefore, the set of second monocrystalline and the second polycrystalline layer is essentially the duplication of the set of first monocrystalline layer and first polycrystalline layer. Adding a second monocrystalline layer and a second polycrystalline layer can be done by repeating processing steps. It would have been obvious to one of ordinary skill in the art at the time of filing to duplicate another set of monocrystalline and polycrystalline layers. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ8. Moreover mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Furthermore, Hiroshima does not teach the first polycrystalline layer comprising metal chalcogenide material and having one or more grain boundaries that originate within the first polycrystalline layer.
Walker teaches a transistor in analogous art, where a first polycrystalline material layer (107, [0040] “e.g., polycrystalline silicon”) having one or more grain boundaries that originate within the first polycrystalline layer ([0070] states, “As shown in FIG. 11, active semiconductor layer 107 is a polycrystalline material made up of grains of semiconductor material. Each grain may consist of an internal region, which is crystalline (often with many internal crystal defects), and an external grain boundary…”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Walker into the structure of Hiroshima to enhance the thermoelectric performance of materials and improved power factors. One would have been motivated to do so because grain boundaries can impede the movement of dislocations, a process that can lead to material deformation. By reducing grain size (and thus increasing the number of grain boundaries), the overall strength and hardness of the material can be increased, a phenomenon known as the Hall-Petch effect.
Hiroshima in view of Walker does not teach the first polycrystalline layer comprising metal chalcogenide material; and
the monocrystalline layer contains a metal chalcogenide material.
Clifton teaches a first crystalline material layer (I-Layer, 18, FIG. 3C) comprising metal chalcogenide material; and
the second crystalline material layer (conductive metal oxide, 16, FIG. 3C) contains a metal chalcogenide material (Paragraph 19 states, “…the first metal oxide layer (I-layer) is tungsten trioxide (WO.sub.3) with a thickness of between 0.2 nm and 3.0 nm, and the second metal oxide layer (M-layer)…”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Clifton into the structure of Hiroshima and Walker, to use metal chalcogenide material to build a transistor. One would have been motivated to do so because semiconductor metal chalcogenides offer several benefits due to their unique properties, including tunable bandgaps, excellent optical and electrical properties, and potential for various applications.
Re Claim 13 Hiroshima in view of Walker and Clifton teaches the transistor structure of claim 12, wherein: the first polycrystalline layer (Hiroshima, 3a) is in contact with a front side and a back side of the first monocrystalline layer (5b, FIG. 4C).
Hiroshima in view of Walker and Clifton does not teach a second monocrystalline layer or a second polycrystalline layer,
However, the second monocrystalline and the second polycrystalline layer are of the same characteristics as the first monocrystalline and the first polycrystalline layer, and their physical placement has the same relationship as to the placement of first monocrystalline and the first polycrystalline layers. Therefore, the set of second monocrystalline and the second polycrystalline layer is essentially the duplication of the set of first monocrystalline layer and first polycrystalline layer. Adding a second monocrystalline layer and a second polycrystalline layer can be done by repeating processing steps. It would have been obvious to one of ordinary skill in the art at the time of filing to duplicate another set of monocrystalline and polycrystalline layers. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ8. And mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Re Claim 14 Hiroshima in view of Walker and Clifton teaches the transistor structure of claim 12, however hoes not teach a second polycrystalline layer.
Hiroshima in view of Walker and Clifton does teach a first layer (Clifton, I-Layer, 18, FIG. 3C) comprising ZnO (Paragraph 9). If a second/duplicate layer is formed, it will comprise the same material as the first layer since the second layer is a duplication of the first layer.
Re Claim 15 Hiroshima in view of Walker and Clifton teaches the transistor structure of claim 14, however does not teach the first and second monocrystalline layers comprise the same metal and the same chalcogen as the first and second polycrystalline layers.
Hiroshima in view of Walker and Clifton does teach a first layer (Clifton, I-Layer, 18, FIG. 3C) comprising ZnO and a second layer (conductive metal oxide, 16, FIG. 3C) comprising ZnO (Paragraph 9). If duplicate layers are formed, they will comprise the same material as the first layers since the duplicate layers are a duplication of the first layers.
Claims 21 -24 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshima (US 20030034523 A1) in view of Walker (US 20070029618 A1) and Heo (US 20180151763 A1).
Re Claim 21 Hiroshima teaches a transistor structure (FIG. 4C) comprising:
a gate electrode (6) [0076] coupled to a channel region of the transistor structure (8, FIG. 4C,) [0076], wherein the channel region comprises a monocrystalline layer (5b, [0081] “…monocrystalline silicon film 5a as the semiconductor thin film 5b…” 5b and 8 are the same part on the chip as shown in Fig. 4C)
a polycrystalline layer (3a) [0071] in contact with the monocrystalline layer (5b, layers are in the same chip and are therefore in mechanical contact),
a gate insulator (10) [0075] between the gate electrode (6) and the polycrystalline layer (3a); and
a source material (7 on left side of 8 in FIG. 9, [0076] “source/drain area 7”) coupled to a first end of the monocrystalline layer (5b/8); and a drain material (7 on right side of 8 in FIG. 8,) coupled to a second end of the monocrystalline layer (5b/8, FIG. 9).
Hiroshima does not teach the polycrystalline layer having one or more grain boundaries that originate within the polycrystalline layer.
Walker teaches the first polycrystalline material layer (107, [0040] “e.g., polycrystalline silicon”) having one or more grain boundaries that originate within the first polycrystalline layer ([0070] states, “As shown in FIG. 11, active semiconductor layer 107 is a polycrystalline material made up of grains of semiconductor material. Each grain may consist of an internal region, which is crystalline (often with many internal crystal defects), and an external grain boundary…”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Walker into the structure of Hiroshima to enhance the thermoelectric performance of materials and improved power factors.
The ordinary artisan would have been motivated to do so because grain boundaries can impede the movement of dislocations, a process that can lead to material deformation. By reducing grain size (and thus increasing the number of grain boundaries), the overall strength and hardness of the material can be increased, a phenomenon known as the Hall-Petch effect.
Hiroshima in view of Walker does not teach the monocrystalline layer comprising a first metal chalcogenide material; and
the polycrystalline layer comprising a second metal chalcogenide material.
Heo teaches the crystalline layers (L10) comprising metal chalcogenide material (FIG. 11). [0074] states, “The 2D material used to form the semiconductor layer S10 may include a metal chalcogenide-based material having a 2D crystalline structure. …the chalcogen element may include one of S, Se, and Te.” Therefore, using L10 for each crystalline layer would leave a crystalline layer comprising a first metal chalcogenide material and the second crystalline layer comprising a second metal chalcogenide material.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Heo into the structure of Hiroshima in view of Walker since Heo teaches a semiconductor device containing crystalline structure layers.
The ordinary artisan would have been motivated to modify Heo in combination with Hiroshima in view of Walker in the above manner for the motivation of integrating metal chalcogen materials into the crystalline layers to help the semiconductor device function in an optimal manner.
Re Claim 22 Hiroshima in view of Walker and Heo teaches the transistor structure of claim 21, wherein the polycrystalline layer and the monocrystalline layer comprise the same metal and the same chalcogen (Heo L10 layer make up the crystalline layers, both layers are the same (L10) and therefore contain the same metal and same chalcogen, [0074] ).
Re Claim 23 Hiroshima in view of Walker and Heo teaches the transistor structure of claim 22, wherein the metal is molybdenum, tungsten or chromium (Heo [0074] mentions tungsten as possible material for L10).
Re Claim 24 Hiroshima in view of Walker and Heo teaches the transistor structure of claim 21, wherein:
the polycrystalline layer (Hiroshima, 3a) has a first metal chalcogenide stoichiometry; and the monocrystalline layer (5b/8) has a second metal chalcogenide stoichiometry (it is inherent that any physical layers will contain a stoichiometry. Hiroshima teaches a polycrystalline layer and a monocrystalline layer, and it is inherent that both have a stoichiometry).
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Re Claims 12-15: Applicant's arguments filed 10/20/2025 have been fully considered but they are not persuasive.
Applicant argues, page 4, Hiroshima in view of Walker and Clifton does not explicitly teach S, Se, or Te elements for the semiconductor materials and claims 12-15 are therefore allowable.
The examiner respectfully disagrees.
Claim broadest reasonable interpretation allows one to use Clifton as it teaches a first crystalline material layer (I-Layer, 18, FIG. 3C) comprising metal chalcogenide material; and
the second crystalline material layer (conductive metal oxide, 16, FIG. 3C) contains a metal chalcogenide material (Paragraph 19 states, “…the first metal oxide layer (I-layer) is tungsten trioxide (WO.sub.3) with a thickness of between 0.2 nm and 3.0 nm, and the second metal oxide layer (M-layer)…”).
Furthermore, oxygen is a chalcogen, and both layers referenced from Clifton contain metal and oxygen.
Allowable Subject Matter
Claims 1-11 are allowed.
Prior art does not teach or clearly suggest the following claim 1 limitation:
…the second crystalline material layer comprises one or more smaller crystal defects that originate within the second layer grains than are present within the first crystalline material layer…
Claims 2-11 depend on claim 1 and are allowable for implicitly including the allowable subject matter above.
Claim 25 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Heo (US 20180151763 A1) teaches a transistor structure comprising two crystalline material layers, a gate electrode, a source terminal, and a drain terminal.
b. Dahl (US 11037782 B1) teaches a transistor structure comprising a crystalline material layer containing one or more crystal defects.
c. Pham (US 20160284853 A1) teaches a transistor structure comprising a gate insulator containing metal and oxygen.
d. Hiroshima (US 20030034523 A1) teaches a transistor structure comprising two crystalline material layers, a gate electrode, a source terminal, and a drain terminal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/CALEB E HENRY/Primary Examiner, Art Unit 2818