Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Response to Arguments
Applicant’s arguments, filed on 10/01/2025, with respect to claim 1 have been fully considered but they are not persuasive. The Examiner respectfully disagrees for at least the following reasons:
Re: Claim 1 (and dependent claims 2-9),
applicant argues, in page 7 and 8, that none of the features of current independent claims 1 and 15 is directed to a mere intended use. Examiner has considered this position. However, the recitations that the interconnect order “corresponds to” increasing/decreasing levels of bit significance describe how the interconnects are used/assigned with respect to signal/bit ordering, and do not require additional structural differences in the interconnects beyond the recited arrangement. Therefore, such functional/relational recitations do not distinguish the claimed apparatus from an otherwise identical prior art apparatus that includes the recited interconnect structures/arrangement (MPEP 2114).
Alternatively, even assuming arguendo that the “corresponds to increase/decrease bit significance” limitations are treated as limiting structural correspondences, that feature is addressed by Muntz (US 7924826 B1) for the specific teaching of mapping successively arranged physical ports/interconnects to logical identifiers/ bit positions in an increasing sequence and in reverse sequence as set forth in the rejection below. Therefore, Applicant’s discussion of DeBaets/Foster silent on bit significance does not traverse the current basis of rejection.
Applicant further argues, in page 8, that neither the relied-upon FIGs. 2 and 3 - nor any other part of DeBaets - teaches or suggest the particular type of features which are variously recited in the claims as being in a plane and along a first direction which is orthogonal to a second line in the plane. For example, DeBaets is completely silent as to whether or how the lines 302A, 302B, 304A, 304B, 306A, 306B shown in DeBaets, FIG. 3 might provide the claimed features in some alleged plane through which said lines extend. Indeed, DeBaets fails to provide any reference whatsoever to any particular levels of bit significance, much less any particular order of such levels. Examiner respectfully disagrees. DaBaets describes, in column 6 lines 44-65, the conductive routing of Fig. 3 in a top plan view and expressly indicates that the relevant group of traces in a segment are in the same plane, with traces extending along parallel lines. Accordingly, DeBaets reasonably teaches the claimed “in the plane” arrangement and supports a first in-plane direction orthogonal to an in-plane reference line.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “…the first circuits are coupled to communicate first signals of the first communication each via a different respective one of the second interconnects; the second circuits are coupled to communicate second signals of the second communication each via a different respective one of the third interconnects…”. It is unclear to if the “first signals” are individual bit lines, or a multi-bit bus where “bit significance” would apply to its constituent bits rather than “the signal” as a whole. There is same issue of unclearly regarding “second signals” as well. For the purpose of examination, “first signals” and “second signals” are interpreted as “a plurality of first bit signals” and “a plurality of second bit signals” respectively.
Claims 2-9 are rejected under 35 U.S.C. 112(b) for their dependency of claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. Claims 1 and 3-9 are rejected under 35 U.S.C. 103 as being unpatentable over DeBaets (US 8759690 B1) in view of Muntz (US 7924826 B1).
Re: Independent Claim 1 (currently amended), DeBaets discloses an integrated circuit (IC) die comprising:
first circuits (DeBaets Fig. 3 Signal line 302B and Col. 6 lines 1-4) to participate in a first communication via first channel (fig.3 signal line 302B carries communication via channel S1);
second circuits (DeBaets Fig. 3 Signal line 306B and Col. 6 lines 1-4) to participate in a second communication via a second channel (fig.3 signal line 306B carries communication via channel S3); and
multiple interconnects (DeBaets Fig. 2 interconnects 208, 216, 224) which each extend through a plane (fig. 2, plane within which 208 lies) and to hardware interfaces on opposite respective surfaces of the IC die (DeBaets Fig 2, contacts 228 and contacts 230 and col. 5 lines 36-40), the multiple interconnects comprising:
first interconnects comprising second interconnects (first of metallization 208 of fig. 2 associated with 302B of fig. 3) which are each coupled to a different respective one of the first circuits; and third interconnects (second of metallization 208 associated with 306B) which are each coupled to a different respective one of the second circuits; and
fourth interconnects (first of metallization 208 of fig. 2 associated with 302A of fig. 3) which, within the IC die, are each electrically insulated from any transmit driver circuit and from any receiver circuit of the IC die (DeBaets Fig. 3, 302A grounded and insulated from any signal lines);
wherein: the first circuits are coupled to communicate first signals of the first communication each via a different respective one of the second interconnects (DeBaets discloses, in column 5 lines 6-10, that metal layer 208 includes conductive traces/lines (e.g., S1/302B) as the interconnects carrying the communication signals);
the second circuits are coupled to communicate second signals of the second communication each via a different respective one of the third interconnects ((DeBaets discloses, in column 5 lines 6-10, that metal layer 208 includes conductive traces/lines (e.g., S3/306B) as the interconnects carrying the communication signals); and
in the plane and along a first direction (DeBaets fig. 2, direction in which metal layer 208 lies) which is orthogonal to a second line in the plane (DeBaets fig. 3, an in-plane reference line drawn parallel to the signal lines 302A/302B/304A/304B/306A/306B and located between the signal line 302B and the signal line 306B in the plane):
the first interconnects are in an alternating arrangement with the fourth interconnects (DeBaets fig. 3, first of metallization 208 of fig. 2 associated with 302B and first of metallization 208 of fig. 2 associated with reference/ground line 302A of fig. 3 are in alternating arrangement with the other signal/reference conductors shown, e.g., G1 S1 G2 S2 G3 S3), and
the second interconnects and the third interconnects are on opposite sides of the second line (fig 2 and fig 3, signal line 302B is located on one side of said reference line and signal line 306B is on the other side reference line).
DeBaets is silent regarding:
a first order, according to which the second interconnects are successively arranged relative to each other, corresponds to an increasing order of respective levels of bit significance of the first signals as communicated with the first circuits; and a second order, according to which the third interconnects are successively arranged relative to each other, corresponds to a decreasing order of respective levels of bit significance of the second signals as communicated with the second circuits.
However, Muntz teaches, in Fig. 1 and column 3 lines 10-67 to column 3 lines 1-5, an integrated circuit device having bitwise pinouts and an internal mapping/definition such that physical ports/pins are associated with logical identifiers according to a selected mode, including: (i) a mode where pins/ports map in an ascending sequence, and (ii) another mode where pin/ports map in a reverse-numerical (descending) sequence; Muntz further explains that differing connector-port ordering (e.g., top-to-middle vs middle-to-bottom) drives the need for such ordering/mapping to avoid routing difficulties and wire crossings. Accordingly, Muntz provides explicit support for the amended recitation that a first order, according to which the second interconnects are successively arranged relative to each other, corresponds to an increasing order of respective levels of bit significance of the first signals as communicated with the first circuits; and a second order, according to which the third interconnects are successively arranged relative to each other, corresponds to a decreasing order of respective levels of bit significance of the second signals as communicated with the second circuits because discloses bitwise signals assigned to pins/ports where the ordered physical arrangement is associated with a logical order (ascending vs reverse/descending) selected to match the connector/stacking arrangement.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Muntz’s taught bitwise pin/port ordering and reverse-ordering correspondence into DeBaets’ planar interconnect routing arrangement (including alternating signals/reference conductors), in order to achieve predictable improvements in routing/stack integration -namely reducing wiring complexity and avoiding crossing/inefficient routing when two communication groups/interfaces must be accommodated with differing physical ordering constraints (e.g., due to mirroring/ stacking/connector ordering), as expressly motivated by Muntz, in column 5 lines 42-67.
Further, to the extend Applicant contends the “bit significate” correspondence language is purely functional, and states how the interconnects function sorting and prioritizing bits in an intended order. MEPE 2114 section II states that a claim containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus if the prior art apparatus teaches all the structural limitations of the claim. The patentability of apparatus depends on what a device is, not what a device does.
Re: Claim 3, DeBaets and Muntz disclose all the limitations of claim 1 on which this claim depends. DeBaets further discloses,
wherein the first interconnects comprise first swizzle circuit structures (Fig.3, first reference line 302A and the first signal 302B line form a twisted pair) and wherein the second interconnects comprise second swizzle circuit structures (Fig.3, second reference line 306A and the second signal 306B line form a twisted pair).
Re: Claim 4, DeBaets and Muntz disclose all the limitations of claim 1 on which this claim depends. DeBaets further teaches,
wherein the first circuits each comprise a respective transmit driver circuit, or each comprise a respective receiver circuit (Fig. 2, col. 5 lines 8-9, metal layer 208 comprises conductive traces for coupling input/output signals. These conductive traces necessarily serve as pathways for transmitting and receiving signals).
Re: Claim 5, DeBaets and Muntz disclose all the limitations of claim 4 on which this claim depends. DeBaets further teaches,
wherein the second circuits each comprise a respective transmit driver circuit, or each comprise a respective receiver circuit (Fig. 2, col. 5 lines 8-9, metal layer 208 comprises conductive traces for coupling input/output signals. These conductive traces necessarily serve as pathways for transmitting and receiving signals).
Re: Claim 6, DeBaets and Muntz disclose all the limitations of claim 1 on which this claim depends. DeBaets further teaches,
wherein each of the first circuits is to provide a respective data bit of the first communication, and wherein each of the second circuits is to provide a respective data bit of the second communication (col. 5 lines 8-9, metal layer 208 comprises conductive traces for coupling input/output signals. These conductive traces serve as signal pathways that transfer data between circuits, supporting communication in a structured manner).
Re: Claim 7, DeBaets and Muntz disclose all the limitations of claim 1 on which this claim depends. DeBaets further teaches,
wherein each of the first circuits is to provide a respective address bit of the first communication, and wherein each of the second circuits is to provide a respective address bit of the second communication (col. 5 lines 8-9, metal layer 208 comprises conductive traces for coupling input/output signals. These conductive traces facilitate structured signal transmission, including data and address communications between circuits).
Re: Claim 8, DeBaets and Muntz disclose all the limitations of claim 1 on which this claim depends. DeBaets further discloses,
wherein the first interconnects and the fourth interconnects are substantially aligned with each other in the plane (Fig 2 and Fig. 3, combination of second and third interconnects are aligned with fourth interconnect in the same plane 208).
Re: Claim 9, DeBaets and Muntz disclose all the limitations of claim 1 on which this claim depends.
DeBaets further teaches,
further comprising: fifth interconnects comprising sixth interconnects (first of metallization 216 of fig. 2 associated with 302B of fig. 3) which are each coupled to a different respective one of the first circuits, and seventh interconnects (second of metallization 216 associated with 306B) which are each coupled to a different respective one of the second circuits;
and eighth interconnects (first of metallization 216 of fig. 2 associated with 302A of fig. 3) which, within the IC die, are each electrically insulated from any transmit driver circuit and from any receiver circuit of the IC die (DeBaets fig. 3, 302A grounded and insulated from any signal lines);
wherein, in the plane and along a third direction (DeBaets fig. 2, direction in which metal layer 216 lies) orthogonal to the second line (DeBaets fig. 3, orthogonal to the signal line 302B):
the fifth interconnects are in an alternating arrangement with the eighth interconnects (Fig 2 and Fig. 3, combination of sixth and seventh interconnects are in alternating arrangement with eighth interconnect),
and the sixth interconnects and the seventh interconnects are on opposite sides of the second line (fig 2 and fig 3, signal line 302B is on one side of the plane and signal line 306B is on the other side of plane).
Further, the limitation “the sixth interconnects are successively arranged to correspond to successively greater levels of bit significance, and the seventh interconnects are successively arranged to correspond to successively lesser levels of bit significance” state how the interconnects function sorting and prioritizing bits in an intended order. MEPE 2114 section II states that a claim containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus if the prior art apparatus teaches all the structural limitations of the claim. The patentability of apparatus depends on what a device is, not what a device does.
Alternatively, even if the above “bit significant corresponds” recitations are treated as limiting, the applied evidence for the increasing/decreasing ordering correspondence is set forth in the rejection of amended claim 1 (which relies on Muntz for the order/correspondence feature), and therefore the limitation does not render claim 9 patentable
14. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over DeBaets (US 8759690 B1) in in view of Muntz (US 7924826 B1) further in view of Foster (US 20110109381 A1).
Re: Claim 2, DeBaets and Muntz disclose all the limitations of claim 1 on which this claim depends.
DeBaets and Muntz are silent regarding:
wherein an arrangement of the multiple interconnects relative to each other in a first plane proximate to a first one of the hardware interfaces is the same as an arrangement of the multiple interconnects relative to each other in a second plane proximate to a second one of the hardware interfaces.
However, Foster teaches wherein an arrangement of the multiple interconnects relative to each other in a first plane proximate to a first one of the hardware interfaces is the same as an arrangement of the multiple interconnects relative to each other in a second plane proximate to a second one of the hardware interfaces.
In Fig 1-2 and Figures 9-10, Foster discloses through-die conductive pathways PTVs 28 (pass through vias) that extend from the lower interface i.e. substrate 26 to the upper interface i.e., die stack 24. Because these vias traverse the die thickness, the in-plane layout of PTVs 28 / TSVs 30 / power 40 / common 42 is invariant near both opposite surfaces. Foster states in ¶ [0044] that the cross-section views appear exactly identical for stacked identical dies without rotation, specifying the same left/center/right ordering- PTVs 28(left), power/common 40/42 (center), TSVs 30(right) across the stack. This sameness necessarily holds for any first plane proximate the lower interface and any second plane proximate the upper interface of a given die, i.e., the arrangement is the same at both interfaces. Foster further explains that PTVs/TSV positions are rotationally symmetric and aligned upon rotation.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Foster’s teaching i.e., arrangement of interconnects in any plane near one surface of the die structure is the same as in any plane near the opposite surface to the structure of DeBaets in order to maintain a fixed, repeated layout across planes to substantially reduce bus signal lines loads when stacking multiple dies and support for faster bus speeds on the vias in the dies of a stack (Foster, ¶¶ [0059]-[0061]).
Conclusion
15. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 9:30am-6pm.
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898