DETAILED ACTION
This office action is in response to amendment filed 10/22/2025.
Claims 1-4, 8-9, 11-12 and 21-27 are pending. Claims 5-7, 10, 13-20 have been canceled. Claims 21-27 are new. Claims 1-2, 4, 8-9, and 11 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4, 21, 22, and 24-27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 4 reciting “within the second gate insulator, a ratio of a concentration of the second metal species to a concentration of the first metal species is less than 0.1” lacks adequate written description. Applicant’s original disclosure describes the second gate insulator having a concentration ratio of “between 0 and 0.1” (¶ 59). Applicant further describe the second metal species can be absent from the second gate insulator (¶ 58). Thus, indicating the range of “between 0 and 0.1” is intended to be inclusive of 0 (when M2 is absent) and 0.1. Specific exclusion of 0.1 is not specifically disclosed. As such, the newly claimed range of “less than 0.1” lacks full support. Applicant’s original disclosure does not specifically recite the concentration ratio in the second gate insulator is “less than 0.1”.
Claim 24 reciting limitations similar to claim 4 lacks adequate written description for similar reason.
Claims 21, 22 and 26 reciting “both the pass-gate and pull-up transistors have threshold voltages magnitudes that are below other NMOS transistors of an integrated circuit” lacks adequate written description.
Claim 25 reciting an NMOS pass-gate transistor comprising a first gate insulator, an NMOS pull-down transistors comprising a second gate insulator, and “the second gate insulator comprises the high-k gate material layer and an amount of the P-dipole dopant comprising second metal species that is more than the amount of the P-dipole dopant of the first gate insulator” lacks adequate written description. Applicant’s disclosure describes the P-dipole dopant having an effect of increasing the threshold voltage in NMOS (¶ 32). Applicant further the amount of P-dipole dopant in the first gate insulator 292 (of pass-gate transistor) is greater than an amount in the second gate insulator 291 (of pull-down transistor). See ¶ 32. On the contrary, claim 25 recites the amount of P-dipole dopant in the second gate insulator is more than the first gate insulator, in opposition to the disclosure. The concentration ratio as recited in claim 25 is not supported by Applicant’s original disclosure.
Other claims are rejected for depending on a rejected claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 8-9, 11-12 and 21-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “the first gate insulator comprises a high-k gate material layer comprising oxygen, a first metal species, and a dipole dopant comprising a second metal species” and “the second gate insulator comprises the high-k gate material layer and the dipole dopant comprising the second metal species” renders the claim indefinite because it is unclear what is require of the “high-k gate material layer”. In the limitation, “the first gate insulator comprises a high-k gate material layer comprising oxygen, a first metal species, and a dipole dopant comprising a second metal species”, the high-k gate material layer appear to be defined to include each of oxygen, a first metal species, and “a dipole dopant comprising a second metal species”. However, in the subsequent limitation “the second gate insulator comprises the high-k gate material layer and the dipole dopant comprising the second metal species”, the high-k gate material layer appear to be separate from “the dipole dopant comprising the second metal species”. Therefore, it is unclear what is required of the high-k gate material layer. Furthermore, it is unclear if the second gate insulator also comprise the oxygen and the first metal species.
Claim 4 reciting “within the first gate insulator, a ratio of a concentration of the second metal species to a concentration of the first metal species is between 0.1 and 0.2” and “within the second gate insulator, a ratio of a concentration of the second metal species to a concentration of the first metal species is less than 0.1” renders the claim indefinite. Claim 1 previously recite “an amount of the dipole dopant comprising the second metal species is greater in the second gate insulator than in the first gate insulator” which contradicts claim 4 reciting the second gate insulator having a concentration ratio of second metal species to first metal species that is less than 0.1 while the first gate insulator has a greater concentration ratio of between 0.1 and 0.2. Furthermore, it is unclear what is the intended scope of between 0.1 and 0.2. Applicant’s disclosure describes between 0 and 0.1 to be inclusive of 0 (M2 can be absent from gate insulator, ¶ 58-59). Therefore, in accordance to Applicant’s disclosure, “between 0.1 and 0.2” is meant to be inclusive of 0.1 and 0.2. However, amended claim 4 reciting the concentration ratio of “less than 0.1” originating from the disclosed “between 0 and 0.1” indicate “between” here is exclusive of 0.1. Therefore, the inconsistency between the original disclosure and claim amendments renders it unclear whether “between” is supposed to be inclusive or exclusive of the range end points.
Claim 24 reciting limitations similar to claim 4 is indefinite for similar reason.
Claim 9 reciting “the same composition” renders the claim due to lack of antecedent basis. It is unclear what is referred to by “the same composition”.
Claim 11 reciting “the second gate insulator comprises the high-k gate material layer and an amount of the N-dipole dopant comprising second metal species that is greater than the amount of the N-dipole dopant of the first gate insulator” renders the claim indefinite. Firstly, “the amount of the N-dipole dopant of the first gate insulator” lacks antecedent basis. Furthermore, “an amount of N-dipole dopant comprising second metal species” renders the claim indefinite due to lack of proper antecedent basis. It is unclear if “second metal species” here is the same as or different from previously recited “a second metal species”.
Claim 25 reciting “the second gate insulator comprises the high-k gate material layer and an amount of the P-dipole dopant comprising second metal species that is greater than the amount of the P-dipole dopant of the first gate insulator” renders the claim indefinite. Firstly, “the amount of the P-dipole dopant of the first gate insulator” lacks antecedent basis. Furthermore, “an amount of P-dipole dopant comprising second metal species” renders the claim indefinite due to lack of proper antecedent basis. It is unclear if “second metal species” here is the same as or different from previously recited “a second metal species”.
Claim 21 reciting “both the pass-gate and pull-up transistors have threshold voltages magnitudes that are below other NMOS transistors of an integrated circuit comprising the SRAM bit-cell structure” renders the claim indefinite. Firstly, “pull-up transistor” lacks antecedent basis. It is unclear what is referred to by the “pull-up transistor”. Furthermore, it is unclear what constitutes “other NMOS transistors of an integrated circuit” and whether they are structural parts of the claimed SRAM bit-cell structure. It is unclear how are the “other NMOS transistors of an integrated circuit” structurally related to the claimed SRAM bit-cell structure. Furthermore, in the event “other NMOS transistors of an integrated circuit” are not part of the SRAM bit-cell structure, it is unclear how do the “other NMOS transistors of an integrated circuit” further limit the claimed SRAM bit-cell structure.
Claims 22 and 26 reciting “both the pass-gate and pull-up transistors have threshold voltages magnitudes that are below other NMOS transistors of an integrated circuit comprising the SRAM array” renders the claim indefinite for reasons similar to claim 21 above.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9, 11, and 21-27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hong et al. US 2022/0077162 A1 (Hong).
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In re claim 1, as best understood, Hong discloses (e.g. FIGs. 1-7 & 15) a static random-access memory (SRAM) bit-cell structure (FIGs. 1 & 4), comprising:
a pass-gate transistor TA1 (¶ 26), comprising:
a first gate electrode GE1 around a channel region AP2 of a first stack of nanoribbons CH2; and
a first gate insulator GI1 (FIG. 6A) between the first gate electrode GE1 and the channel region AP2 of the first stack of nanoribbons CH2, wherein the first gate insulator GI1 comprises a high-k gate material layer HK (e.g. hafnium oxide, ¶ 84) comprising oxygen, a first metal species (e.g. hafnium, ¶ 84), and a dipole dopant comprising a second metal species (concentration of dipole element in GI1 may be lower than in GI2, ¶ 97; a difference in concentration between the dipole elements in TA1 and TD1, ¶ 98); and
a pull-down transistor TD1 (¶ 26) of a same conductivity type as the pass-gate transistor TA1 (e.g. both NMOS, ¶ 26), the second pull-down transistor TD1 comprising:
a second gate electrode GE2 around a channel region AP2 of a second stack of nanoribbons CH2; and
a second gate insulator GI2 (FIG. 6B) between the second gate electrode GE2 and the channel region AP2 of the second stack of nanoribbons CH2, wherein “the second gate insulator GI2 comprises the high-k gate material layer HK and the dipole dopant comprising the second metal species” (¶ 94), and wherein an amount of the dipole dopant comprising the second metal species is greater in the second gate insulator GI2 than in the first gate insulator GI1 (concentration of dipole element in GI1 may be lower than in GI2, ¶ 97; a difference in concentration between the dipole elements in TA1 and TD1, ¶ 98).
In re claim 2, Hong discloses (e.g. FIGs. 4 & 6) wherein:
the pass-gate and pull-down transistors TA1,TD1 are NMOS device structures (¶ 26); and
the dipole dopant is an N-dipole dopant (¶ 94-95, e.g. La as N-dipole dopant having an effect in lower the threshold voltage of NMOS).
In re claim 3, Hong discloses (e.g. FIGs. 4 & 6) wherein;
the first metal species (of HK hafnium oxide, ¶ 84) is a first of Hf, Al, Zr, or Y; and
the second metal species (¶ 94) is Mg, Ca, Sr, La, Sc, Ba, Gd, Er, Yb, Lu, Ga, Mo, Co, Ni, Nb, or a second of Hf, Al, Zr, or Y.
In re claim 4, as best understood, Hong discloses (e.g. FIGs. 6-7) wherein:
within “the first gate insulator” (GI2, as best understood), a ratio of a concentration of the second metal species to a concentration of the first metal species is “between 0.1 and 0.2” (¶ 120, e.g. 10% dopant; furthermore, as shown in FIG. 7, there exist a point in the continuous doping profile of the dipole element in GI2, as which point the ratio of concentration of the dipole element to the metal species of the HK is 0.1-0.2 or 10-20%); and
within “the second gate insulator” (GI1, as best understood), a ratio of a concentration of the second metal species to a concentration of the first metal species is less than 0.1 (¶ 97, “the highest concentration of the dipole element in the first gate insulating layer GI1 may be lower than the highest concentration of the dipole element in the second gate insulating layer GI2”).
Since the concentration ratio in GI2 is 10% or 0.1 (¶ 120), the concentration ratio in GI1 which is lower than in GI2 would be less than 0.1. Furthermore, there exist a point in the doping profile of the dipole element in GI1, as which point the ratio of concentration of the dipole element to the metal species of the HK is less than 0.1.
In re claim 9, as best understood, Hong discloses (e.g. FIGs. 4- 6 and 15) wherein:
the first stack of nanoribbons CH2 (of first transistor TA1) and the second stack of nanoribbons CH2 (of second transistor TD1) have the same composition (they are part of the same active pattern AP2);
the first gate electrode GE1 and the second gate electrode GE2 have the same composition (both having WF1,WF2 and EL, ¶ 93);
the first transistor TA1 has a first threshold voltage; and
the second transistor TD1 has a second threshold voltage, lower than the first threshold voltage (¶ 99).
In re claim 11, as best understood, Hong discloses a device comprising:
a microprocessor (blocks implemented as microprocessor, ¶ 166) comprising:
an arithmetic logic unit (device including logic element, ¶ 3; blocks implemented as logic gates, ¶ 166); and
a cache memory CE (FIG. 3) comprising an SRAM array, wherein the SRAM array comprises a plurality of bit-cells CE1-CE4 and each bit cell comprises (FIGs. 4-7 & 15):
an NMOS pass-gate transistor TA1 (¶ 26), comprising:
a first stack of nanoribbons CH2 (FIG. 15A);
a first gate electrode GE1 around a channel region AP2 of the first stack of nanoribbons CH2; and
a first gate insulator GI1 (FIG. 6A) between the first gate electrode GE1 and the channel region AP2 of the first stack of nanoribbons CH2, wherein the first gate insulator GI1 comprises a high-k gate material layer HK (e.g. hafnium oxide, ¶ 84) comprising oxygen, a first metal species (e.g. hafnium, ¶ 84), and an N-dipole dopant comprising a second metal species (no particular “P-dipole dopant” claimed that would distinguish over the various dipole element disclosed by Hong in ¶ 94; concentration of dipole element in GI1 may be lower than in GI2, ¶ 97; a difference in concentration between the dipole elements in TA1 and TD1, ¶ 98); and
an NMOS pull-down transistor TD1 (¶ 26), comprising:
a second stack of nanoribbons CH2;
a second gate electrode GE2 around a channel region AP2 of the second stack of nanoribbons CH2; and
a second gate insulator GI2 (FIG. 6B) between the second gate electrode GE2 and the channel region AP2 of the second stack of nanoribbons CH2, wherein the second gate insulator GI2 comprises the high-k gate material layer HK and “an amount of the N-dipole dopant comprising second metal species (¶ 94) that is greater than the amount of the N-dipole dopant of the first gate insulator” GI1 (concentration of dipole element in GI1 may be lower than in GI2, ¶ 97; a difference in concentration between the dipole elements in TA1 and TD1, ¶ 98); and
a power supply (supply power via power line VDD, FIGs. 1-2) coupled to power the microprocessor.
In re claim 21, as best understood, Hong discloses (e.g. FIGs. 4-7) wherein:
both the pass-gate TA1 and “pull-up transistors” (TD1, as best understood) have threshold voltages magnitudes that are below “other NMOS transistors of an integrated circuit comprising the SRAM bit-cell structure”. As best understood, Hong teaches pass-gate transistor TA and pull-down transistor TD containing different amounts of dipole elements that decreases the threshold voltage of the NMOS transistor (¶ 95-99). As such, TA1 and TD1 have lower threshold voltages magnitudes in comparison with “other NMOS transistors” not containing any dipole element. The “other NMOS transistors” are not required to be part of the claimed device as best understood. And the “other NMOS transistors” may be transistors containing P-dipole element which further increases threshold voltages of NMOS transistor. The “other NMOS transistors” may further be of different constructions such that higher threshold voltages are exhibited.
In re claim 22, as best understood, Hong discloses (e.g. FIGs. 4-7) wherein:
both the pass-gate TA1 and “pull-up transistors” (TD1, as best understood) have threshold voltages magnitudes that are below “other NMOS transistors of an integrated circuit comprising the SRAM array”. As best understood, Hong teaches pass-gate transistor TA and pull-down transistor TD containing different amounts of dipole elements that decreases the threshold voltage of the NMOS transistor (¶ 95-99). As such, TA1 and TD1 have lower threshold voltages magnitudes in comparison with “other NMOS transistors” not containing any dipole element. The “other NMOS transistors” are not required to be part of the claimed device as best understood. And the “other NMOS transistors” may be transistors containing P-dipole element which further increases threshold voltages of NMOS transistor. The “other NMOS transistors” may further be of different constructions such that higher threshold voltages are exhibited.
In re claim 23, Hong discloses (e.g. FIGs. 4 & 6) wherein;
the first metal species (of HK hafnium oxide, ¶ 84) is a first of Hf, Al, Zr, or Y; and
the second metal species (¶ 94) is Mg, Ca, Sr, La, Sc, Ba, Gd, Er, Yb, Lu, Ga, Mo, Co, Ni, Nb, or a second of Hf, Al, Zr, or Y.
In re claim 24, as best understood, Hong discloses (e.g. FIGs. 6-7) wherein:
within “the first gate insulator” (GI2, as best understood), a ratio of a concentration of the second metal species to a concentration of the first metal species is “between 0.1 and 0.2” (¶ 120, e.g. 10% dopant; furthermore, as shown in FIG. 7, there exist a point in the continuous doping profile of the dipole element in GI2, as which point the ratio of concentration of the dipole element to the metal species of the HK is 0.1-0.2 or 10-20%); and
within “the second gate insulator” (GI1, as best understood), a ratio of a concentration of the second metal species to a concentration of the first metal species is less than 0.1 (¶ 97, “the highest concentration of the dipole element in the first gate insulating layer GI1 may be lower than the highest concentration of the dipole element in the second gate insulating layer GI2”).
Since the concentration ratio in GI2 is 10% or 0.1 (¶ 120), the concentration ratio in GI1 which is lower than in GI2 would be less than 0.1. Furthermore, there exist a point in the doping profile of the dipole element in GI1, as which point the ratio of concentration of the dipole element to the metal species of the HK is less than 0.1.
In re claim 25, as best understood, Hong discloses a device comprising:
a microprocessor (blocks implemented as microprocessor, ¶ 166) comprising:
an arithmetic logic unit (device including logic element, ¶ 3; blocks implemented as logic gates, ¶ 166); and
a cache memory CE (FIG. 3) comprising an SRAM array, wherein the SRAM array comprises a plurality of bit-cells CE1-CE4 and each bit cell comprises (FIGs. 4-7 & 15):
an NMOS pass-gate transistor TA1 (¶ 26), comprising:
a first stack of nanoribbons CH2 (FIG. 15A);
a first gate electrode GE1 around a channel region AP2 of the first stack of nanoribbons CH2; and
a first gate insulator GI1 (FIG. 6A) between the first gate electrode GE1 and the channel region AP2 of the first stack of nanoribbons CH2, wherein the first gate insulator GI1 comprises a high-k gate material layer HK (e.g. hafnium oxide, ¶ 84) comprising oxygen, a first metal species (e.g. hafnium, ¶ 84), and a P-dipole dopant comprising a second metal species (no particular “P-dipole dopant” claimed that would distinguish over the various dipole element disclosed by Hong in ¶ 94; concentration of dipole element in GI1 may be lower than in GI2, ¶ 97; a difference in concentration between the dipole elements in TA1 and TD1, ¶ 98); and
an NMOS pull-down transistor TD1 (¶ 26), comprising:
a second stack of nanoribbons CH2;
a second gate electrode GE2 around a channel region AP2 of the second stack of nanoribbons CH2; and
a second gate insulator GI2 (FIG. 6B) between the second gate electrode GE2 and the channel region AP2 of the second stack of nanoribbons CH2, wherein the second gate insulator GI2 comprises the high-k gate material layer HK and “an amount of the P-dipole dopant comprising second metal species (¶ 94) that is more than the amount of the P-dipole dopant of the first gate insulator” GI1 (concentration of dipole element in GI1 may be lower than in GI2, ¶ 97; a difference in concentration between the dipole elements in TA1 and TD1, ¶ 98); and
a power supply (supply power via power line VDD, FIGs. 1-2) coupled to power the microprocessor.
In re claim 26, as best understood, Hong discloses (e.g. FIGs. 4-7) wherein:
both the pass-gate TA1 and “pull-up transistors” (TD1, as best understood) have threshold voltages magnitudes that are below “other NMOS transistors of an integrated circuit comprising the SRAM array”. As best understood, Hong teaches pass-gate transistor TA and pull-down transistor TD containing different amounts of dipole elements that decreases the threshold voltage of the NMOS transistor (¶ 95-99). As such, TA1 and TD1 have lower threshold voltages magnitudes in comparison with “other NMOS transistors” not containing any dipole element. The “other NMOS transistors” are not required to be part of the claimed device as best understood. And the “other NMOS transistors” may be transistors containing P-dipole element which further increases threshold voltages of NMOS transistor. The “other NMOS transistors” may further be of different constructions such that higher threshold voltages are exhibited.
In re claim 27, Hong discloses (e.g. FIGs. 4 & 6) wherein;
the first metal species (of HK hafnium oxide, ¶ 84) is a first of Hf, Al, Zr, or Y; and
the second metal species (¶ 94) is Al, Ga, Mo Co, Ni or Nb.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claim 1 above.
In re claim 8, Hong discloses (FIGs. 2, 4, 6 & 15, ¶ 26) wherein the SRAM bit-cell structure further comprises a pair of pull-up transistors TU1,TU2, and wherein each of the pull-up transistors TU1,TU2 further comprises:
a third stack of nanoribbons (FIG. 15B);
a third gate electrode GE2,GE3 around a channel region AP1 of the third stack of nanoribbons CH1; and
a third gate insulator GI2 (FIG. 6C) between the third gate electrode GE2,GE3 and the channel region AP1 of the third stack of nanoribbons CH1, wherein the third gate insulator GI2 comprises the high-k gate material layer HK and comprises the same amount of dipole dopant comprising the second metal species as the first gate insulator GI1 (¶ 112).
Hong teaches the amount of dipole element in third gate insulator layer of the pull-up transistor TU1 may be the same as the pass-gate transistor TA1, e.g. may both not contain dipole element so as to improve read operation of the SRAM cell (¶ 112). Hong further teaches the first gate insulator GI1 of pass-gate transistor TA1 may include the dipole element in concentration lower than the second gate insulator GI2 of the pull-down transistor TD1 (¶ 97).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a lower concentration of dipole element in both the gate insulators of the pass-gate transistor and pull-up transistor, and a higher concentration of dipole element in the pull-down transistor, such that the read operation of the SRAM cell can be improved as taught by Hong.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claim 11 above, and further in view of Sung et al. US 2020/0403081 A1 (Sung).
In re claim 12, Hong teaches the claimed device including power being supplied via the power line VDD. Hong does not explicitly disclose a battery is coupled to the power supply.
However, Sung discloses (FIG. 5) a battery 2418 coupled to the power supply to supply power to various components of a mobile device (¶ 57,83).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use battery as the power source of Hong’s device to enhance portability in a mobile device as taught by Sung.
Response to Arguments
Applicant's arguments filed 10/22/2025 have been fully considered but they are not persuasive.
Applicant argues Hong fails to teach non-zero doping of pass-gate transistor with the same dipole dopant as the pull-down transistor (Remark, pages 7-8).
This is not persuasive. Hong discloses exemplary embodiment where the pass-gate transistor TA1 “may not include the dipole element”. However, Hong also more generally discloses the concentration of dipole element in GI1 of the pass-gate transistor TA1 may be lower than in GI2 of the pull-down transistor TD1 (¶ 97). Furthermore, Hong discloses there exists a difference in concentration between the dipole elements in TA1 and TD1 (¶ 98). Therefore, the disclosure of Hong teaches the pass-gate transistor that include dipole element, but at a concentration that is “lower than” that in the pull-down gate transistor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896