DETAILED ACTION
Claims 1-30 are pending.
Claims 1-5, 8, 19-22, 25, and 30 have been elected and examined.
Claims 6-7, 9-18, 23-24, and 26-29 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings Inquiry
In original FIG.3, the examiner questions whether the connections between 306, 318, and 314 are illustrated correctly. As far as the examiner can tell from reading the specification, circuit 318 optimizes a loop stored in 312 and stores the optimized loop (308O) into 312. Thus, shouldn’t the bus between 306 and 318 be a bidirectional bus that allows instructions to flow in both directions between 306 and 318? If so, the examiner then questions the purpose of the output bus from 318 to 314? If the instructions are coming from 312, then the examiner is not clear on what is being sent by 318 to 314.
Should changes to FIG.3 be required, a corrected drawing sheet in compliance with 37 CFR 1.121(d) is required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Claim Interpretation
At least one claim is identified as including non-limiting contingent limitations. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding claim 20, if a loop optimization is unavailable and the captured loop is not to be replayed, then the method ends with the determining step. This is the broadest reasonable interpretation (BRI) of the claim. The examiner recommends replacing “if” with --that-- in line 11, and inserting --determining that the captured loop is to be replayed in the instruction pipeline;-- before “and” in line 16. This will cause all claimed steps to be required. Please propagate any change to dependent claims in appropriate fashion.
Regarding claim 21, if a loop optimization is unavailable, the method of claim 21, under BRI, does not include the modifying and inserting steps of the last two paragraphs.
Regarding claim 22, if a loop optimization is unavailable or at least one loop instruction cannot be transformed while maintaining the same function…, the method of claim 22, under BRI, does not include the modifying.
Regarding claim 25, if a loop optimization is unavailable or at least one loop instruction is not loop invariant to the captured loop, the method of claim 25, under BRI, does not include the transforming.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 22, and 25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 5, “the entry for the at least one instruction”. From claim 3, each loop instruction is stored in an entry, and there is no basis for a single entry storing more than one instruction.
In claim 22, “the modifying”, since there is a modifying step in claim 22 and another in claim 20.
Claim 25 is rejected due to its dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 19-22, 25, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Kanter, “Inside Nehalem: Intel’s Future Processor and System”, in view of Shwartsman (US 2017/0185407), Chilimbi et al. (US 2017/0192787), and Rappoport et al. (US 2016/0328172).
Referring to claim 1, Kanter has taught an out-of-order processor (p.5, lines 11-12) comprising:
an instruction processing circuit configured to process an instruction stream comprising a first plurality of instructions in an instruction pipeline (see p.4 and p.7 and note the Nehalem pipelined processing circuit);
the instruction processing circuit comprising:
an instruction fetch circuit (p.4, Nehalem’s “Instruction Fetch Unit”) configured to fetch the first plurality of instructions from an instruction memory (p.4, Nehalem’s instruction cache (I-cache));
an instruction decode circuit (p.4, Nehalem’s complex/simple decoders, which make up a decode circuit), in the instruction pipeline, configured to decode the first plurality of instructions into a plurality of decoded instructions (decoders decode instructions into decoded instructions (micro-ops));
a rename/allocate circuit (p.7, Nehalem’s register alias table and allocator), in the instruction pipeline, configured to perform register renaming to enable the plurality of decoded instructions to be executed (p.8, lines 3-5. The RAT, as known, renames registers for execution); and
an execution circuit (p.4, Nehalem’s ALUs, FMULs, FDIVs, BRANCH, etc.), in the instruction pipeline, configured to execute the plurality of decoded instructions out of order (again, see p.5, lines 11-12); and
a loop buffer circuit (p.4, Nehalem’s LSD buffer, which buffers loops (p.5, lines 11-13)) coupled directly to the instruction decode circuit (p.4, Nehalem’s LSD is coupled to the output of the decode circuit), the loop buffer circuit configured to:
receive copies of the plurality of decoded instructions as they flow through the instruction pipeline from the instruction decode circuit to the rename/allocate circuit (from p.4 and p.7, Nehalem’s LSD sits between the decode circuit and RAT/allocate circuit. As loop instructions are decoded and passed for renaming, the LSD stores the loop therein);
detect, in the instruction stream, a loop comprising a plurality of loop instructions among the plurality of decoded instructions (the LSD is a loop stream detector (p.2, last paragraph). A loop must be detected so that the LSD can store and feed the loop for renaming without involving fetch/decode again (p.5, lines 11-12));
in response to detection of the loop in the instruction stream:
capture the plurality of loop instructions of the detected loop as a captured loop directly from the instruction decode circuit (again, when a loop is detected, it is captured from the decoders, which are sending the instructions to the LSD); and
in response to determining the captured loop is to be replayed in the instruction
pipeline:
insert the loop after the instruction decode circuit and prior to the rename/allocate circuit in the instruction pipeline (again, see p.4 and p.7, where the LSD sits between decode and rename (RAT). Thus, when the LSD issues loop instructions, they are inserted after decode and before rename); and
discontinue fetching of the plurality of loop instructions of the captured loop (see p.5, lines 11-13. The loop instructions come directly from the LSD. The fetch and decode units are not used to obtain the loop instructions again).
Kanter has not taught that in response to detection of the loop in the instruction stream: in response to determining a loop optimization is available to be made for the captured loop, modify the captured loop to produce an optimized loop. However, Shwartsman has taught that an LSD (FIG.1, 104) prior to rename (FIG.1, 106), i.e., a similar configuration as in Kanter, can be used to determine when a loop can be optimized by eliminating loop-invariant instructions (abstract, FIG.2, paragraph 21, etc.). Further:
In a first rejection, the loop is modified through a training phase where instructions are marked for removal (paragraphs 21, 24, and 36-37). This generates an optimized loop, which in future iterations is sent to the RAT, which removes marked instructions (paragraph 37). Thus, an optimized/marked loop is sent to rename/RAT, where the removal will occur. In order to reduce the number of instructions to execute, which would speed up processing, reduce power, etc., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kanter to in response to detection of the loop in the instruction stream: in response to determining a loop optimization is available to be made for the captured loop, modify the captured loop to produce an optimized loop.
Alternatively, in a second rejection, Shwartsman does not actually teach the storage of an optimized loop (e.g. storing a version of the captured loop with fewer instructions). However, Chilimbi has taught such a concept, where a loop is detected, modified for optimization to generate an optimized loop, which is stored in an optimized cache (see FIG.4 and FIG.7, steps 704+), and then that optimized loop is what is fed into the pipeline (paragraphs 52 and 58). One of ordinary skill in the art would have recognized that storing the optimized loop in a buffer in Shwartsman would reduce the processing needed by the RAT to actually drop the instructions in each iteration. In other words, the RAT may be relieved of the redundant duty of removing the same instructions each iteration. Instead, the stored optimized loop would already have loop invariant instructions removed so that no instructions sent to RAT would need to be dropped. Thus, to implement optimization efficiently in Kanter, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kanter to in response to detection of the loop in the instruction stream: in response to determining a loop optimization is available to be made for the captured loop, modify the captured loop to produce an optimized loop, i.e., it would have been obvious to not only eliminate loop-invariant instructions, but also to store a version of the loop with no loop-invariant instructions so as to only send what is necessary to the rename stage); and
Kanter has also not explicitly taught in response to determining the captured loop is to be replayed in the instruction pipeline: send a loop replay indicator to the instruction fetch circuit to discontinue fetching of the plurality of loop instructions of the captured loop. However, Rappoport has taught powering down to the fetch unit (which requires sending it a signal) when the LSD is replaying loops (paragraph 62). Since the fetch unit is not needed to fetch instructions already in the LSD, one would be motivated to send the fetch unit it a signal to power it down and save power. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kanter to, in response to determining the captured loop is to be replayed in the instruction pipeline: send a loop replay indicator to the instruction fetch circuit to power the fetch unit down and discontinue fetching of the plurality of loop instructions of the captured loop.
Referring to claim 2, Kanter, as modified, has taught the out-of-order processor of claim 1, wherein the loop buffer circuit comprises:
a loop detection circuit configured to detect the loop in the instruction stream (as stated above, the detection is performed, and it is inherently performed by a loop detection circuit. That is, a processor performs the operation, and a processor is comprised of circuitry);
a loop capture circuit configured to capture the plurality of loop instructions of the detected loop as the captured loop (as stated above, since capturing is performed, a loop capture circuit exists to perform the capturing);
a loop optimization circuit configured to: determine if the loop optimization is available to be made for the captured loop, based on the captured loop; and in response to determining the loop optimization is available to be made for the captured loop, modify the captured loop to produce the optimized loop; and a loop replay circuit configured to, in response to determining the captured loop is to be replayed in the instruction pipeline, insert the optimized loop after the instruction decode circuit and prior to the execution circuit in the instruction pipeline (again, as stated above, these functions are performed, and, thus, there is a loop optimization circuit that performs the functions).
Referring to claim 3, Kanter, as modified, has taught the out-of-order processor of claim 1, further comprising a loop buffer memory (p.5, lines 11-14; the LSD has entries for 28 uops) comprising a plurality of instruction entries each configured to store a decoded instruction among the plurality of decoded instructions (to store 28 uops, there needs to be at least 28 entries);
wherein the loop buffer circuit is further configured to:
capture the plurality of loop instructions of the detected loop as the captured loop by being configured to:
store each loop instruction among the plurality of loop instructions in an instruction entry among the plurality of instructions entries in the loop buffer memory (again the LSD stores decoded uops);
determine if the loop optimization is available to be made for the captured loop by being configured to:
access the plurality of loop instructions for the captured loop in the plurality of instruction entries in the loop buffer memory; and determine, based on the accessed plurality of loop instructions for the captured loop in the plurality of instruction entries in the loop buffer memory, if the loop optimization is available to be made for the captured loop (based on the second rejection of claim 1, see FIG.4 of Chilimbi, where each instruction in a captured loop is analyzed to determine where an optimization can occur);
in response to determining the loop optimization is available to be made for the captured loop, modify at least one instruction entry among the plurality of instruction entries in the loop buffer memory for the captured loop to produce the optimized loop; and in response to determining the captured loop is to be replayed in the instruction pipeline, insert the optimized loop from the loop buffer memory into the instruction pipeline to be replayed (again, based on the 2nd rejection, this is the proposed combination. In Chilimbi, optimized loop code is stored and sent when a loop is to be replayed. In Kanter, the loop to be replayed is in the LSD. Thus, the combination teaches updated the LSD with optimized loop code to continue using the LSD to replay the loop).
Referring to claim 4, Kanter, as modified, has taught the out-of-order processor of claim 1, wherein the loop buffer circuit is further configured to: determine if the loop optimization is available to be made for the captured loop, based on the captured loop, by being configured to:
determine if at least one loop instruction among the plurality of loop instructions in the captured loop can be transformed while maintain the same function of the at least one loop instruction when executed (see FIG.4 of Chilimbi and the description thereof. Basically, the loop is optimized to perform the same function in a more efficient way); and
in response to determining the at least one loop instruction among the plurality of loop instructions in the captured loop can be transformed while maintaining the same function of the at least one loop instruction when executed, transform the at least one loop instruction among the plurality of loop instructions in the captured loop to produce the optimized loop (again, in the combination where an optimization can be performed, e.g. code can be eliminated, an instruction would be transformed to not occur).
Referring to claim 5, Kanter, as modified, has taught the out-of-order processor of claim 3, wherein the loop buffer optimization circuit is further configured to:
determine if the loop optimization is available to be made for the captured loop by being configured to determine if at least one loop instruction among the plurality of loop instructions in the captured loop can be transformed while maintaining the same function of the at least one loop instruction when executed (see FIG.4 and the description thereof. Basically, the loop is optimized to perform the same function in a more efficient way); and
in response to determining at least one loop instruction among the plurality of loop instructions in the captured loop can be transformed while maintaining the same function of the at least one loop instruction when executed, modify the entry for the at least one instruction among the plurality of instruction entries in the loop buffer memory to produce the optimized loop (again, in the combination, the loop in the LSD is updated with the optimized loop (transformed instruction(s))).
Referring to claim 8, Kanter, as modified, has taught the out-of-order processor of claim 4, wherein the loop buffer circuit is further configured to:
determine if the at least one loop instruction among the plurality of loop instructions in the captured loop can be transformed by being configured to determine if the at least one loop instruction among the plurality of loop instructions in the captured loop is loop invariant to the captured loop; and in response to determining the at least one loop instruction among the plurality of loop instructions in the captured loop is loop invariant to the captured loop, remove the at least one loop instruction among the plurality of loop instructions determined to be loop invariant from the captured loop to produce the optimized loop (again, this is the idea of the combination based on both Shwartsman and Chilimbi, who both remove loop-invariant instructions).
Referring to claim 19, Kanter, as modified, has taught the out-of-order processor of claim 1, further comprising an instruction cache configured to cache at least some of the first plurality of instructions from the instruction memory to increase a fetch speed of the instruction fetch circuit (p.4, Nehalem’s I-cache, where the purpose of instruction cache is to speed up fetching).
Claim 20 is rejected for similar reasoning as claim 1. Also, because claim 20 includes contingent limitations, claim 20 is alternatively rejected for similar reasoning as only a subset of reasoning in the rejection of claim 1.
Claim 21 is rejected for similar reasoning as claim 3 (or a subset thereof due to contingent limitations).
Claim 22 is rejected for similar reasoning as claim 4 (or a subset thereof due to contingent limitations).
Claim 25 is rejected for similar reasoning as claim 8 (or a subset thereof due to contingent limitations).
Claim 30 is mostly rejected for similar reasoning as claim 1. Note that Kanter, as modified, has taught non-transitory computer-readable medium (p.4, Nehalem’s I-cache) having stored thereon computer executable instructions which, when executed by an out-of-order processor, cause the out-of-order processor to replay an optimized loop based on a captured loop in an instruction pipeline in the out-of-order processor, by causing the out-of-order processor to perform the claimed functions (the instructions in I-cache, including the loop instructions, would cause all actions within the pipeline to occur, including those claimed).
---------------------------------------------------------------------------------------------------------------------
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20-22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chilimbi et al. (US 2017/0192787), in view of the examiner’s taking of Official Notice.
Referring to claim 20, Chilimbi has taught a method of replaying an optimized loop based on a captured loop in an instruction pipeline in a processor, comprising:
detecting in the instruction pipeline, a loop, in an instruction stream, comprising a plurality of loop instructions among a plurality of decoded instructions (FIG.7, 702; in order to detect if a loop is optimizable by 220 (FIG.2), a loop must be detected. In addition, the loop instructions are detected from instructions at the commit stage (paragraph [0072]), which is after decoding takes place in stage 204. Thus, the loop instructions are detected among decoded instructions of a fetched stream);
executing the plurality of decoded instructions in an execution circuit in the instruction pipeline (FIG.2, instructions are executed in stage 208 of the pipeline);
in response to detection of the loop in the instruction stream:
capturing a copy of the plurality of loop instructions of the detected loop as the captured loop directly from an instruction decode circuit in the instruction pipeline (by detecting the loop, it is captured for potential optimization. Note that 220 captures the loop from the commit stage 212. The decode circuit is interpreted to include at least 204, 206, 208, 210, and 212. Thus, instructions are captured directly from a decode circuit);
determining, based on the captured loop, if a loop optimization is available to be made for the captured loop (see FIG.7, 704);
Chilimbi has not taught that the processor is an out-of-order processor, nor that the execution circuit is configured to execute the plurality of instructions out of order. However, out-of-order processors and execution is well-known and accepted in the art. Out-of-order execution is used in most high-performance processors to make use of instruction cycles that would otherwise be wasted. Specifically, instructions that are ready to execute are allowed to execute even if a preceding instruction has not yet executed (for instance, due to a stall). This reduces reduced idle time and increased throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chilimbi such that the processor is an out-of-order processor, and that the execution circuit is configured to execute the plurality of instructions out of order. Applicant’s attention is directed to the Wikipedia entry for “Out-of-order execution” (not formally cited herein) for more information.
Note that all struck-through limitations are not required by the prior art because they are contingent steps that need not occur based on one or more conditions.
Referring to claim 21, Chilimbi, as modified, has taught the method of claim 20.
Chilimbi has not taught capturing the plurality of loop instructions of the detected loop as the captured loop comprises storing each loop instruction among the plurality of loop instructions in an instruction entry among a plurality of instructions entries in a loop buffer memory. That is, Chilimbi does not disclose that optimizer 220 has a buffer or that optimized 220 accesses instructions from a buffer. However, Official Notice is taken that buffering instructions, including those to be optimized, was well known in the art before applicant’s invention. Buffering the instructions allows the instructions to be stored while optimization occurs. This would allow Chilimbi to look for optimizations among non-adjacent instructions, thereby increasing optimization opportunity. If instructions are not buffered and they disappear after commit, this could prevent optimizations where they could have otherwise occurred. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chilimbi to either include a loop buffer memory in 220 or 212 (e.g. a reorder buffer used for out-of-order execution could be used) to capture a loop;
Chilimbi, as modified, has further taught determining if the loop optimization is available to be made based on the captured loop comprises:
accessing the plurality of loop instructions for the captured loop in the plurality of instruction entries in the loop buffer memory (again, optimizations would be looked for in buffered loop instructions); and
determining, based on the accessed plurality of loop instructions for the captured loop in the plurality of instruction entries in the loop buffer memory, if the loop optimization is available to be made for the captured loop (again, optimizations are looked for (FIG.7, 704)); and
Note that all struck-through limitations are not required by the prior art because they are contingent steps that need not occur based on one or more conditions.
Referring to claim 22, Chilimbi, as modified, has taught the method of claim 20, wherein:
determining if the loop optimization is available to be made for the captured loop, based on the captured loop, comprises:
determining if at least one loop instruction among the plurality of loop instructions in the captured loop can be transformed while maintaining the same function of the at least one loop instruction when executed (see FIG.4 and the description thereof. Basically, the loop is optimized to perform the same function in a more efficient way);
Note that all struck-through limitations are not required by the prior art because they are contingent steps that need not occur based on one or more conditions.
Referring to claim 25, Chilimbi has taught the method of claim 22, wherein:
determining if the at least one loop instruction among the plurality of loop instructions in the captured loop can be transformed comprises determining if the at least one loop instruction among the plurality of loop instructions in the captured loop is loop invariant to the captured loop (see FIG.4 and the description thereof);
Note that all struck-through limitations are not required by the prior art because they are contingent steps that need not occur based on one or more conditions.
Response to Arguments
On pages 21-22 of applicant’s response, applicant argues that the examiner’s interpretation of “instruction decode circuit” is unreasonably broad.
The examiner respectfully disagrees. The examiner’s interpretation is broad because “instruction decode circuit” is broad. At the extreme, a processor as a whole can be characterized as an instruction decode circuit because a processor is a circuit that decodes instructions for execution. Similarly, any portion of processor circuitry that includes a decoder is an instruction decode circuit.
On page 22 of applicant’s response, applicant inadequately traverses the examiner’s taking of Official Notice because applicant has not explained why the noticed features are not well-known in the art (MPEP 2144.03(C)). Thus, a supporting reference is not provided at this point in time. Out-of-order processing is ubiquitous in modern processor architectures, and the examiner does not see why inclusion of loop instructions would preclude its implementation in Chilimbi, as implied by applicant in the last paragraph of page 22.
Conclusion
The following prior art previously made of record and not relied upon is considered pertinent to applicant's disclosure:
Jackson, 2014/0047218, has taught capturing decoded instructions as they flow from decode stage 104 to rename stage 604 in a pipeline.
Hayenga has taught a pipeline with a decoded loop buffer (FIG.2).
Hiraki has taught a Stage-Skip Pipeline, in which a decoded instruction buffer stores decoded loops to save power by stopping fetching and decoding of loop instructions (e.g. see section III and FIG.2).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183