DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 08 January 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, and 9-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (U.S. Pub. 2018/0323199) in view of Lee et al. (U.S. Pub. 2019/0252386).
Claim 1: Roberts et al. discloses a semiconductor memory device in Figs. 1-5 and in paragraphs 2, 59, 61, 62, 64 and 67, comprising:
a memory cell array (10) including plural memory cells (19), each memory cell (19) including a capacitor (34) and a transistor (25) coupled to a word line (90y) and a bit line (56) vertically arranged in a direction (vertical direction in Fig. 5) perpendicular to a direction (horizontal direction in Fig. 5) of the word line (90y), the memory cell array (10) including a word line stack (stack of 90y) including word lines (90y) of different lateral lengths (lengths in the horizontal direction) vertically stacked; and
a plurality of second vias (97) individually formed on upper surfaces of the end portions of the word lines (90y) in the direction (vertical direction in Fig. 5) of the bit line (56).
Roberts et al. appears not to explicitly disclose a sub word line driver block including sub word lines which are coupled to the word lines of the word line stack and disposed below end portions of the word lines of the word line stack;
a plurality of first vias individually formed on upper surfaces of the sub word lines in a direction of the bit line; and
a plurality of metal wires individually disposed at higher level than the word lines and coupled to the word lines and the sub word lines through the first and second vias.
Lee et al., however, in Figs. 5 and 7B and in paragraphs 75, 80, 89 and 96-101, discloses a sub word line driver block (LML/LML2 and PER2) including sub word lines (LML/LML2) which are coupled to the word lines (WL) of the word line stack (stack of WLs) and disposed below end portions (end portions of WL) of the word lines (WL) of the word line stack (stack of WLs);
a plurality of first vias (CNT) individually formed on upper surfaces of the sub word lines (LML2) in a direction (vertical direction); and
a plurality of metal wires (ML5) individually disposed at higher level than the word lines (WL) and coupled to the word lines (WL) and the sub word lines (LML2) through the first and second vias (CNT and VI) in order to operate the memory cell array.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Roberts et al. with the disclosure of Lee et al. to have made a sub word line driver block including sub word lines which are coupled to the word lines of the word line stack and disposed below end portions of the word lines;
a plurality of first vias individually formed on upper surfaces of the sub word lines in a direction of the bit line; and
a plurality of metal wires individually disposed at higher level than the word lines and coupled to the word lines and the sub word lines through the first and second vias in order to connect the memory cell array to peripheral circuit that can read and write to the cells of the array to operate the memory cell array (paragraph 75 of Lee et al.).
Since Roberts et al. discloses the word line stack and Lee et al. discloses the sub word lines are below end portions of the word lines, Roberts et al. in view of Lee et al. would disclose a sub word line driver block including sub word lines disposed below end portions of the word lines of the word line stack.
Since Roberts et al. discloses a bit line vertically arranged and Lee et al. discloses the plurality of first vias individually formed in the vertical direction, Roberts et al. in view of Lee et al. would disclose a plurality of first vias individually formed on upper surfaces of the sub word lines in a direction of the bit line.
Claim 2: Since Roberts et al. discloses the word line stack and Lee et al. discloses the sub word lines are below end portions of the word lines, Roberts et al. in view of Lee et al. would disclose discloses the semiconductor memory device of claim 1, wherein the word line stack is disposed at a higher level than the sub word lines.
Claim 3: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 1, and, Roberts et al., in Fig. 5, further discloses wherein the end portion of the word line stack (stack of 90y) has a step structure.
Claim 5: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 1, and Lee et al., in Figs. 5 and 7B and in paragraphs 96-101, further discloses wherein the sub word line driver block (LML2 and PER2) includes a plurality of sub word line drivers (sub-word line drivers) for controlling the word lines (WL), and the sub word line drivers (sub-word line drivers) are connected to the sub word lines (LML2), respectively.
Since Roberts et al. discloses the word line stack, Roberts et al. in view of Lee et al. would disclose the plurality of sub word line drivers for controlling the word lines of the word line stack.
Claim 6: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 5, and Roberts et al., in Fig. 5, further discloses
wherein the word line stack (stack of 90y) includes a lower-level word line stack (the two lower 90y) and an upper-level word line stack (the two upper 90y), and
wherein the lower-level word line stack (the two lower 90y) and the upper-level word line stack (the two upper 90y) are connected to different second vias (97).
Since Lee et al., in Figs. 5 and 7B, discloses the second vias (VI) are connected (connected through LML2 and CNT to PER2) to different groups of sub word line drivers (sub-word line drivers), Roberts et al. in view of Lee et al. would disclose wherein the lower-level word line stack and the upper-level word line stack are connected to different groups of the sub word line drivers.
Claim 9: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 1, and Lee et al., in Fig. 7B, discloses wherein the word lines (WL) and the sub word lines (LML2) of the word line stack are connected to each other through interconnections (ML5).
Claim 10: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 1, Roberts et al., in Fig. 1 and in paragraph 61, further discloses wherein each of the memory cells includes:
a laterally oriented active layer (20, 22 and 24) having one side coupled to the bit line (56); and
the capacitor (34) connected to another side of the laterally oriented active layer (20, 22 and 24).
Claim 11: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 10, Roberts et al., in Fig. 3 and in paragraph 65, further discloses wherein the capacitor (capacitor 34, which comprises 46, 48 and 50) includes a cylinder-type storage node (48).
Claim 12: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 10, Roberts et al., in Fig. 1 and in paragraph 61, further discloses wherein the laterally oriented active layer (20, 22 and 24) includes a thin-body channel (24) having a smaller thickness (thickness of 24 smaller than thickness of 90y on the left ends) than each of the word lines (90y).
Claim 13: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 12, Roberts et al., in Fig. 4 and in paragraph 61, further discloses the word lines (90y) include a double word line in which two word lines (90y above and below 24) face each other with the thin-body channel (24) interposed therebetween.
Claim 14: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 12, Roberts et al., in paragraph 61, further discloses wherein the thin-body channel (24) includes a semiconductor material or an oxide semiconductor material.
Claim 15: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 12, Roberts et al., in paragraph 61, further discloses wherein the thin-body channel (24) includes polysilicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide)
Claim 16: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 10, and Roberts et al., in paragraphs 4, 61 and 65, discloses the memory cells 19 individually comprise a transistor 25 and a capacitor 25, wherein the capacitor insulator 50 is silicon dioxide, and if the capacitor insulator includes only silicon dioxide, the memory would be volatile memory. Therefore, Roberts et al. would disclose the memory cells are Dynamic Random-Access Memory (DRAM) cells.
Claim 17: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 1, and Lee et al., in Fig. 7B, further discloses wherein the sub word lines (LML2) and the metal wires (ML5) extend along a same direction (D2).
Claim 18: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 1, and Lee et al., in Figs. 5 and 7AB further discloses wherein the word lines (WL) and the sub word lines (LML2) individually extend in directions (D3 and D1, respectively) crossing each other.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. in view of Lee et al. as applied to claim 1 above, and further in view of U.S. Pub. 2011/0176375, hereinafter referred to as ‘375.
Claim 4: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 1, and Lee et al., in Fig. 7B and in paragraph 78, further discloses the sub word line block (LML2 and PER2) includes transistors (peripheral transistors), wherein the transistors are disposed at a lower level than the sub word lines (LML2).
Roberts et al. in view of Lee et al. appears not to explicitly disclose wherein the sub word line driver block includes a plurality of p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) and a plurality of n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), the plurality of PMOSFETs and the plurality of NMOSFETs being connected to the sub word lines, and
wherein the PMOSFETs and the NMOSFETs are disposed at a lower level than the sub word lines.
‘375, however, in Figs. 2 and 4 and in paragraph 55, discloses the sub word line driver block (SWD) includes a plurality of p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) (410) and a plurality of n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) (450), the plurality of PMOSFETs (410) and the plurality of NMOSFETs (450) being connected to the sub word lines (line connecting SWD to WL).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of ‘375 that is in the same field of endeavor with Roberts et al. in view of Lee et al., before the effective filing date of the claimed invention in order to substitute the sub word line driver block including a plurality of p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) and a plurality of n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), the plurality of PMOSFETs and the plurality of NMOSFETs being connected to the sub word lines as disclosed by ‘375 for the configuration of the sub word line driver block disclosed by Roberts et al. in view of Lee et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the sub word line driver block including a plurality of p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) and a plurality of n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), the plurality of PMOSFETs and the plurality of NMOSFETs being connected to the sub word lines disclosed by ‘375 for the configuration of the sub word line driver block disclosed by Roberts et al. in view of Lee et al. would have yielded predictable results, namely providing driving the memory cells of the memory array. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Roberts et al. in view of Lee et al. in view of ‘375 would therefore disclose the sub word line driver block includes a plurality of p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) and a plurality of n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), the plurality of PMOSFETs and the plurality of NMOSFETs being connected to the sub word lines, and
wherein the PMOSFETs and the NMOSFETs are disposed at a lower level than the sub word lines.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. in view of Lee et al. as applied to claim 6 above, and further in view of Yun et al. (U.S. Pub. 2015/0117079).
Claims 7 and 8: Roberts et al. in view of Lee et al. discloses the semiconductor memory device of claim 6, and Lee et al., in Figs. 5 and 7B and in paragraphs 34 and 78, further discloses wherein the different groups of the sub word line drivers (transistors respectively connected to the different LML2) include a first group of the sub word line drivers (transistors connected to the right WLs) and a second group of the sub word line drivers (transistors connected to the left WLs).
Roberts et al. in view of Lee et al. appears not to explicitly disclose
wherein the first group of the sub word line drivers and the second group of the sub word line drivers share different main word lines, and
wherein the main word lines have a bended shape.
Yun et al., however, in Fig. 5 and in paragraphs 3 and 46, discloses
the first group of the sub word line drivers (top two 235) and the second group of the sub word line drivers (third and fourth 235 from the top) share different main word lines (240a and 242b), and
the main word lines (240a and 242b) have a bended shape in order to selectively activate one of a plurality of sub word lines.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Roberts et al. in view of Lee et al. with the disclosure of Yun et al. to have made the first group of the sub word line drivers and the second group of the sub word line drivers share different main word lines, and the main word lines have a bended shape in order to selectively activate one of a plurality of sub word lines (paragraph 3 of Yun et al.).
Response to Arguments
Applicant's arguments filed 08 January 2026 have been fully considered but they are not persuasive.
Applicant contends Roberts et al. and Lee et al. does fails to disclose “a sub word line driver block including sub word lines of the word line stack and disposed below end portions of the word lines of the word line stack” as recited in claim 1.
Examiner notes that Fig. 7B of Lee et al. is an alternate embodiment of the cross-sectional view taken along line C-C’ of Fig. 5. In the alternate embodiment of Fig. 7B, LML of Fig. 5 is LML2. In Fig. 5, Lee et al. shows LML and PER2 electrically connected to CNT, VI and ML5 and ML5 is electrically connected to VI and CL2 (WL). Fig. 7B of Lee et al. shows ML5 electrically connected to VI and CL2 (WL) and LML2 disposed under end portions of CL2 (WL). Lee et al., in Figs. 5 and 7B, would therefore disclose “a sub word line driver block including sub word lines of the word line stack and disposed below end portions of the word lines of the word line stack.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.L/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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