CTFR 17/561,518 CTFR 98866 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-06 AIA Claim s 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and/or species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/9/2025 . Information Disclosure Statement 06-52 AIA The information disclosure statement (IDS) submitted on 12/29/2025 was filed after the mailing date of the Non-Final Rejection on 07/08/2025 . The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Arguments Applicant’s amendments, see page 8, filed 10/06/2025, with respect to claims 3 and 12 have been fully considered. The claim objections of claims 3 and 12 has been withdrawn. Applicant’s amendments, see page 8, filed 10/06/2025, with respect to claims 1 and 10 have been fully considered and are persuasive. The 112 rejection of claims 1-16 has been withdrawn. 07-38-02 Applicant’s arguments, see pages 8-12 , filed 10/06/2025, with respect to the rejection(s) of claim(s) 1-16 under 102 and 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ko et al. (US 20200006557 A1). Claim Rejections - 35 USC § 103 07-103 AIA The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. 07-21-aia AIA Claim s 1-4 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 10121882 B1) in view of Ko et al. (US 20200006557 A1) . Regarding Claim 1 , Ho teaches an integrated circuit structure (col. 1, “Technical Field”), comprising: a substrate layer (Fig. 21A, 2104, Fig. 23A, 2304); an epitaxial layer coupled to the substrate layer (Fig. 21A, 2112, 2132); a fin trim isolation (FTI) plug (Fig. 23B, 2308D-G) comprising a compressive film (2350) that exerts a compressive strain (per col. 36, lines 28-31), a gate spacer layer (Fig. 21C, 2140) in between the FTI plug and the epitaxial layer. Ho does not disclose: a conductive contact structure on the epitaxial layer, the conductive contact structure having a top surface at a same level as a top surface of the FTI plug. However, Ko discloses: a conductive contact structure (80) on the epitaxial layer (42), the conductive contact structure having a top surface at a same level as a top surface of the FTI plug (66). ([0048], [0051], Fig. 13) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Ho and Ko for a conductive contact structure on the epitaxial layer, the conductive contact structure having a top surface at a same level as a top surface of the FTI plug so that “ the stresses are not only reduced, they also become more uniform.” (Ko, [0052]) Regarding Claim 2 , Ho teaches the integrated circuit structure of claim 1 (as stated above), wherein the compressive film (Fig. 23B, 2350) of the FTI plug (2308D-G) is to exert the compressive strain outward from the FTI plug (col. 36, lines 28-31, “As described above, it is to be appreciated that poly plug stress effects can benefit both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress)”). Regarding Claim 3 , Ho teaches the integrated circuit structure of claim 1 (as stated above), wherein the compressive film comprises: SiGe , SiO, SiN, or AlN (Fig. 21C, 2140, col. 32, lines 65-67, material liner including SiN formed within fin end stressor plug openings, Fig. 21K, 2152, col. 33, lines 34-36, fill material including SiO is formed in plug openings). Regarding Claim 4 , Ho teaches the integrated circuit structure of claim 1 (as stated above), wherein the integrated circuit structure comprises a non-planar transistor (col. 15, lines 6-9 “Processes may involve selectively doping sub-fin regions of tri-gate or finFET transistors fabricated on bulk silicon wafers”). Regarding Claim 10 , Ho teaches an integrated circuit structure (col. 1, “Technical Field”), comprising: a substrate layer (Fig. 21A, 2104, Fig. 23A, 2304); a first epitaxial layer coupled to the substrate layer (Fig. 21A, 2112, 2132); a second epitaxial layer coupled to the substrate layer (2112, 2132); a first fin trim isolation (FTI) plug (Fig.’s 22A-D) comprising a compressive film (Fig. 21B, col. 32, lines 60-63, that exerts a compressive strain “openings 2116 and 2136 . . . [where] fin end stressor dielectric plugs may be formed.”, Fig. 23B, 2308D-G, col. 36, lines 28-31, plug stress effects can benefit PMOS transistors through compressive channel stress); a second FTI plug (Fig.’s 22A-D) comprising the compressive film (Fig. 21B, col. 32, lines 60-63, “openings 2116 and 2136 . . . [where] fin end stressor dielectric plugs may be formed.”, Fig. 23B, 2308D-G, col. 36, lines 28-31, plug stress effects can benefit PMOS transistors through compressive channel stress); and a silicon channel between the first epitaxial layer and the second epitaxial layer (Fig. 21A, silicon fins 2102, 2122 each have active gate electrode locations 2108, 2128 between first and second epitaxial layers 2112, 2132. The portions of fins 2102, 2122 coupled to the active gate electrodes and between the epitaxial layers 2112, 2132 each constitute a channel.), wherein the first epitaxial layer is between the first FTI plug and the silicon channel (a first 2112 is between a first plug location 2116 and a first end of the portion of 2102 that constitutes the channel), and wherein the second epitaxial layer is between the second FTI plug and the silicon channel (a second 2112 is between a second plug location 2116 and a second end of the portion of 2102 that constitutes the channel). Ho does not disclose: a first conductive contact structure on the first epitaxial layer, the first conductive contact structure having a top surface at a same level as a top surface of the first FTI plug; and a second conductive contact structure on the second epitaxial layer, the second conductive contact structure having a top surface at a same level as a top surface of the second FTI plug. However, Ko discloses: a first conductive contact structure (80 left) on the first epitaxial layer (42 left), the first conductive contact structure having a top surface at a same level as a top surface of the first FTI plug (66 left); (Fig. 13) and a second conductive contact structure (80 right) on the second epitaxial layer (42 right in Fig. 5B), the second conductive contact structure having a top surface at a same level as a top surface of the second FTI plug (see additional 66 in Fig. 12D). ([0048], Fig. 12D and 13) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Ho and Ko for a first conductive contact structure on the first epitaxial layer, the first conductive contact structure having a top surface at a same level as a top surface of the first FTI plug; and a second conductive contact structure on the second epitaxial layer, the second conductive contact structure having a top surface at a same level as a top surface of the second FTI plug so that “ the stresses are not only reduced, they also become more uniform.” (Ko, [0052]) Regarding Claim 11 , Ho teaches the integrated circuit structure of claim 10 (as stated above), wherein the compressive film (Fig. 23B, 2350) of the first FTI plug (2308D-G) and the second FTI plug (2308D-G) is to exert a respective compressive strain outward from the respective FTI plugs (col. 36, lines 28-31, “As described above, it is to be appreciated that poly plug stress effects can benefit both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress)”). Regarding Claim 12 , Ho teaches the integrated circuit structure of claim 10 (as stated above), wherein the compressive film comprises: SiGE, SiO, SiN, or AlN (Fig. 21C, 2140, col. 32, lines 65-67, material liner including SiN formed within fin end stressor plug openings, Fig. 21K, 2152, col. 33, lines 34-36, fill material including SiO is formed in plug openings) . 07-22-aia AIA Claim s 5-9 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 10121882 B1) in view of Ko et al. (US 20200006557 A1) as applied to claim s 1 and 10 above, and further in view of Su et al. (US 20210376076 A1) . Regarding Claim 5 : the integrated circuit structure of claim 4, wherein the non-planar transistor is a fin field-effect transistor, a forksheet transistor, or a gate-all-around (GAA) transistor. Ho teaches the integrated circuit structure of claim 4 (as stated above), wherein the non-planar transistor is a fin field-effect transistor (col. 15, lines 6-9) . . . or a gate-all-around (GAA) transistor (col. 23, lines 25-29, “gate electrode that wraps around. . . all sides of the fin. . .”). Ho does not teach the non-planar transistor is . . . a forksheet transistor. However, Su teaches the non-planar transistor is . . . a forksheet transistor (Fig. 1, [0011] “the nano-FETs are forksheet FETs”) and that “forksheet FETs allow n-type devices and p-type devices to be formed close to one another, and allow the gate structures 120 to be physically and electrically coupled to one another, thereby reducing the amount of gate contacts used in a CMOS process” ([0014]). While designing an integrated circuit structure comprising a non-planar transistor one could reference Ho and arrive at the integrated circuit structure of Claim 4. Then, motivated by the desire to scale to smaller features and increase densities of functional units, one could reference and incorporate Su’s teachings on forksheet FETs which allow n-and-p-type devices to be formed close to one another. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Ho, incorporating teachings from Su, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 6 : the integrated circuit structure of claim 5, wherein the integrated circuit structure further comprises a silicon channel coupled to the epitaxial layer. Ho and Su teach the integrated circuit structure of claim 5 (as stated above), wherein the integrated circuit structure further comprises a silicon channel (Ho, Fig. 21A, a portion of first silicon fin 2102 constitutes the channel portion of the gate structure) coupled to the epitaxial layer (2112 coupled to 2102). Further, an integrated circuit structure comprising a non-planar transistor with a silicon channel coupled to an epitaxial layer is common in the art. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su and knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 7 : the integrated circuit structure of claim 6, wherein the non-planar transistor is a forksheet transistor or a GAA transistor, and wherein the integrated circuit structure further comprises a workfunction metal coupled to the silicon channel. Ho and Su teach the integrated circuit structure of claim 6 (as stated above), wherein the non-planar transistor is a forksheet transistor (stated above – see “Regarding claim 5”) or a GAA transistor (stated above – see “Regarding claim 5”), and wherein the integrated circuit structure further comprises a workfunction metal (Ho, Fig. 31A, 3102B, col. 45, lines 53-56, “conductive layer 3102B includes a metal and may be . . . a workfunction layer”) coupled to the silicon channel (Fig. 31A, 3106). Further, an integrated circuit structure comprising a non-planar transistor with a workfunction metal coupled to a silicon channel is common in the art. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su and knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 8 : the integrated circuit structure of claim 7, further comprising a high-k dielectric material coupled to the workfunction metal. Ho and Su teach the integrated circuit structure of claim 7 (as stated above), further comprising a high-k dielectric material (Ho, Fig. 31A, 3103) coupled to the workfunction metal (3103 coupled to 3102B). Further, a high-k dielectric material coupled to a workfunction metal is a common design for gate structures in the art. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su and knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 9 : the integrated circuit structure of claim 8, wherein the high-k dielectric material comprises: H f O 2 , Z r O 2 , or T i O 2 . Ho and Su teach the integrated circuit structure of claim 8 (as stated above), wherein the high-k dielectric material comprises: H f O 2 , Z r O 2 , or T i O 2 (Ho, col. 80, lines 46-58, gate dielectric layer composed of high-k material such as but not limited to hafnium oxide, zirconium oxide). Further, T i O 2 is a high-k material known to the art as an effective gate dielectric. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su and knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 13 : the integrated circuit structure of claim 10, wherein the integrated circuit structure comprises a non-planar transistor that is a fin field-effect transistor (FinFET), a forksheet transistor, or a gate-all-around (GAA) transistor. Ho teaches the integrated circuit structure of claim 10 (as stated above), wherein the integrated circuit structure comprises a non-planar transistor that is a fin field-effect transistor (FinFET) (col. 15, lines 6-9) . . . or a gate-all-around (GAA) transistor (col. 23, lines 25-29, “gate electrode that wraps around. . . all sides of the fin. . .”). Ho does not teach the non-planar transistor is . . . a forksheet transistor. However, Su teaches the non-planar transistor is . . . a forksheet transistor (Fig. 1, [0011] “the nano-FETs are forksheet FETs”) and that “forksheet FETs allow n-type devices and p-type devices to be formed close to one another, and allow the gate structures 120 to be physically and electrically coupled to one another, thereby reducing the amount of gate contacts used in a CMOS process” ([0014]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 14 : the integrated circuit structure of claim 13, wherein the non-planar transistor is a GAA or forksheet transistor, and wherein the integrated circuit structure further comprises a workfunction metal coupled to the silicon channel. Ho and Su teach the integrated circuit structure of claim 13 (as stated above), wherein the non-planar transistor is a GAA (Ho, col. 23, lines 25-29, “gate electrode that wraps around. . . all sides of the fin. . .”). or forksheet transistor (Su, Fig. 1, [0011] “the nano-FETs are forksheet FETs”), and wherein the integrated circuit structure further comprises a workfunction metal (Ho, Fig. 31A, 3102B, col. 45, lines 53-56, “conductive layer 3102B includes a metal and may be . . . a workfunction layer”) coupled to the silicon channel (Fig. 31A, 3106). Further, an integrated circuit structure comprising a non-planar transistor with a workfunction metal coupled to a silicon channel is common in the art. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su and knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 15 : the integrated circuit structure of claim 14, further comprising a high-k dielectric material coupled to the workfunction metal. Ho and Su teach the integrated circuit structure of claim 14 (as stated above), further comprising a high-k dielectric material (Ho, Fig. 31A, 3103) coupled to the workfunction metal (3103 coupled to 3102B). Further, a high-k dielectric material coupled to a workfunction metal is a common design for gate structures in the art. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su and knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05. Regarding Claim 16 : the integrated circuit structure of claim 15, wherein the high-k dielectric material comprises: H f O 2 , Z r O 2 , or T i O 2 . Ho and Su teach the integrated circuit structure of claim 15 (as stated above), wherein the high-k dielectric material comprises: H f O 2 , Z r O 2 , or T i O 2 (Ho, col. 80, lines 46-58, gate dielectric layer composed of high-k material such as but not limited to hafnium oxide, zirconium oxide). Further, T i O 2 is a high-k material known to the art as an effective gate dielectric. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention motivated by the above reasoning to reference Ho, then incorporate teachings from Su and knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yin et al. (US 20130146977 A1) discloses “when the stress of the insulating plug is adjusted, for example, the PMOS device has a tensile stress and the NMOS device has a compressive stress, the stress of the insulating plug acts upon the semiconductor base, and an opposite stress can be produced in the semiconductor base, that is, a compressive stress can be produced in the semiconductor base of the PMOS device, and a tensile stress can be produced in the semiconductor base of the NMOS device. The opposite stress generated within the semiconductor base can be used to further regulate the stress in the channel region of the device resulting in improvement in carrier mobility in the channel region” in [0015] but does not disclose all the limitations as required by the claims . Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jesse Goss whose telephone number is (571) 272-5170. The examiner can normally be reached M-F 830-600. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 17/561,518 Page 2 Art Unit: 2897 Application/Control Number: 17/561,518 Page 3 Art Unit: 2897 Application/Control Number: 17/561,518 Page 4 Art Unit: 2897 Application/Control Number: 17/561,518 Page 5 Art Unit: 2897 Application/Control Number: 17/561,518 Page 6 Art Unit: 2897 Application/Control Number: 17/561,518 Page 7 Art Unit: 2897 Application/Control Number: 17/561,518 Page 8 Art Unit: 2897 Application/Control Number: 17/561,518 Page 9 Art Unit: 2897 Application/Control Number: 17/561,518 Page 10 Art Unit: 2897 Application/Control Number: 17/561,518 Page 11 Art Unit: 2897 Application/Control Number: 17/561,518 Page 12 Art Unit: 2897
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