DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1 – 20 are pending. Claims 1, 13, and 18 were amended. Claims 16 and 17 were withdrawn.
Response to Arguments
Applicant’s amendments and arguments have been considered but are moot in view of the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-15, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20210104475A1 to Radhakrishnan et al. (hereinafter “Radhakrishnan”) in view of US20090117325A1 to Gardner et al. (hereinafter “Gardner”).
RE: Claim 1, Radhakrishnan discloses An electronic package (300, [0051], FIG. 3), comprising:
a substrate (302; alternatively, 250 shown in FIG. 2F and the portion of 302 in FIG. 3 that would be to the left and right of 205 and 270 shown in FIG. 2F; magnetic inductors 350 in FIG. 3 are substantially similar to inductors 200 in FIGs. 2A-2F, [0052]; Accordingly, 200 is in 302), wherein the substrate comprises glass (302 is a PCB made of glass epoxy base, [0054]);
a via opening (262 in FIG. 2B for inductor 200 and/or opening defined by outermost left 270 in FIG. 2F) through a thickness of the substrate;
a first layer (left 205 in FIG. 2D, [0040]; alternatively, leftmost portion of left 205 in FIG. 2D) over sidewalls (sidewalls of 250 which define 262 and/or sidewalls of 270 which define an opening therein; the word “over” is not defined in the instant specification; the word “over” has been defined as “used as a function word to indicate position on or motion to the other side or beyond,” see definition 5a for the preposition over provided by Merriam-Webster available at https://www.merriam-webster.com/dictionary/over, accessed on Sept. 24, 2025; accordingly, under a broad reasonable interpretation, left 205 is over sidewalls of 250 and/or sidewalls of 270 since left 205 is on sidewalls of 250 and/or sidewalls of 270) of the via opening, wherein the first layer comprises a magnetic material (205 are magnetic interconnects, [0040]) having a sidewall;
a second layer (left 270 in FIG. 2F; alternatively, outermost left 270 in FIG. 2F) over the first layer, wherein the second layer is an insulator (insulating layer 270 may be disposed over and around the magnetic interconnects 205 and the substrate layer 250, [0045]); and
a third layer (240 in FIG. 2F) that fills the via opening, wherein the third layer is a conductor having a vertical sidewall laterally spaced apart from the sidewall of the first layer (240 includes conductive material, [0048]; via openings 264-265 may expose the inner sidewalls of the insulating layer 270 within the openings 206, [0046]; insulating layer 270 may have inner portions located within the openings 206 of the magnetic interconnects 205, where the inner portions of the insulating layer 270 may be directly coupled and surrounded with the inner sidewalls of the openings 206 of the magnetic interconnects 205, [0047], see FIG. 2E; accordingly, in FIG. 2F, the vertical sidewall of 240 is laterally spaced apart from the sidewall of 205 by 270).
Radhakrishnan does not explicitly disclose the sidewall of the magnetic material is a tapered sidewall.
However, in the same field of endeavor, Gardner discloses The magnetic via 110 structure/shape may be optimized to obtain good inductance within an inductive structure, such as the inductive structure 116 of FIG. 1 e for example, according to a particular application. In another embodiment (referring to FIG. 1 f), the magnetic via 110 of the inductive structure 116 may be formed to comprise a tapered sidewall 111, [0021].
Gardner further discloses Tapering and/or beveling the magnetic via sidewalls may improve the magnetic properties of the magnetic material because the properties in the horizontal direction tend to be better than those in the vertical direction. This is because the magnetic domains are not disrupted when they extend into the magnetic via region when there is a more gradual slope. [0022].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the magnetic interconnects 205 with a tapered sidewall as taught by Gardner to improve the magnetic properties of the magnetic interconnects 205 and to prevent the disruption of magnetic domains therein.
RE: Claim 2, Radhakrishnan discloses The electronic package of claim 1, further comprising:
a seed layer between the first layer and the sidewalls of the via opening (the conductive layers 210-211 and/or the PTH vias 240-241 may be initially disposed as a seed layer(s), [0049]; accordingly, a seed layer would be positioned between the left 205 and the sidewalls of the opening defined by 250).
RE: Claim 4, modified Radhakrishnan discloses The electronic package of claim 1, further comprising:
a seed layer between the second layer and the third layer (the conductive layers 210-211 and/or the PTH vias 240-241 may be initially disposed as a seed layer(s), [0049]; accordingly, a seed layer would be positioned between the left 270 and 240).
RE: Claim 5, modified Radhakrishnan discloses The electronic package of claim 1, wherein a diameter of the via opening is approximately 150µm or smaller (The magnetic interconnects 205 with the openings 206 is substantially similar to the magnetic interconnects 105 with the openings 106 described above in FIGS. 1A-1C, [0044]; the magnetic interconnect 105 has a diameter (or an outer diameter, an overall diameter, a total width, etc.) (“B”) of approximately 55 um to 1.21 mm, [0025]; accordingly, 205 would also have an outer diameter of approximately 55 um to 1.21 mm such as 55 um; since the outermost layer of 270 is in contact with the outer diameter of 205, the opening defined by the outermost layer of 270 would have substantially the same diameter, i.e., 55 um; here, “um” is considered a unit for micrometers or microns).
RE: Claim 6, modified Radhakrishnan discloses The electronic package of claim 1, wherein a thickness of the first layer is approximately 10µm or smaller (The magnetic interconnects 205 with the openings 206 is substantially similar to the magnetic interconnects 105 with the openings 106 described above in FIGS. 1A-1C, [0044]; the magnetic interconnect 105 may have a width (“C”) of approximately 500 um or less, [0025], FIG. 1B; accordingly, 205 would also have a width / thickness of approximately 500 um or less such as 10 um; here, “um” is considered a unit for micrometers or microns).
RE: Claim 7, modified Radhakrishnan discloses The electronic package of claim 1, further comprising:
a second via opening (263 in FIG. 2B for inductor 200 and/or opening defined by outermost layer of right 270 in FIG. 2F) through the thickness of the substrate;
a fourth layer (right 205 in FIG. 2F, [0040]) over sidewalls of the second via opening, wherein the fourth layer comprises a magnetic material (205 are magnetic interconnects, [0040]);
a fifth layer (right 270 in FIG. 2F, [0046], FIG. 2E; a plurality of via openings 264-265 may be patterned (or drilled) through portions of the insulating layer 270, where such patterned/drilled portions of the insulating layer 270 may be positioned (or located) within the openings 206 of the magnetic interconnects 205, [0046]) over the fourth layer, wherein the fifth layer is an insulator; and
a sixth layer (241 in FIG. 2F, [0048]; 241 includes conductive material, [0048]) that fills the second via opening, wherein the sixth layer is a conductor.
RE: Claim 8, modified Radhakrishnan discloses The electronic package of claim 7, wherein the sixth layer is electrically coupled to the third layer by a trace (210 or 211, [0040]) over a surface of the substrate (240 is electrically coupled to 241 by capacitance between 210, 211, 270).
RE: Claim 9, modified Radhakrishnan discloses The electronic package of claim 1, further comprising:
a fourth layer (portion of left 205 to the right of 240 in FIG. 2F, [0040]) between the first layer and the sidewalls of the via opening, wherein the fourth layer comprises a magnetic material (205 are magnetic interconnects, [0040]); and
a fifth layer between the fourth layer and the first layer, wherein the fifth layer is an insulator (As modified, a portion of 270 is inside space defined by 205; accordingly, the portion of 270 inside space defined by 205 is between leftmost portion of left 205 and the portion of left 205 to the right of 240).
RE: Claim 10, modified Radhakrishnan discloses The electronic package of claim 1, wherein the first layer and the second layer extend over a top surface and a bottom surface of the substrate (When 200 is rotated slightly counterclockwise, the far left 205 and far left 270 would extend over to cover the top side surface of 250 and the bottom side surface of 250 in FIG. 2E-2F).
RE: Claim 11, modified Radhakrishnan discloses The electronic package of claim 10, further comprising:
an insulating layer (As discussed above, the portion of 270 inside 205) over an end of the first layer and the second layer on the top surface and a bottom surface of the substrate (When 200 is rotated slightly counterclockwise, the portion of 270 inside 205 would extend over the end of the far left 205 and the end of the far left outermost 270 in FIG. 2F which extend over a top side surface and bottom side surface of 250).
RE: Claim 12, modified Radhakrishnan discloses The electronic package of claim 1, further comprising:
a buildup layer (layer of 302 in FIG. 3 that would be above 250 shown in FIG. 2F) over a top surface of the substrate (the layer of 302 would be over a top surface of 250);
a pad (the PTH vias 240-241 and the conductive layers 210-211 may be substantially similar to the PTH vias 140-141 and the conductive layers 110-111 described above in FIG. 1A, [0049]; the PCB may include a plurality of conductive layers (e.g., the PTH vias 140-141, the conductive layers 110-111, etc.), which may further include copper (or metallic) traces, lines, pads, vias, via pads, holes, and/or planes, [0028]; accordingly, 210 includes pads and vias; a pad of 210 would correspond to the claimed pad) on the buildup layer above the third layer; and
a via (a via of 210, as discussed above) through the buildup layer to electrically couple the pad to the third layer (FIG. 2F shows 210 electrically coupled to 240).
RE: Claim 13, Radhakrishnan discloses An electronic package (300, [0051], FIG. 3), comprising:
a substrate (250 shown in FIG. 2F and the portion of 302 in FIG. 3 that would be to the left and right of 205 and 270 shown in FIG. 2F; magnetic inductors 350 in FIG. 3 are substantially similar to inductors 200 in FIGs. 2A-2F, [0052]; Accordingly, 200 is in 302);
a first inductor (350, [0051]) through a thickness of the substrate;
a second inductor (package substrate 302 includes one or more magnetic inductors 350, [0051]; a second inductor 350 would be one magnetic inductor more than one magnetic inductor 350) through the thickness of the substrate; wherein each of the first inductor and the second inductor comprise:
a via opening (262 in FIG. 2B for inductor 200 and/or opening defined by outermost left 270 in FIG. 2F) through a thickness of the substrate;
a first layer (left 205 in FIG. 2D, [0040]; alternatively, leftmost portion of left 205 in FIG. 2D) over sidewalls (sidewalls of 250 which define 262 and/or sidewalls of 270 which define an opening therein; the word “over” is not defined in the instant specification; the word “over” has been defined as “used as a function word to indicate position on or motion to the other side or beyond,” see definition 5a for the preposition over provided by Merriam-Webster available at https://www.merriam-webster.com/dictionary/over, accessed on Sept. 24, 2025; accordingly, under a broad reasonable interpretation, left 205 is over sidewalls of 250 and/or sidewalls of 270 since left 205 is on sidewalls of 250 and/or sidewalls of 270) of the via opening, wherein the first layer comprises a magnetic material (205 are magnetic interconnects, [0040]) having a sidewall;
a second layer (left 270 in FIG. 2F; alternatively, outermost left 270 in FIG. 2F) over the first layer, wherein the second layer is an insulator (insulating layer 270 may be disposed over and around the magnetic interconnects 205 and the substrate layer 250, [0045]);
and a third layer (240 in FIG. 2F) over the second layer, wherein the third layer is a conductor having a vertical sidewall laterally spaced apart from the sidewall of the first layer (240 includes conductive material, [0048]; via openings 264-265 may expose the inner sidewalls of the insulating layer 270 within the openings 206, [0046]; insulating layer 270 may have inner portions located within the openings 206 of the magnetic interconnects 205, where the inner portions of the insulating layer 270 may be directly coupled and surrounded with the inner sidewalls of the openings 206 of the magnetic interconnects 205, [0047], see FIG. 2E; accordingly, in FIG. 2F, the vertical sidewall of 240 is laterally spaced apart from the sidewall of 205 by 270);
first buildup layers (portions of 302 in FIG. 3 that would be over 250 shown in FIG. 2F; also 316 in FIG. 3, [0055]) over the substrate; and
second buildup layers (portions of 302 in FIG. 3 that would be under 250 shown in FIG. 2F; also 320 in FIG. 3, [0055]) under the substrate.
Radhakrishnan does not explicitly disclose the sidewall of the magnetic material is a tapered sidewall.
However, in the same field of endeavor, Gardner discloses The magnetic via 110 structure/shape may be optimized to obtain good inductance within an inductive structure, such as the inductive structure 116 of FIG. 1 e for example, according to a particular application. In another embodiment (referring to FIG. 1 f), the magnetic via 110 of the inductive structure 116 may be formed to comprise a tapered sidewall 111, [0021].
Gardner further discloses Tapering and/or beveling the magnetic via sidewalls may improve the magnetic properties of the magnetic material because the properties in the horizontal direction tend to be better than those in the vertical direction. This is because the magnetic domains are not disrupted when they extend into the magnetic via region when there is a more gradual slope. [0022].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the magnetic interconnects 205 with a tapered sidewall as taught by Gardner to improve the magnetic properties of the magnetic interconnects 205 and to prevent the disruption of magnetic domains therein.
RE: Claim 14, modified Radhakrishnan discloses The electronic package of claim 13, wherein the third layer of the first inductor is coupled to the third layer of the second inductor by a trace (210 or 211, [0040]) in the first buildup layers or the second buildup layers (As modified, 240, 241 from one inductor 200 would be coupled to the 240, 241 from the other inductor 200 by 210, 211).
RE: Claim 15, modified Radhakrishnan The electronic package of claim 13, wherein the substrate is a glass substrate (The substrate layer 250 may be substantially similar to the substrate layer 150, [0042]; the substrate layer 150 may include one or more materials such as epoxy, glass (or glass fibers), and/or the like, [0029]; the package substrate 302 is a PCB. For one embodiment, the PCB is made of an FR-4 glass epoxy base, [0054]).
RE: Claim 18, Radhakrishnan discloses An electronic system (300, [0051], FIG. 3), comprising:
a board (312, [0051]);
a package substrate (302, [0051]) coupled to the board, wherein the package substrate comprises:
a substrate (portion of 302 to the left and to the right of 250 and including 250 as discussed below, excluding the portions of 302 above and below 250, [0040],[0051]);
a first inductor (350, [0051]) through a thickness of the substrate;
a second inductor (package substrate 302 includes one or more magnetic inductors 350, [0051]; a second inductor 350 would be one magnetic inductor more than one magnetic inductor 350) through the thickness of the substrate; wherein each of the first inductor and the second inductor comprise:
a via opening (262 in FIG. 2B for inductor 200 and/or opening defined by outermost left 270 in FIG. 2F) through a thickness of the substrate;
a first layer (left 205 in FIG. 2D, [0040]; alternatively, leftmost portion of left 205 in FIG. 2D) over sidewalls (sidewalls of 250 which define 262 and/or sidewalls of 270 which define an opening therein; the word “over” is not defined in the instant specification; the word “over” has been defined as “used as a function word to indicate position on or motion to the other side or beyond,” see definition 5a for the preposition over provided by Merriam-Webster available at https://www.merriam-webster.com/dictionary/over, accessed on Sept. 24, 2025; accordingly, under a broad reasonable interpretation, left 205 is over sidewalls of 250 and/or sidewalls of 270 since left 205 is on sidewalls of 250 and/or sidewalls of 270) of the via opening, wherein the first layer comprises a magnetic material (205 are magnetic interconnects, [0040]) having a sidewall;
a second layer (left 270 in FIG. 2F; alternatively, outermost left 270 in FIG. 2F) over the first layer, wherein the second layer is an insulator (insulating layer 270 may be disposed over and around the magnetic interconnects 205 and the substrate layer 250, [0045]); and
a third layer (240 in FIG. 2F) over the second layer, wherein the third layer is a conductor having a vertical sidewall laterally spaced apart from the sidewall of the first layer (240 includes conductive material, [0048]; via openings 264-265 may expose the inner sidewalls of the insulating layer 270 within the openings 206, [0046]; insulating layer 270 may have inner portions located within the openings 206 of the magnetic interconnects 205, where the inner portions of the insulating layer 270 may be directly coupled and surrounded with the inner sidewalls of the openings 206 of the magnetic interconnects 205, [0047], see FIG. 2E; accordingly, in FIG. 2F, the vertical sidewall of 240 is laterally spaced apart from the sidewall of 205 by 270);
first buildup layers (portions of 302 in FIG. 3 over 250 in FIG. 2F; also 316 in FIG. 3, [0055]) over the substrate; and
second buildup layers (portions of 302 in FIG. 3 under 250 in FIG. 2F; also 320 in FIG. 3, [0055]) under the substrate; and
a die (314 in FIG. 3, [0051]) coupled to the package substrate.
Radhakrishnan does not explicitly disclose the sidewall of the magnetic material is a tapered sidewall.
However, in the same field of endeavor, Gardner discloses The magnetic via 110 structure/shape may be optimized to obtain good inductance within an inductive structure, such as the inductive structure 116 of FIG. 1 e for example, according to a particular application. In another embodiment (referring to FIG. 1 f), the magnetic via 110 of the inductive structure 116 may be formed to comprise a tapered sidewall 111, [0021].
Gardner further discloses Tapering and/or beveling the magnetic via sidewalls may improve the magnetic properties of the magnetic material because the properties in the horizontal direction tend to be better than those in the vertical direction. This is because the magnetic domains are not disrupted when they extend into the magnetic via region when there is a more gradual slope. [0022].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the magnetic interconnects 205 with a tapered sidewall as taught by Gardner to improve the magnetic properties of the magnetic interconnects 205 and to prevent the disruption of magnetic domains therein.
RE: Claim 19, modified Radhakrishnan discloses The electronic system of claim 18, wherein the substrate comprises glass or an organic glass fiber woven core (The substrate layer 250 may be substantially similar to the substrate layer 150, [0042]; the substrate layer 150 may include one or more materials such as epoxy, glass (or glass fibers), and/or the like, [0029]; the package substrate 302 is a PCB. For one embodiment, the PCB is made of an FR-4 glass epoxy base, [0054]).
RE: Claim 20, modified Radhakrishnan discloses The electronic system of claim 18, wherein the third layer of the first inductor is coupled to the third layer of the second inductor by a trace (210 or 211, [0040]) in the first buildup layers or the second buildup layers (As modified, 240, 241 from one inductor 200 would be coupled to the 240, 241 from the other inductor 200 by 210, 211).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radhakrishnan and Gardner as applied to claim 2, and further in view of US 20210159160 A1 to Chen et al. (hereinafter “Chen”).
RE: Claim 3, modified Radhakrishnan does not explicitly disclose The electronic package of claim 2, further comprising:
an adhesion layer between the seed layer and the sidewalls of the via opening.
However, in a similar field of endeavor, Chen discloses The seed layer 142 may be formed on the adhesion layer 140 or directly on the sidewalls of the through-assembly vias 113, [0054], FIG. 1B. In FIG. 1B, the adhesion layer 140 is formed around the seed layer 142.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the seed layer on an adhesion layer with the adhesion layer being formed around the seed layer as taught by Chen to improve the adhesion of the seed layer of 240. As a result, portions of the adhesion layer would be between portions of the seed layer and sidewalls defined by 250.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899