Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/22/2026 has been entered.
Claim Rejections Withdrawal
Applicant’s amendment of Claims 6 and 16 is acknowledged. Thus, the rejection under 112 is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 11-13, 15-18 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. Patent Pub. No. 2021/0375853) of record, in view of Shue (U.S. Patent Pub. No. 2022/0285292) of record, in view of Xie (U.S. Patent No. 9,754,923) of record.
Regarding Claim 1
FIG. 1 of Chen discloses an integrated circuit structure, comprising: a first die (T1) comprising a first device layer (113) and a first plurality of metallization layers (MD_1, VD_1) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (T2) comprising a second device layer (114) and a second plurality of metallization layers (MD_2, VD_2) over the second device layer, the second device layer comprising a second plurality of integrated circuit devices (stacked); a signal line coupling the first die and the second die at a first side of the first and second dies, the signal line (M0_1) continuous over the first device layer and the second device layer and a backside power rail (BM0_1 [0040]) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail has a longest dimension along a same direction as a longest dimension of the signal line, and wherein the first device layer and the second device layer are vertically between the backside power rail and the signal line.
Chen is silent with respect to “the second die separated from the second die by a scribe region” and “the backside power rail extends laterally beyond an end of the signal line along the direction”.
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Shue. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue).
Chen as modified by Shue is silent with respect to “the backside power rail extends laterally beyond an end of the signal line along the direction”.
FIG. 4 of Xie discloses a similar integrated circuit structure, comprising a signal line (M5) coupling the first die and the second die at a first side of the first and second dies (106), the signal line continuous over the first device layer and the second device layer and a backside power rail (108) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail extends laterally beyond an end of the signal line along the direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Xie. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of minimizing power loss (Abstract of Xie).
Regarding Claim 2
FIG. 1 of Shue discloses the signal line (108I) is coupled to the first plurality of metallization layers (124z) of the first die by a first via stack of the first die, and the signal line is coupled to the second plurality of metallization layers of the second die by a second via stack of the second die.
Regarding Claim 3
FIG. 4 of Xie discloses the backside power rail (108) is coupled to the first device layer of first die by a first backside via structure, and the backside power rail is coupled to second device layer of the second die by a second backside via structure.
Regarding Claim 4
FIG. 1 of Shue discloses the first device layer and the second device layer are both logic device layers, or are both SRAM device layers [0018].
Regarding Claim 5
FIG. 1 of Shue discloses the first device layer is a logic device layer, and the second device layer is an SRAM device layer [0018].
.
Regarding Claim 6
FIG. 1 of Chen discloses an integrated circuit structure, comprising: a first die (T1) comprising a first device layer (113) and a first plurality of metallization layers (MD_1, VD_1) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (T2) comprising a second device layer (114) and a second plurality of metallization layers (MD_2, VD_2) over the second device layer, the second device layer comprising a second plurality of integrated circuit devices (stacked); a front side power rail (M0_1) coupling the first die and the second die at a first side of the first and second dies, the front side power rail continuous over the first device layer and the second device layer; and a backside power rail (BM0_1 [0040]) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail has a longest dimension along a same direction as a longest dimension of the signal line, and wherein the first device layer and the second device layer are vertically between the backside power rail and the front side power rail.
Chen is silent with respect to “the second die separated from the second die by a scribe region” and “the backside power rail extends laterally beyond an end of the front side power rail along the direction”.
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Shue. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue).
Chen as modified by Shue is silent with respect to “the backside power rail extends laterally beyond an end of the front side power rail along the direction”.
FIG. 4 of Xie discloses a similar integrated circuit structure, comprising a front side power rail (M6) coupling the first die and the second die at a first side of the first and second dies (106), the signal line continuous over the first device layer and the second device layer and a backside power rail (108) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail extends laterally beyond an end of the front side power rail along the direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Xie. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of minimizing power loss (Abstract of Xie).
Regarding Claim 11
FIG. 1 of Chen discloses a board [0107]; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first die (T1) comprising a first device layer (113) and a first plurality of metallization layers (MD_1, VD_1) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (T2) comprising a second device layer (114) and a second plurality of metallization layers (MD_2, VD_2) over the second device layer, the second device layer comprising a second plurality of integrated circuit devices (stacked); a signal line coupling the first die and the second die at a first side of the first and second dies, the signal line (M0_1) continuous over the first device layer and the second device layer and a backside power rail (BM0_1 [0040]) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail has a longest dimension along a same direction as a longest dimension of the signal line, and wherein the first device layer and the second device layer are vertically between the backside power rail and the signal line.
Chen is silent with respect to “the second die separated from the second die by a scribe region” and “the backside power rail extends laterally beyond an end of the signal line along the direction”.
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Shue. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue).
Chen as modified by Shue is silent with respect to “the backside power rail extends laterally beyond an end of the signal line along the direction”.
FIG. 4 of Xie discloses a similar integrated circuit structure, comprising a signal line (M5) coupling the first die and the second die at a first side of the first and second dies (106), the signal line continuous over the first device layer and the second device layer and a backside power rail (108) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail extends laterally beyond an end of the signal line along the direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Xie. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of minimizing power loss (Abstract of Xie).
The preamble “computing device” is a statement of intended use and is not considered to be of significance to claim construction, see MPEP 2111.02 II. During examination, statements in the preamble reciting the purpose or intended use of the claimed invention must be evaluated to determine whether the recited purpose or intended use results in a structural difference (or, in the case of process claims, manipulative difference) between the claimed invention and the prior art. If so, the recitation serves to limit the claim. See, e.g., In re Otto, 312 F.2d 937, 938, 136 USPQ 458, 459 (CCPA 1963). MPEP 2111.02. Since Shue discloses a substantially identical structure of Claim 18, the recitation “computing device” is treated as the purpose or intended use of the claimed invention.
Regarding Claim 12
FIG. 1 of Shue discloses a memory coupled to the board [0018].
Regarding Claim 13
FIG. 5 of Shue discloses a communication chip coupled to the board [0070].
Regarding Claim 15
FIG. 5 of Shue discloses the component is a packaged integrated circuit die [0004].
Regarding Claim 16
FIG. 1 of Chen discloses a board [0107]; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first die (T1); a second die (T2); a signal line (M0_1) coupling the first die and the second die at a first side of the first and second dies; a front side power rail (VSS) coupling the first die and the second die at a first side of the first and second dies; and a backside power rail (VDD) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, wherein the first device layer and the second device layer are vertically between the backside power rail and the signal line.
Chen is silent with respect to “a first die comprising a first device layer and a first plurality of metallization layers over the first device layer; a second die comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region” and “the backside power rail extends laterally beyond an end of the front side power rail along the direction”.
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Shue. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue).
Chen as modified by Shue is silent with respect to “the backside power rail extends laterally beyond an end of the front side power rail along the direction”.
FIG. 4 of Xie discloses a similar integrated circuit structure, comprising a front side power rail (M6) coupling the first die and the second die at a first side of the first and second dies (106), the signal line continuous over the first device layer and the second device layer and a backside power rail (108) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail extends laterally beyond an end of the front side power rail along the direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Xie. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of minimizing power loss (Abstract of Xie).
The preamble “computing device” is a statement of intended use and is not considered to be of significance to claim construction, see MPEP 2111.02 II. During examination, statements in the preamble reciting the purpose or intended use of the claimed invention must be evaluated to determine whether the recited purpose or intended use results in a structural difference (or, in the case of process claims, manipulative difference) between the claimed invention and the prior art. If so, the recitation serves to limit the claim. See, e.g., In re Otto, 312 F.2d 937, 938, 136 USPQ 458, 459 (CCPA 1963). MPEP 2111.02. Since Shue discloses a substantially identical structure of Claim 18, the recitation “computing device” is treated as the purpose or intended use of the claimed invention.
Regarding Claim 17
FIG. 1 of Shue discloses a memory coupled to the board [0018].
Regarding Claim 18
FIG. 5 of Shue discloses a communication chip coupled to the board [0070].
Regarding Claim 20
FIG. 5 of Shue discloses the component is a packaged integrated circuit die [0004].
Claims 1, 6, 11 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Rubin (U.S. Patent Pub. No. 2020/0135646) of record, in view of Shue.
Regarding Claim 1
FIG. 1 of Rubin discloses an integrated circuit structure, comprising: a first die (left) comprising a first device layer (left 118) and a first plurality of metallization layers (left BEOL) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (right) comprising a second device layer (right 118) and a second plurality of metallization layers (right BEOL) over the second device layer [0036], the second device layer comprising a second plurality of integrated circuit devices (stacked); a signal line (M1) coupling the first die and the second die at a first side of the first and second dies, the front side power rail continuous over the first device layer and the second device layer; and a backside power rail (102 [0036]) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail has a longest dimension along a same direction as a longest dimension of the signal line, and wherein the first device layer and the second device layer are vertically between the backside power rail and the front side power rail, wherein the backside power rail extends laterally beyond an end of the signal line along the direction.
Rubin is silent with respect to “the second die separated from the second die by a scribe region”.
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rubin, as taught by Shue. The ordinary artisan would have been motivated to modify Rubin in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue).
Regarding Claim 6
FIG. 1 of Rubin discloses an integrated circuit structure, comprising: a first die (left) comprising a first device layer (left 118) and a first plurality of metallization layers (left BEOL) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (right) comprising a second device layer (right 118) and a second plurality of metallization layers (right BEOL) over the second device layer [0036], the second device layer comprising a second plurality of integrated circuit devices (stacked); a front side power rail (M2) coupling the first die and the second die at a first side of the first and second dies, the front side power rail continuous over the first device layer and the second device layer; and a backside power rail (102 [0036]) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail has a longest dimension along a same direction as a longest dimension of the signal line, and wherein the first device layer and the second device layer are vertically between the backside power rail and the front side power rail, wherein the backside power rail extends laterally beyond an end of the front side power rail along the direction.
Rubin is silent with respect to “the second die separated from the second die by a scribe region”.
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rubin, as taught by Shue. The ordinary artisan would have been motivated to modify Rubin in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue).
Regarding Claim 11
FIG. 1 of Rubin discloses a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first die (left) comprising a first device layer (left 118) and a first plurality of metallization layers (left BEOL) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (right) comprising a second device layer (right 118) and a second plurality of metallization layers (right BEOL) over the second device layer [0036], the second device layer comprising a second plurality of integrated circuit devices (stacked); a signal line (M1) coupling the first die and the second die at a first side of the first and second dies, the signal line continuous over the first device layer and the second device layer and a backside power rail (102 [0036]) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail has a longest dimension along a same direction as a longest dimension of the signal line, and wherein the first device layer and the second device layer are vertically between the backside power rail and the signal line, wherein the backside power rail extends laterally beyond an end of the signal line along the direction.
Rubin is silent with respect to “the second die separated from the second die by a scribe region”.
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rubin, as taught by Shue. The ordinary artisan would have been motivated to modify Rubin in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue). The preamble “computing device” is a statement of intended use and is not considered to be of significance to claim construction, see MPEP 2111.02 II. During examination, statements in the preamble reciting the purpose or intended use of the claimed invention must be evaluated to determine whether the recited purpose or intended use results in a structural difference (or, in the case of process claims, manipulative difference) between the claimed invention and the prior art. If so, the recitation serves to limit the claim. See, e.g., In re Otto, 312 F.2d 937, 938, 136 USPQ 458, 459 (CCPA 1963). MPEP 2111.02. Since Shue discloses a substantially identical structure of Claim 18, the recitation “computing device” is treated as the purpose or intended use of the claimed invention.
Regarding Claim 16
FIG. 1 of Rubin discloses a computing device [0093], comprising: a board (100); and a component coupled to the board, the component including an integrated circuit structure, comprising: a first die (left) comprising a first device layer (left 118) and a first plurality of metallization layers (left BEOL) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (right) comprising a second device layer (right 118) and a second plurality of metallization layers (right BEOL) over the second device layer, the second device layer comprising a second plurality of integrated circuit devices (stacked); a front side power rail (M2) coupling the first die and the second die at a first side of the first and second dies, the front side power rail continuous over the first device layer and the second device layer; and a backside power rail (102) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the backside power rail has a longest dimension along a same direction as a longest dimension of the signal line, and wherein the first device layer and the second device layer are vertically between the backside power rail and the front side power rail, wherein the backside power rail extends laterally beyond an end of the front side power rail along the direction.
Rubin is silent with respect to “the second die separated from the first die by a scribe region”
FIG. 1 of Shue discloses a similar integrated circuit structure, comprising a first die (104a) comprising a first device layer (124y) and a first plurality of metallization layers (124z) over the first device layer; a second die (104b) comprising a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rubin, as taught by Shue. The ordinary artisan would have been motivated to modify Rubin in the above manner for purpose of reducing manufacturing cost and improving performance ([0072] of Shue).
The preamble “computing device” is a statement of intended use and is not considered to be of significance to claim construction, see MPEP 2111.02 II. During examination, statements in the preamble reciting the purpose or intended use of the claimed invention must be evaluated to determine whether the recited purpose or intended use results in a structural difference (or, in the case of process claims, manipulative difference) between the claimed invention and the prior art. If so, the recitation serves to limit the claim. See, e.g., In re Otto, 312 F.2d 937, 938, 136 USPQ 458, 459 (CCPA 1963). MPEP 2111.02. Since Rubin discloses a substantially identical structure of Claim 18, the recitation “computing device” is treated as the purpose or intended use of the claimed invention.
Claims 7-10 rejected under 35 U.S.C. 103 as being unpatentable over Rubin and Shue, in view of Tamaru (U.S. Patent Pub. No. 2012/0306101) of record.
Regarding Claim 7
Rubin as modified by Shue discloses Claim 6.
Rubin as modified by Shue is silent with respect to “the front side power rail is coupled to the first plurality of metallization layers of the first die by a first via stack of the first die, and the front side power rail is coupled to the second plurality of metallization layers of the second die by a second via stack of the second die”.
FIG. 5 of Tamaru discloses a similar integrated circuit structure, wherein the front side power rail is coupled to the first plurality of metallization layers of the first die by a first via stack of the first die, and the front side power rail is coupled to the second plurality of metallization layers of the second die by a second via stack of the second die.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rubin, as taught by Tamaru. The ordinary artisan would have been motivated to modify Rubin in the above manner for purpose of suppressing reduction in interconnection resources for signal lines ([0005] of Tamaru).
Regarding Claim 8
FIG. 1 of Tamaru discloses the backside power rail is coupled to the first device layer of first die by a first backside via structure, and the backside power rail is coupled to second device layer of the second die by a second backside via structure.
Regarding Claim 9
FIG. 1 of Shue discloses the first device layer and the second device layer are both logic device layers, or are both SRAM device layers [0018].
Regarding Claim 10
FIG. 1 of Shue discloses the first device layer is a logic device layer, and the second device layer is an SRAM device layer [0018].
Claim 14 rejected under 35 U.S.C. 103 as being unpatentable over Chen, Shue and Xie, in view of Zhu (CN 101202545) of record.
Regarding Claim 14
Chen as modified by Shue and Xie discloses Claim 11.
Chen as modified by Shue and Xie is silent with respect to “a battery coupled to the board”.
FIG. 2 of Zhu discloses a similar computing device, comprising a battery coupled to the board [0078].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Kusano. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of portable applications.
Claim 19 rejected under 35 U.S.C. 103 as being unpatentable over Rubin and Shue, in view of Zhu.
Regarding Claim 19
Rubin as modified by Shue discloses Claim 16.
Rubin as modified by Shue is silent with respect to “a battery coupled to the board”.
FIG. 2 of Zhu discloses a similar computing device, comprising a battery coupled to the board [0078].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rubin, as taught by Kusano. The ordinary artisan would have been motivated to modify Rubin in the above manner for purpose of portable applications.
Pertinent Art
FIG. 31 of Huang (U.S. Patent Pub. No. 2021/0366906) discloses an integrated circuit structure, comprising: a first die (left, such as N1/P1 of FIG. 1K) comprising a first device layer (left 260) and a first plurality of metallization layers (left 277) over the first device layer, the first device layer comprising a first plurality of integrated circuit devices (stacked); a second die (right, such as N2/P2 of FIG. 1K) comprising a second device layer (right 260) and a second plurality of metallization layers (right 277) over the second device layer, the second device layer comprising a second plurality of integrated circuit devices (stacked); a signal line coupling the first die and the second die at a first side of the first and second dies, the signal line continuous over the first device layer and the second device layer (FIG. 1K) and a backside power rail (284) coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side, the backside power rail continuous beneath the first device layer and the second device layer, wherein the first device layer and the second device layer are vertically between the backside power rail and the signal line. US 20080165109 discloses a signal line coupling the first die and the second die and a power rail coupling the first die and the second die. Lin (U.S. Patent Pub. No. 2020/0019671) discloses a device and a plurality of metallization layers vertically between a front side power rail and backside power rail; and vertically between the backside power rail and the signal line. Peng (U.S. Patent Pub. No. 2021/0391318); Jiang (CN 110676304).
Response to Arguments
Applicant’s arguments with respect to Claims 1, 6, 11 and 16 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Furthermore, the configuration of the claimed “the backside power rail extends laterally beyond an end of the signal line along the direction” was a matter of choice (as evidenced by FIGS 2 and 3 of Chen, US 20210358850), which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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