DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on May 15th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on May 15th, 2026 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 8-9, with respect to the rejections of claims 1-10 under 35 U.S.C 103(a) have been considered but are moot in view of the new ground(s) of rejection.
Applicant argues that Yeh fails to teach “wherein the second die and the first die are on a common semiconductor substrate” (see Applicant’s argument and pgs. 8-9). The Examiner respectfully disagrees because Yeh discloses the second die (device 113) and the first die (device 111) are indirectly on semiconductor device 215 as a common semiconductor substrate (see Fig. 2 and [0057-0058]) as recited in amended claims 1 and 6.
In view of the foregoing reasons, the examiner believes that all Applicant's arguments and remarks are addressed. The examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (Pub. No.: US 2015/0371951 A1), hereinafter as Yeh, and in view of Liaw (Pub. No.: US 2006/0102957 A1).
Regarding claim 1, Yeh discloses an integrated circuit structure in Fig. 2, comprising: a first die (device 111 being logic die) comprising a first device layer (first active devices of transistors and passive devices) and a first plurality of metallization layers (first metallization layers) over the first device layer (see [0023-0024] and [0026]), wherein the first device layer is a logic device layer (transistors and passive device of capacitors/resistors can provide function for logic circuit); a second die (device 113 being memory die) comprising a second device layer (second active devices) and a second plurality of metallization layers (second metallization layers), the second die separated from the first die by a scribe region (a region of encapsulant 115 between device 111 and 113) (see [0029]), wherein the second device layer is a transistor device layer (second active devices of device 113 being transistors) (see [0023] and [0028]); wherein the second die and the first die are on a common semiconductor substrate (device 113 and device 111 are indirectly on semiconductor device 215 as a common semiconductor substrate) (see Fig. 2 and [0057-0058]); and a common conductive interconnection (one conductive line of the third metallization layers 207) coupling the first die and the second die at a first side of the first and second dies (through pad 123 of device 111 and pad 125 of device 113) (upper surfaces of devices 111 and 113) (see [0044-0045]).
Yeh fails to disclose the second plurality of metallization layers over the second device layer and the second plurality of metallization layers comprises a layer of capacitor structures between an upper metallization layer portion and a lower metallization layer portion.
Liaw discloses an integrated circuit in Fig. 12 comprising a memory die (DRAM device 340) comprising a device layer (transistor P3) and a plurality of metallization layers (capacitor C3, metal wires 360, and wires 370) over the device layer (see [0078-0079], [0082]), wherein the second device layer is a transistor device layer (transistor P3), and the plurality of metallization layers comprises a layer of capacitor structures (a top plate 356b of capacitor C3) between an upper metallization layer portion (via and metal wires 360) and a lower metallization layer portion (via connecting to bottom plate 358b) (see [0082]).
Modifying the second die of Yeh to have the same structure of the memory die (DRAM device 340) of Liaw for having the plurality of metallization layers disposing over the second device layer and the second plurality of metallization layers comprising a layer of capacitor structures between an upper metallization layer portion and a lower metallization layer portion for disclosing all limitations of claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the second die of Yeh to have the same structure of the memory die of Liaw because the modified structure would more liable memory chip of packaging with small soft error on integrated circuit and further reduce low manufacturing cost (see Liaw and [0003-0005]).
Regarding claim 2, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 1, wherein a capacitor structure of the layer of capacitor structures is coupled to a transistor of the transistor device layer of the second die to provide a one-transistor-one-capacitor (1T-1 C) memory device (capacitor C3 and transistor P3) (see Liaw and Fig. 12).
Regarding claim 3, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 1, wherein the second die is vertically partitioned into a first memory structure and a second memory structure (DRAM cell 340 can made into multiple cell memory of the first memory structure and the second memory structure) (see Liaw and Figs 1 and 12).
Regarding claim 4, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 1, wherein the common conductive interconnection is a signal line (one conductive line of the third metallization layers 207 can send signal between devices 111 and 113) (see Yeh and Fig. 12).
Regarding claim 5, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 1, wherein the common conductive interconnection is a backside power rail (one conductive line of the third metallization layers 207 can function to provide power to devices 111 and 113) (see Yeh and Fig. 12).
Regarding claim 6, Yeh discloses an integrated circuit structure in Fig. 2, comprising: a first die (device 111 being memory die) comprising a first device layer (first active devices of transistors and passive devices) and a first plurality of metallization layers (first metallization layers) over the first device layer, wherein the first device layer is a first transistor device layer (see [0023-0024] and [0026]); a second die (device 113 also being memory die) comprising a second device layer (second active devices) and a second plurality of metallization layers (second metallization layers), the second die separated from the first die by a scribe region (a region of encapsulant 115 between device 111 and 113) (see [0029]), wherein the second device layer is a second transistor device layer (second active devices of device 113 being transistors) (see [0023] and [0028]); wherein the second die and the first die are on a common semiconductor substrate (device 113 and device 111 are indirectly on semiconductor device 215 as a common semiconductor substrate) (see Fig. 2 and [0057-0058]); and a common conductive interconnection (one conductive line of the third metallization layers 207) coupling the first die and the second die at a first side of the first and second dies (through pad 123 of device 111 and pad 125 of device 113) (upper surfaces of devices 111 and 113) (see [0044-0045]).
Yeh fails to disclose the first plurality of metallization layers comprises a first layer of capacitor structures between a first upper metallization layer portion and a first lower metallization layer portion, the second plurality of metallization layers over the second device layer and the second plurality of metallization layers comprises a second layer of capacitor structures between a second upper metallization layer portion and a second lower metallization layer portion.
Liaw discloses an integrated circuit in Fig. 12 comprising a memory die (DRAM device 340) comprising a device layer (transistor P3) and a plurality of metallization layers (capacitor C3, metal wires 360, and wires 370) over the device layer (see [0078-0079], [0082]), wherein the second device layer is a transistor device layer (transistor P3), and the plurality of metallization layers comprises a layer of capacitor structures (a top plate 356b of capacitor C3) between an upper metallization layer portion (via and metal wires 360) and a lower metallization layer portion (via connecting to bottom plate 358b) (see [0082]).
Modifying each of the first die and the second die of Yeh to have the same structure of the memory die (DRAM device 340) of Liaw for forming the first die comprising the first plurality of metallization layers comprising a first layer of capacitor structures between a first upper metallization layer portion and a first lower metallization layer portion and forming the second die comprising the second plurality of metallization layers disposing over the second device layer and the second plurality of metallization layers comprising a second layer of capacitor structures between a second upper metallization layer portion and a second lower metallization layer portion as recited in claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first die and second die of Yeh to have the same structure of the memory die of Liaw because the modified structure would more liable memory chips of packaging with small soft error on integrated circuit and further reduce low manufacturing cost (see Liaw and [0003-0005]).
Regarding claim 7, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 6, wherein a capacitor structure of the first layer of capacitor structures is coupled to a transistor of the first transistor device layer of the first die to provide a first one-transistor-one-capacitor ( first 1T-1 C) memory device (capacitor C3 and transistor P3) (see Liaw and Fig. 12), and wherein a capacitor structure of the second layer of capacitor structures is coupled to a transistor of the second transistor device layer of the second die to provide a second one-transistor-one-capacitor (second 1T-1C) memory device (capacitor C3 and transistor P3) (see Liaw and Fig. 12).
Regarding claim 8, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 6, wherein the second die is vertically partitioned into a first memory structure and a second memory structure (DRAM cell 340 can made into multiple cell memory of the first memory structure and the second memory structure) (see Liaw and Figs 1 and 12).
Regarding claim 9, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 6, wherein the common conductive interconnection is a signal line (one conductive line of the third metallization layers 207 can send signal between devices 111 and 113) (see Yeh and Fig. 12).
Regarding claim 10, the combination of Yeh and Liaw discloses the integrated circuit structure of claim 6, wherein the common conductive interconnection is a backside power rail (one conductive line of the third metallization layers 207 can function to provide power to devices 111 and 113) (see Yeh and Fig. 12).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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