DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 10/28/2025, with respect to Rejections under 35 USC 103 have been fully considered and are persuasive, amendments overcome the rejection as written. The 35 USC 103 rejections of claims 1-20 has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in further view of US 12394660 B2 Grant et al.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a drain structure having… a bottommost surface” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. No bottommost surface is illustrated and/or labeled, fig. 1 and fig. 2 of the instant application illustrate the drain structure (108/208) as being continuous with the substrate (102/202) having no clear bottommost surface of the drain structure.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being obvious over US 12249558 B2 Seo et al hereafter “Seo” in view of US 20220208757 A1 Do et al hereafter “Do” and US 12394660 B2 Grant et al hereafter “Grant”.
Regarding Claim 1 Seo fig. 2A teaches an integrated circuit structure, comprising:
a device layer (the layer and/or device, as illustrated in fig. 2A) comprising a drain structure (SD, the left trio ) having an uppermost surface (the uppermost surface of SD) and a bottommost surface (the bottommost surface of SD);
a buried power rail (POR) within the device layer and neighboring the drain structure, the buried power rail having an uppermost surface (the uppermost surface of POR) below the uppermost surface of the drain structure [as illustrated in fig. 2A];
a top-side power rail (CT1 and 132 and 142), the top-side power rail having a bottommost surface (the bottommost surface of CT1) above the uppermost surface of the drain structure [as illustrated in fig. 2A]; and
a conductive structure (CTE, and/or 134 and/or 144) directly coupling the top-side power rail to the buried power rail [as illustrated in fig. 2A].
Seo does not teach the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail nor the uppermost surface of the buried power rail above the bottommost surface of the drain.
Do teaches similar device comprising a top-side power rail (VSS and/or VVDD fig. 27A) vertically overlapping with a buried power rail (PWL1 left and/or right fig. 27A, met under broadest reasonable interpretation and/or MPEP 2112.01) along a vertical axis central [see annotation below] to the top-side power rail and the buried power rail
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange the device as taught by Seo such that “the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail” as Do teaches as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI. C.].
Grant teaches a similar device comprising a buried power rail (834 fig. 12B) which has an uppermost surface (the topmost surface of 834 fig. 12B) below an uppermost surface (the upper most surface of 820 fig. 12B) of a drain (comprising 820 fig. 12B) and above a bottommost surface (bottommost surface of 820, fig. 12B see annotation below) of the drain structure.
It would have been obvious to one of ordinary skill in the to combine the device of Seo in view of Do in further view of Grant such that the limitation “the buried power rail having an uppermost surface below the uppermost surface of the drain structure and above the bottommost surface of the drain structure” is fully met as combining art recognized equivalence for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case it is combining known power rail structure for the purpose of providing to the device and/or as a part of routine optimization of the lateral dimension, vertical dimension, and metal volume of the power rail to make additional space for other components and/or to lower resistance through the power rail without driving any negative impact to either via resistance and/or capacitance in the BEOL [Grant Column 1 lines 23-35, See MPEP 2144.05 II.]
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Annotated fig. 27: highlighting a vertical axis
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Grant Annotated fig. 12B: highlighting different surfaces as claimed in the limitations
Regarding claim 2 Seo in view of Do and Grant teaches as shown above in fig. 2A the integrated circuit structure of claim 1, wherein a cell boundary [see annotation below] of the device layer separates an active cell [left side see, annotation below] from a dummy cell [the right side meets this limitation as it has the same composition and structure as disclosed per MPEP 2112.01], wherein the buried power rail is within both the active cell and the dummy cell [as illustrated in fig. 2A, see annotation below], and wherein the drain structure is only within the active cell [as illustrated in fig. 2A, see annotation below].
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Annotated fig. 2A: highlighting the Active Cell, Dummy Cell, and Cell boundary
Regarding claim 3 Seo in View of Do and Grant teaches as shown above in fig. 2A the integrated circuit structure of claim 2, wherein the conductive structure comprises a tall via structure (CTE is structurally and compositionally the same as a VIA, see MPEP 2112.01), the tall via structure only within the dummy cell [as illustrated in fig. 2A CTE is only within the dummy cell].
Regard claim 4 Seo in view of Do and Grant teaches in fig. 2A as shown above the integrated circuit structure of claim 1, wherein the conductive structure comprises one or more via structures (Fig. 2A illustrates 1 CTE VIA structure), each via structure extending from the uppermost surface of the buried power rail to a location (topmost surface of CT1) above the uppermost surface of the drain structure [as illustrated in fig. 2A].
Regarding claim 5 Seo in view of Do and Grant teaches in fig. 2A as shown above the integrated circuit structure of claim I, wherein one or more trench contact layers (CT1) are on the drain structure [as illustrated in fig. 2A].
Regarding claim 6 Seo in view of Do and Grant teaches in fig. 2A as shown above the integrated circuit structure of claim 1, wherein the buried power rail is vertically over and coupled (coupled using element 200) to a bottom metallization structure (150), the bottom metallization structure exposed at a backside of the device layer (the bottommost surface of the layer and/device as illustrated in fig. 2A).
Regarding claim 7 Seo in view of Do and Grant teaches in fig. 2A as shown above the integrated circuit structure of claim 1, wherein the buried power rail is not coupled to the top-side power rail by a source structure [illustrated in fig. 2A the buried power rail POR is directly coupled to the top-side power rail (comprising CT1 and/or 132 and/or 142) by a tall via CTE].
Regarding claim 8 Seo as illustrated in fig. 2A teaches an integrated circuit structure, comprising:
an active cell (left side, see annotation below) separated from a dummy cell (the right side meets this limitation as it is structurally and compositionally the same as claimed and/or disclosed see MPEP 2112.01, see annotation below) by a cell boundary (see annotation below);
a buried power rail (POR) within both the active cell and the dummy cell [as illustrated in fig. 2A] and a drain structure (SD left trio), the buried power rail having an uppermost surface (topmost surface of POR) below an upper most surface of the drain structure (topmost surface of SD left trio); and
a top-side power rail (comprising CT1 and/or 132 and/or 142) coupled to the buried power rail, [coupled by one or VIAs comprising CTE and/or 134 and/or 144], wherein the buried power rail is not coupled to the top-side power rail by a source structure [illustrated in fig. 2 coupled by one or more via’s comprising CTE and/or 134 and/or 144].
Seo does not teach the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail nor the topmost surface of the buried power rail above a bottommost surface of the drain structure.
Do teaches similar device comprising a top-side power rail (VSS and/or VVDD fig. 27A) vertically overlapping and coupled with a buried power rail (PWL1 left and/or right fig. 27A, met under broadest reasonable interpretation and/or MPEP 2112.01) along a vertical axis central [see annotation below] to the top-side power rail and the buried power rail.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange the device as taught by Seo such that “the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail” as Do teaches as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI. C.].
Grant teaches a similar device comprising a buried power rail (834 fig. 12B) which has an uppermost surface (the topmost surface of 834 fig. 12B) below an uppermost surface (the upper most surface of 820 fig. 12B) of a drain (comprising 820 fig. 12B) and above a bottommost surface (bottommost surface of 820, fig. 12B see annotation below) of the drain structure.
It would have been obvious to one of ordinary skill in the to combine the device of Seo in view of Do in further view of Grant such that the limitation “the buried power rail having an uppermost surface below an uppermost surface of the drain structure and above a bottommost surface of the drain structure” is fully met as combining art recognized equivalence for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case it is combining known power rail structure for the purpose of providing to the device and/or as a part of routine optimization of the lateral dimension, vertical dimension, and metal volume of the power rail to make additional space for other components and/or to lower resistance through the power rail without driving any negative impact to either via resistance and/or capacitance in the BEOL [Grant Column 1 lines 23-35, See MPEP 2144.05 II.]
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Annotated fig. 27: highlighting a vertical axis
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Annotated fig. 2A: highlighting the Active Cell, Dummy Cell, and Cell boundary
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Grant Annotated fig. 12B: highlighting different surfaces as claimed in the limitations
Regarding claim 9 Seo in view of Do and Grant teaches in fig. 2A as shown above the integrated circuit structure of claim 8, wherein the top-side power rail is coupled to the buried power rail by a tall via structure (CTE), the tall via structure only within the dummy cell [as illustrated in fig. 2A].
Regarding claim 10 Seo in view of Do and Grant teaches in fig. 2A as shown above the integrated circuit structure of claim 8, wherein the buried power rail is vertically over and coupled (coupled by element 200) to a bottom metallization structure (150).
Regarding claim 11 Seo teaches a computing device, comprising:
a board (30 fig. 23 under broadest reasonable interpretation, and/or explicitly 31 fig. 25-26, column 21 lines 19-20 “printed circuit board”); and
a component coupled to the board, the component including an integrated circuit structure (the component as illustrated in fig. 2A sufficiently disclosed a being part of the computing device in Column 1 lines 35-40 “a semiconductor device having increased reliability, which can be easily fabricated, and a semiconductor package including the same” wherein the embodiments of fig.’s 23, 25 and 26 are the semiconductor package and fig. 1-16C are various embodiments and cross-sections of the semiconductor device, see “brief description of the drawings” beginning column 2 ending column 3), comprising:
a device layer (the device and/or layer of fig. 2A) comprising a drain structure (SD left trio) having an uppermost surface (the upper most surface SD left trio) and a bottommost surface (the bottommost surface SD left trio);
a buried power rail (POR) within the device layer and neighboring the drain structure [illustrated fig. 2A], the buried power rail having an uppermost surface (the upper most surface of POR) below the uppermost surface of the drain structure [illustrated fig. 2A];
a top-side power rail (comprising CT1 and/or 132 and/or 142), the top-side power rail having a bottommost surface (the bottom most surface of CT1) above the uppermost surface of the drain structure [illustrated fig. 2A]; and
a conductive structure (comprising CTE and 134 and 144) directly coupling the top-side power rail to the buried power rail.
Seo does not teach the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail.
Do teaches similar device comprising a top-side power rail (VSS and/or VVDD fig. 27A) vertically overlapping with a buried power rail (PWL1 left and/or right fig. 27A, met under broadest reasonable interpretation and/or MPEP 2112.01) along a vertical axis central [see annotation below] to the top-side power rail and the buried power rail nor the uppermost surface of the buried power rail above the bottommost surface of the drain.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange the device as taught by Seo such that “the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail” as Do teaches as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI. C.].
Grant teaches a similar device comprising a buried power rail (834 fig. 12B) which has an uppermost surface (the topmost surface of 834 fig. 12B) below an uppermost surface (the upper most surface of 820 fig. 12B) of a drain (comprising 820 fig. 12B) and above a bottommost surface (bottommost surface of 820, fig. 12B see annotation below) of the drain structure.
It would have been obvious to one of ordinary skill in the to combine the device of Seo in view of Do in further view of Grant such that the limitation “the buried power rail having an uppermost surface below the uppermost surface of the drain structure and above the bottommost surface of the drain structure” is fully met as combining art recognized equivalence for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case it is combining known power rail structure for the purpose of providing to the device and/or as a part of routine optimization of the lateral dimension, vertical dimension, and metal volume of the power rail to make additional space for other components and/or to lower resistance through the power rail without driving any negative impact to either via resistance and/or capacitance in the BEOL [Grant Column 1 lines 23-35, See MPEP 2144.05 II.]
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Annotated fig. 27: highlighting a vertical axis
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Grant Annotated fig. 12B: highlighting different surfaces as claimed in the limitations
Regarding claim 12 Seo in view of Do and Grant teaches as shown above the computing device of claim 11, further comprising:
a memory coupled to the board (an embodiment is sufficiently disclosed as part of 500 fig. 23, Column 20 lines 5-10 “the first semiconductor chips 500 may constitute a high band width (HBM) memory chip including a plurality of memory chips”).
Regarding claim 13 Seo in view of Do and Grant teaches as shown above the computing device of claim 11, further comprising:
a communication chip coupled to the board (an embodiment is sufficiently disclosed as part of 500 fig. 23, Column 20 lines 5-10 “the first semiconductor chips 500 may constitute a high band width (HBM) memory chip including a plurality of memory chips, wherein “band width” is a measurement of the communication frequency range).
Regarding claim 14 Seo in view of Do and Grant teaches as shown above the computing device of claim 11, further comprising:
a camera coupled to the board (an embodiment is sufficiently disclosed as “image sensor chip” 900 fig. 26, wherein an image sensor constitutes a camera under broadest reasonable interpretation column 22 lines 29-33).
Regarding claim 15 Seo in view of Do and Grant teaches as shown above the computing device of claim 11, wherein the component is a packaged integrated circuit die (the semiconductor package of fig. 23 and/or 25 and/or 26).
Regarding claim 16 Seo teaches a computing device, comprising:
a board (30 fig. 23 under broadest reasonable interpretation, and/or explicitly 31 fig. 25-26, column 21 lines 19-20 “printed circuit board”); and
a component coupled to the board (the component as illustrated in fig. 2A sufficiently disclosed a being part of the computing device in Column 1 lines 35-40 “a semiconductor device having increased reliability, which can be easily fabricated, and a semiconductor package including the same” wherein the embodiments of fig.’s 23, 25 and 26 are the semiconductor package and fig. 1-16C are various embodiments and cross-sections of the semiconductor device, see “brief description of the drawings” beginning column 2 ending column 3), the component including an integrated circuit structure , comprising:
an active cell (left side of fig. 2A, see annotation below) separated from a dummy cell (right side of fig. 2A, is structurally and compositionally the same [see MPEP 2112], see annotation below) by a cell boundary (see annotation below);
a buried power rail (POR fig. 2A) within both the active cell and the dummy cell and a neighboring a drain structure (SD left trio fig. 2A); and
a top-side power rail (comprising CT1 and 132 and 142) coupled to the buried power rail, [illustrated in fig. 2A], wherein the buried power rail is not coupled to the top-side power rail by a source structure [limitation is met as it is coupled by directly by VIA CTE].
Seo does not teach the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail nor the uppermost surface of the buried power rail above the bottommost surface of the drain structure.
Do teaches similar device comprising a top-side power rail (VSS and/or VVDD fig. 27A) vertically overlapping with a buried power rail (PWL1 left and/or right fig. 27A, met under broadest reasonable interpretation and/or MPEP 2112.01) along a vertical axis central [see annotation below] to the top-side power rail and the buried power rail.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange the device as taught by Seo such that “the top-side power rail vertically overlapping with the buried power rail along a vertical axis central to the top-side power rail and the buried power rail” as Do teaches as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI. C.].
Grant teaches a similar device comprising a buried power rail (834 fig. 12B) which has an uppermost surface (the topmost surface of 834 fig. 12B) below an uppermost surface (the upper most surface of 820 fig. 12B) of a drain (comprising 820 fig. 12B) and above a bottommost surface (bottommost surface of 820, fig. 12B see annotation below) of the drain structure.
It would have been obvious to one of ordinary skill in the to combine the device of Seo in view of Do in further view of Grant such that the limitation “the buried power rail having an uppermost surface below an uppermost surface of the drain structure and above a bottommost surface of the drain structure” is fully met as combining art recognized equivalence for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case it is combining known power rail structure for the purpose of providing to the device and/or as a part of routine optimization of the lateral dimension, vertical dimension, and metal volume of the power rail to make additional space for other components and/or to lower resistance through the power rail without driving any negative impact to either via resistance and/or capacitance in the BEOL [Grant Column 1 lines 23-35, See MPEP 2144.05 II.]
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Grant Annotated fig. 12B: highlighting different surfaces as claimed in the limitations
Regarding claim 17 Seo in view of Do and Grant teaches as shown above the computing device of claim 16, further comprising:
a memory coupled to the board (an embodiment is sufficiently disclosed as part of 500 fig. 23, Column 20 lines 5-10 “the first semiconductor chips 500 may constitute a high band width (HBM) memory chip including a plurality of memory chips”).
Regarding claim 18 Seo in view of Do and Grant teaches as shown above the computing device of claim 16, further comprising:
a communication chip coupled to the board (an embodiment is sufficiently disclosed as part of 500 fig. 23, Column 20 lines 5-10 “the first semiconductor chips 500 may constitute a high band width (HBM) memory chip including a plurality of memory chips, wherein “band width” is a measurement of the communication frequency range).
Regarding claim 19 Seo in view of Do and Grant teaches as shown above the computing device of claim 16, further comprising:
a camera coupled to the board (an embodiment is sufficiently disclosed as “image sensor chip” 900 fig. 26, wherein an image sensor constitutes a camera under broadest reasonable interpretation column 22 lines 29-33).
Regarding claim 20 Seo in view of Do and Grant teaches as shown above the computing device of claim 16, wherein the component is a packaged integrated circuit die (the semiconductor package of fig. 23 and/or 25 and/or 26).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893