Detailed Action
This office action is in response to the request for continued examination filed on December 2nd, 2025. Claims 1-2, 4-7, and 9-30 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 2nd, 2025, has been entered.
Response to Arguments
Applicant's arguments filed December 2nd, 2025, have been fully considered but they are not persuasive.
Applicant argues (pgs. 11-13, “Remarks”) that Liu fails to teach the limitations presented in amended Claims 1, 6, 11, and 16.
However, as seen below, Rachmady can be utilized to teach the additional limitations presented in amended Claims 1, 6, 11, and 16. Applicant does not comment on Rachmady as it pertains to the introduced limitations. As a result, Claims 1, 6, 11, and 16 are rejected by the combination of Rachmady and Liu.
Therefore, applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, and 9-30 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (2015/0144880 A1; hereinafter Rachmady) in view of Liu et al. (2022/0367625 A1; hereinafter Liu).
Regarding Claim 1, Rachmady (fig. 1A and annotated fig. 1B) teaches an integrated circuit structure ([0015], 100), comprising:
a vertical arrangement of nanowires ([0015], stack of 110, see annotated fig. 1B);
a gate stack ([0015], 116, 118) over the vertical arrangements of nanowires (110);
a first epitaxial source or drain structure ([0015], 106) at a first end of the vertical arrangement of nanowires (left side of stack 110); and a
second epitaxial source or drain structure ([0015], 107) at a second end of the vertical arrangement of nanowires (right side of stack 110), wherein
one or both of the first (106) or second (107) epitaxial source or drain structures has an upper portion (portion of 106 and 107 above 108, referred to as upper portion, see annotated fig. 1B) and a lower epitaxial extension portion ([0018], portion of 106 and 107 within 108, referred to as lower portion, see annotated fig. 1B), wherein
the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction, and wherein the upper portion (upper portion) has an outermost sidewall (outermost sidewall, see annotated fig. 1B) at the corresponding first or second end of the vertical arrangement of nanowires (outermost sidewall contacts left side of stack 110, for example).
Rachmady doesn’t teach the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction.
However, Liu (annotated fig. 26) teaches the upper portion ([0055], portion of 98 above 62, referred to as upper portion, see annotated fig. 26) has a lateral width along a source to drain direction (left to right in fig. 26) greater than (see annotated fig. 26) a lateral width of the lower epitaxial extension portion (portion of 98 within 62, referred to as lower portion, see annotated fig. 26) along the source to drain direction. Liu also teaches various lower epitaxial extension portions that teach the above limitation ([0053], figs. 13A-C). One of ordinary skill in the art would have found it obvious to try and use a differently shaped lower epitaxial extension portion and yielded the predictable results of a functional transistor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use a differently shaped lower epitaxial extension portion since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
PNG
media_image1.png
526
702
media_image1.png
Greyscale
Annotated Figure 1B
PNG
media_image2.png
714
640
media_image2.png
Greyscale
Annotated Figure 26
Regarding Claim 2, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 1, wherein the upper portion (upper portion) is continuous with the lower epitaxial extension portion (lower portion).
Regarding Claim 4, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 1, wherein the vertical arrangement of nanowires (110) is over a sub-fin ([0020], portion of 109 under the stack of 110, referred to as sub-fin, see annotated fig. 1B).
Regarding Claim 5, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 4, wherein the lower epitaxial extension portion (lower portion) has a bottommost surface ([0015], 104, see fig. 1B) below an uppermost surface of the sub-fin (top of sub-fin in contact with 114, see annotated fig. 1B, also see figs. 3L-M for similar features).
Regarding Claim 6, Rachmady (fig. 1A and annotated fig. 1B) teaches an integrated circuit structure, comprising:
a fin ([0015], stack of 110, see fig. 1B);
a gate stack ([0015], 116, 118) over the fin (stack of 110);
a first epitaxial source or drain structure ([0015], 106) at a first end of the fin (left side of stack of 110); and a
second epitaxial source or drain structure ([0015], 107) at a second end of the fin (right side of stack of 110), wherein
one or both of the first (106) or second (107) epitaxial source or drain structures has an upper portion (portion of 106 and 107 above 108, referred to as upper portion, see annotated fig. 1B) and a lower epitaxial extension portion ([0018], portion of 106 and 107 within 108, referred to as lower portion, see annotated fig. 1B), wherein
the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction, and wherein the upper portion (upper portion) has an outermost sidewall (outermost sidewall, see annotated fig. 1B) at the corresponding first or second end of the fin (outermost sidewall is contact with the left side of stack of 110, for example).
Rachmady doesn’t teach the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction.
However, Liu (annotated fig. 26) teaches the upper portion ([0055], portion of 98 above 62, referred to as upper portion, see annotated fig. 26) has a lateral width along a source to drain direction (left to right in fig. 26) greater than (see annotated fig. 26) a lateral width of the lower epitaxial extension portion (portion of 98 within 62, referred to as lower portion, see annotated fig. 26) along the source to drain direction. Liu also teaches various lower epitaxial extension portions that teach the above limitation ([0053], figs. 13A-C). One of ordinary skill in the art would have found it obvious to try and use a differently shaped lower epitaxial extension portion and yielded the predictable results of a functional transistor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use a differently shaped lower epitaxial extension portion since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 7, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 6, wherein the upper portion (upper portion) is continuous with the lower epitaxial extension portion (lower portion).
Regarding Claim 9, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 6, wherein the fin (110) is over a sub-fin ([0020], portion of 109 under the stack of 110, referred to as sub-fin, see annotated fig. 1B).
Regarding Claim 10, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 9, wherein the lower epitaxial extension portion (lower portion) has a bottommost surface ([0015], 104) below an uppermost surface of the sub-fin (top of sub-fin in contact with 114, see annotated fig. 1B, also see figs. 3L-M for similar features).
Regarding Claim 11, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches a computing device ([0056], 400, see fig. 4), comprising:
a board ([0056], 402, see fig. 4); and
a component ([0056], 404, see fig. 4) coupled to the board (402), the component (404) including an integrated circuit structure ([0059]), comprising:
a vertical arrangement of nanowires ([0015], stack of 110, see fig. 1B);
a gate stack ([0015], 116, 118) over the vertical arrangements of nanowires (110);
a first epitaxial source or drain structure ([0015], 106) at a first end of the vertical arrangement of nanowires (left side of stack 110); and
a second epitaxial source or drain structure ([0015], 107) at a second end of the vertical arrangement of nanowires (right side of stack 110), wherein
one or both of the first (106) or second (107) epitaxial source or drain structures has an upper portion (portion of 106 and 107 above 108, referred to as upper portion, see annotated fig. 1B) and a lower epitaxial extension portion ([0018], portion of 106 and 107 within 108, referred to as lower portion, see annotated fig. 1B), wherein
the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction, and wherein the upper portion (upper portion) has an outermost sidewall (outermost sidewall, see annotated fig. 1B) at the corresponding first or second end of the vertical arrangement of nanowires (outermost sidewall contacts left side of stack 110, for example).
Rachmady doesn’t teach the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction.
However, Liu (annotated fig. 26) teaches the upper portion ([0055], portion of 98 above 62, referred to as upper portion, see annotated fig. 26) has a lateral width along a source to drain direction (left to right in fig. 26) greater than (see annotated fig. 26) a lateral width of the lower epitaxial extension portion (portion of 98 within 62, referred to as lower portion, see annotated fig. 26) along the source to drain direction. Liu also teaches various lower epitaxial extension portions that teach the above limitation ([0053], figs. 13A-C). One of ordinary skill in the art would have found it obvious to try and use a differently shaped lower epitaxial extension portion and yielded the predictable results of a functional transistor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use a differently shaped lower epitaxial extension portion since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 12, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 11, further comprising: a memory ([0057], DRAM) coupled to the board (402).
Regarding Claim 13, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 11, further comprising: a communication chip ([0056], 406, see fig. 4) coupled to the board (402).
Regarding Claim 14, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 11, further comprising: a battery ([0057], battery) coupled to the board (402).
Regarding Claim 15, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 11, further comprising: the component (404) is a packaged integrated circuit die ([0059]).
Regarding Claim 16, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches a computing device ([0056], 400, see fig. 4), comprising:
a board ([0056], 402, see fig. 4); and
a component ([0056], 404, see fig. 4) coupled to the board (402), the component (404) including an integrated circuit structure ([0059]), comprising:
a fin ([0015], stack of 110, see fig. 1B);
a gate stack ([0015], 116, 118) over the fin (110);
a first epitaxial source or drain structure ([0015], 106) at a first end of the fin (left side of stack 110); and
a second epitaxial source or drain structure ([0015], 107) at a second end of the fin (right side of stack 110), wherein
one or both of the first (106) or second (107) epitaxial source or drain structures has an upper portion (portion of 106 and 107 above 108, referred to as upper portion, see annotated fig. 1B) and a lower epitaxial extension portion ([0018], portion of 106 and 107 within 108, referred to as lower portion, see annotated fig. 1B), wherein
the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction, and wherein the upper portion (upper portion) has an outermost sidewall (outermost sidewall, see annotated fig. 1B) at the corresponding first or second end of the fin (outermost sidewall is in contact with left side of stack 110, for example).
Rachmady doesn’t teach the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction.
However, Liu (annotated fig. 26teaches the upper portion ([0055], portion of 98 above 62, referred to as upper portion, see annotated fig. 26) has a lateral width along a source to drain direction (left to right in fig. 26) greater than (see annotated fig. 26) a lateral width of the lower epitaxial extension portion (portion of 98 within 62, referred to as lower portion, see annotated fig. 26) along the source to drain direction. Liu also teaches various lower epitaxial extension portions that teach the above limitation ([0053], figs. 13A-C). One of ordinary skill in the art would have found it obvious to try and use a differently shaped lower epitaxial extension portion and yielded the predictable results of a functional transistor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use a differently shaped lower epitaxial extension portion since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 17, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 16, further comprising: a memory ([0057], DRAM) coupled to the board (402).
Regarding Claim 18, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 16, further comprising: a communication chip ([0056], 406, see fig. 4) coupled to the board (402).
Regarding Claim 19, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 16, further comprising: a battery ([0057], battery) coupled to the board (402).
Regarding Claim 20, Rachmady (figs. 1A and 4 and annotated fig. 1B) teaches the computing device of claim 16, further comprising: the component (404) is a packaged integrated circuit die ([0059]).
Regarding Claim 21, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 1, wherein the vertical arrangement of nanowires (stack of 110) comprises a first nanowire (bottommost 110), a second nanowire (middle 110) over the first nanowire (bottommost 110), and a third nanowire (topmost 110) over the second nanowire (middle 110).
Regarding Claim 22, Rachmady doesn’t teach the integrated circuit structure of claim 1, further comprising: a first conductive contact on the first epitaxial source or drain structure; and a second conductive contact on the second epitaxial source or drain structure.
However, Liu (annotated fig. 26) teaches a first conductive contact ([0085], 144 above left 98, referred to as first conductive contact, see annotated fig. 26) on the first epitaxial source or drain structure ([0017], left 98); and a second conductive contact ([0085], 144 above right 98, referred to as second conductive contact, see annotated fig. 26) on the second epitaxial source or drain structure (right 98). Liu also teaches that the source/drain contacts may connect the FET to other features ([0089]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated circuit structure of Rachmady to include the first and second conductive contacts of Liu to connect the FET to other features.
Regarding Claim 23, Liu (annotated fig. 26) teaches the integrated circuit structure of claim 22, wherein the first conductive contact has an uppermost surface (top surface of first conductive contact, see annotated fig. 26) at a same level (see annotated fig. 26) as an uppermost surface of the gate stack ([0085], 142, 124; uppermost surface refers to the top surface of 142).
Regarding Claim 24, Liu (annotated fig. 26) teaches the integrated circuit structure of claim 23, wherein the second conductive contact has an uppermost surface (top surface of second conductive contact, see annotated fig. 26) at a same level (see annotated fig. 26) as an uppermost surface of the gate stack ([0085], 142, 124; uppermost surface refers to the top surface of 142).
Regarding Claim 25, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 4, wherein the lower epitaxial extension portion (lower portion) of each of the first (106) and second (107) epitaxial source or drain structures is laterally adjacent (see annotated fig. 1B) to the sub-fin (sub-fin).
Regarding Claim 26, Rachmady (fig. 1A and annotated fig. 1B) teaches an integrated circuit structure ([0015], 100), comprising:
a sub-fin ([0020], portion of 109 under the stack of 110, referred to as sub-fin, see annotated fig. 1B);
a vertical arrangement of nanowires ([0015], stack of 110, see annotated fig. 1B) over the sub-fin (sub-fin);
a first source or drain structure ([0015], 106) at a first end of the vertical arrangement of nanowires (left side of stack 110),
the first source or drain structure (106) having an upper portion (portion of 106 above 108, referred to as upper portion of 106, see annotated fig. 1B) and a lower epitaxial extension portion ([0018], portion of 106 within 108, referred to as lower portion of 106, see annotated fig. 1B), the lower epitaxial extension portion (lower portion of 106) laterally adjacent (see annotated fig. 1B) to the sub-fin (sub-fin), wherein
the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction, and wherein the upper portion (upper portion of 106) has an outermost sidewall (outermost sidewall of 106, see annotated fig. 1B) at the first end of the vertical arrangement of nanowires (outermost sidewall of 106 is in contact with left side of stack 110);
a second source or drain structure ([0015], 107) at a second end of the vertical arrangement of nanowires (right side of stack 110), the second end (right side of stack 110) laterally opposite the first end (left side of stack 110),
the second source or drain structure (107) having an upper portion (portion of 107 above 108, referred to as upper portion of 107, see annotated fig. 1B) and a lower epitaxial extension portion ([0018], portion of 107 within 108, referred to as lower portion of 106, see annotated fig. 1B), the lower epitaxial extension portion (lower portion of 107) laterally adjacent (see annotated fig. 1B) to the sub-fin (sub-fin), wherein
the upper portion has a lateral width along the source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction, and wherein the upper portion (upper portion of 107) has an outermost sidewall (outermost sidewall of 107, see annotated fig. 1B) at the second end of the vertical arrangement of nanowires (outermost sidewall of 107 is in contact with the right side of stack 110);
a gate stack ([0015], 116, 118) over and around each of the nanowires (110) of the vertical arrangement of nanowires (stack of 110) and laterally between the first source or drain structure (106) and the second source or drain structure (107);
a first conductive contact on the first source or drain structure; and a second conductive contact on the second source or drain structure.
Rachmady doesn’t teach the upper portion has a lateral width along a source to drain direction greater than a lateral width of the lower epitaxial extension portion along the source to drain direction.
However, Liu (annotated fig. 26) teaches the upper portion ([0055], portion of 98 above 62, referred to as upper portion, see annotated fig. 26) has a lateral width along a source to drain direction (left to right in fig. 26) greater than (see annotated fig. 26) a lateral width of the lower epitaxial extension portion (portion of 98 within 62, referred to as lower portion, see annotated fig. 26) along the source to drain direction. Liu also teaches various lower epitaxial extension portions that teach the above limitation ([0053], figs. 13A-C). One of ordinary skill in the art would have found it obvious to try and use a differently shaped lower epitaxial extension portion and yielded the predictable results of a functional transistor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use a differently shaped lower epitaxial extension portion since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Rachmady doesn’t teach a first conductive contact on the first source or drain structure; and a second conductive contact on the second source or drain structure.
However, Liu (annotated fig. 26) teaches a first conductive contact ([0085], 144 above left 98, referred to as first conductive contact, see annotated fig. 26) on the first source or drain structure ([0017], left 98); and a second conductive contact ([0085], 144 above right 98, referred to as second conductive contact, see annotated fig. 26) on the second source or drain structure (right 98). Liu also teaches that the source/drain contacts may connect the FET to other features ([0089]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated circuit structure of Rachmady to include the first and second conductive contacts of Liu to connect the FET to other features.
Regarding Claim 27, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 26, wherein the vertical arrangement of nanowires (stack of 110) comprises a first nanowire (bottommost 110), a second nanowire (middle 110) over the first nanowire (bottommost 110), and a third nanowire (topmost 110) over the second nanowire (middle 110).
Regarding Claim 28, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 26, wherein the first conductive contact has an uppermost surface (top surface of first conductive contact, see annotated fig. 26) at a same level (see annotated fig. 26) as an uppermost surface of the gate stack ([0085], 142, 124; uppermost surface refers to the top surface of 142).
Regarding Claim 29, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 28, wherein the second conductive contact has an uppermost surface (top surface of second conductive contact, see annotated fig. 26) at a same level (see annotated fig. 26) as an uppermost surface of the gate stack ([0085], 142, 124; uppermost surface refers to the top surface of 142).
Regarding Claim 30, Rachmady (fig. 1A and annotated fig. 1B) teaches the integrated circuit structure of claim 26, wherein the vertical arrangement of nanowires (stack of 110) is a vertical arrangement of silicon nanowires ([0022], nanowires 110 may be Si).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 25, 2026