DETAILED ACTION
This Notice is responsive to communication filed on 01/06/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/26/2026 has been entered.
Response to Amendment
The amendment filed on 01/06/2026 under 37 C.F.R. 1.111 has been entered. Claims 1, 2, 4, 8, 12-14, 24 and 25 remain pending in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (US 20240250053).
Regarding claim 1, Huang discloses a die module Fig. 4: 400, comprising:
a first die Fig. 4: 401 with a set of first pads Fig. 4: 401HR, a set of second pads Fig. 4: 401LS, and a set of third pads Fig. 4: 401HR’ with surfaces that are substantially coplanar with a surface of a first dielectric layer Fig. 4: 105, the set of second pads Fig. 4: 401LS laterally between the set of first pads Fig. 4: 401HR and the set of third pads Fig. 4: 401HR’, wherein the set of second pads Fig. 4: 401LS is a set of dummy pads that is not coupled to a die (para. 0043 teaches “supporters” not electrically connected);
a second die Fig. 4: 200 with a set of fourth pads Fig. 4: 203 with surfaces that are substantially coplanar with a surface of a second dielectric layer (-underfill located beneath 200), and wherein the first pads Fig. 4: 401HR are bonded to the fourth pads Fig. 4: 203 and the first dielectric layer Fig. 4: 105 is bonded to the second dielectric layer (via Fig. 4: 403); and
a third die Fig. 4: 300 with a set of fifth pads Fig. 4: 303 with surfaces that are substantially coplanar with a surface of a third dielectric layer (underfill located beneath 300), and wherein the third pads Fig. 4: 401HR’ are bonded to the fifth pads Fig. 4: 303 and the first dielectric layer Fig. 4: 105 is bonded to the third dielectric layer (via Fig. 4: 403).
Regarding claim 2, Huang teaches the die module of claim 1, wherein a width of the first die Fig. 4: 401 is greater than a width of the second die Fig. 4: 200 (shown in Fig. 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) as applied to claim 1 above, and further in view of Uzoh et al. (US 20250266401).
Regarding claim 4, although Huang teaches the substantial features of claim 1, Huang fails to explicitly teach the die module of claim 1, wherein corners of the second die are rounded. However, Uzoh teaches wherein corners of the second die Fig. 12: 106 are rounded (para. 0074, “edges of the top die 106 may also be rounded”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Huang and Uzoh for the purpose of preventing point stress concentration during stack fabrication and avoiding cracking or chipping fragile dies (para. 0074).
Claims 8, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053), and further in view of Chen et al. (US 20200286879).
Regarding claim 8, although Huang teaches the substantial features of claim 1, Huang fails to explicitly teach the die module of claim 1, further comprising through die via through a thickness of the second die. However, Chen discloses the die module of claim 1, further comprising a through die via through a thickness of the second die Fig. 1C: 19a (para. 0069, “Vias such as TSVs, TIVs, TDVs, or the like, or a combination thereof may be formed to electrical connect the dies or devices on the semiconductor package structure 100a to the dies 19a and the wafer 18”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Huang and Chen for the purpose of stacking more layers of dies or devices on the package structure to form a multi-layer stacked chip-on-wafer structure (para. 0069).
Regarding claim 13, although Huang teaches the substantial features of claim 1, Huang fails to explicitly teach the die module of claim 1, wherein the first die comprises through die vias. However, Chen discloses the die module of claim 1, wherein the first die Fig. 1C: 18 comprises through die vias (para. 0069, “Vias such as TSVs, TIVs, TDVs, or the like, or a combination thereof may be formed to electrical connect the dies or devices on the semiconductor package structure 100a to the dies 19a and the wafer 18”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Huang and Chen for the purpose of stacking more layers of dies or devices on the package structure to form a multi-layer stacked chip-on-wafer structure (para. 0069).
Regarding claim 14, although Huang teaches the substantial features of claim 1, Huang fails to explicitly teach the die module of claim 13, wherein pads are coupled to the through die vias. However, Chen teaches pads Fig. 1A: 14, 24 are coupled to the through die vias (in para 0069) for the purpose of bonding the dies. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the pads in contact with the dies and the through die vias in the first die for the purpose of stacking more layers of dies or devices on the semiconductor package to form multi-layer stack chip-on-wafer structure (para. 0069).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) as applied to claim 1 above, and further in view of Budd et al. (US 10,217,637).
Regarding claim 12, although Huang teaches the substantial elements of claim 1, Huang fails to explicitly teach the die module of claim 1, wherein the first die comprises first fiducial marks, and wherein the second die comprises second fiducial marks that are aligned with the first fiducial marks. However, Budd teaches wherein the first die Fig. 8B: 26 comprises first fiducial marks Fig. 8B: 26A, and wherein the second die Fig. 8B: 34A comprises second fiducial marks Fig. 8B: 34AA that are aligned with the first fiducial marks (col. 11, lines 2-5). Therefore, it would have been obvious to one of ordinary skill in the art before the date of the claimed invention to combine Huang’s and Budd’s teachings to include fiducial marks in Huang’s die module for the purpose of facilitating proper alignment of these structures (col. 11, lines 2-5).
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) and further in view of Chen et al. (US 20210091064).
Regarding claim 24, Huang teaches an electronic system, comprising:
a package substrate Fig. 4: 404; and
a die module Fig. 4: 400 coupled to the package substrate Fig. 4: 404, wherein the die module comprises Fig. 4: 400:
a first die Fig. 4: 401 with a set of first pads Fig. 4: 401HR, a set of second pads Fig. 4: 401LS, and a set of third pads Fig. 4: 401HR’ with surfaces that are substantially coplanar with a surface of a first dielectric layer Fig. 4: 105, the set of second pads Fig. 4: 401LS laterally between the set of first pads Fig. 4: 401HR and the set of third pads Fig. 4: 401HR’, wherein the set of second pads Fig. 4: 401LS is a set of dummy pads that is not coupled to a die (para. 0043 teaches “supporters” not electrically connected);
a second die Fig. 4: 200 with a set of fourth pads Fig. 4: 203 with surfaces that are substantially coplanar with a surface of a second dielectric layer (underfill located beneath 200), and wherein the first pads Fig. 4: 401HR are bonded to the fourth pads Fig. 4: 203 and the first dielectric layer Fig. 4: 105 is bonded to the second dielectric layer (via Fig. 4: 403); and
a third die Fig. 4: 300 with a set of fifth pads Fig. 4: 303 with surfaces that are substantially coplanar with a surface of a third dielectric layer (underfill located beneath 300), and wherein the third pads Fig. 4: 401HR’ are bonded to the fifth pads Fig. 4: 303 and the first dielectric layer Fig. 4: 105 is bonded to the third dielectric layer (via Fig. 4: 403).
Huang fails to explicitly teach the electronic system comprising a board, with the package substrate coupled to the board.
However, Chen (US 2021/0091064 A1) teaches the electronic system Fig. 4B, comprising a board Fig. 4B: 400, a package substrate Fig. 4B: 100 coupled to the board Fig. 4B: 400, and a die module Fig. 4B: W1 coupled to the package substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the date of the claimed invention to combine Huang’s and Chen’s teachings for the purpose of grounding the dies and the package substrate (para 0056).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) and Chen et al. (US 20210091064), and further in view of Uzoh et al. (US 20250266401).
Regarding claim 25, although Huang and Chen teach the substantial features of claim 24, they fail to explicitly teach the electronic system of claim 24, wherein corners of the second die are rounded. However, Uzoh teaches wherein corners of the second die Fig. 12: 106 are rounded (para. 0074, “edges of the top die 106 may also be rounded”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Huang, Chen, and Uzoh for the purpose of preventing point stress concentration during stack fabrication and avoiding cracking or chipping fragile dies (para. 0074).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2 ,4, 8, 12-14 and 24-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 27, 2026