DETAILED ACTION
This Notice is responsive to communication filed on 06/29/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 06/29/2026 under 37 C.F.R. 1.111 has been entered. Claims 1, 4, 8, 12-14, 24 and 25 remain pending in the application. Claim 2 has been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 1 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053), and further in view of Yu et al. (US 20210066254).
Regarding claim 1, Huang discloses a die module Fig. 4: 400, comprising:
a first die Fig. 4: 401 with a set of first pads Fig. 4: 401HR, a set of second pads Fig. 4: 401LS, and a set of third pads Fig. 4: 401HR’ with surfaces that are substantially coplanar with a surface of a first dielectric layer Fig. 4: 105,
the set of second pads Fig. 4: 401LS laterally between the set of first pads Fig. 4: 401HR and the set of third pads Fig. 4: 401HR’,
wherein the set of second pads Fig. 4: 401LS is a set of dummy pads that is not coupled to a die (para. 0043 teaches “supporters” not electrically connected);
a second die Fig. 4: 200 with a set of fourth pads Fig. 4: 203 with surfaces that are substantially coplanar with a surface of a second dielectric layer (-underfill located beneath 200),
wherein the first pads Fig. 4: 401HR are bonded to the fourth pads Fig. 4: 203 and the first dielectric layer Fig. 4: 105 is bonded to the second dielectric layer (via Fig. 4: 403), and
wherein the second die has a lateral width entirely within a lateral width of the first die; and
a third die Fig. 4: 300 with a set of fifth pads Fig. 4: 303 with surfaces that are substantially coplanar with a surface of a third dielectric layer (underfill located beneath 300),
wherein the third pads Fig. 4: 401HR’ are bonded to the fifth pads Fig. 4: 303 and the first dielectric layer Fig. 4: 105 is bonded to the third dielectric layer (via Fig. 4: 403), and
wherein the third die has a lateral width entirely within the lateral width of the first die.
Yu discloses the following claim limitations not explicitly disclosed by Huang:
wherein the second die Fig. 1: 110 has a lateral width entirely within a lateral width of the first die Fig. 1: 100; and
wherein the third die Fig. 1: 120 has a lateral width entirely within the lateral width of the first die Fig. 1: 100.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Huang’s teachings with Yu’s teachings in order to eliminate issues such as crack and/or delamination from the corners of the first die, by encapsulating the body portion of the first die Fig. 1: 100b, including the top, corner and sides, in an encapsulant Fig. 1: 130.
Regarding claim 13, Yu discloses the die module of claim 1, wherein the first die Fig. 1: 100 comprises through die vias Fig. 1: 105 (para. 0030).
Regarding claim 14, Yu discloses the die module of claim 13, wherein pads Fig. 4A: 108 are coupled to the through die vias Fig. 1: 105 (shown in Fig. 1).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) and Yu et al. (US 20210066254) as applied to claim 1 above, and further in view of Uzoh et al. (US 20250266401).
Regarding claim 4, Uzoh teaches the following claim limitations not explicitly disclosed by Huang or Yu:
The die module of claim 1, wherein corners of the second die Fig. 12: 106 are rounded (para. 0074, “edges of the top die 106 may also be rounded”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Huang with Uzoh for the purpose of preventing point stress concentration during stack fabrication and avoiding cracking or chipping fragile dies (para. 0074).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) and Yu et al. (US 20210066254) as applied to claim 1 above, and further in view of Chen et al. (US 20200286879).
Regarding claim 8, Chen discloses the following claim limitations not explicitly disclosed by Huang or Yu:
the die module of claim 1, further comprising a through die via through a thickness of the second die Fig. 1C: 19a (para. 0069, “Vias such as TSVs, TIVs, TDVs, or the like, or a combination thereof may be formed to electrical connect the dies or devices on the semiconductor package structure 100a to the dies 19a and the wafer 18”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Huang with Chen for the purpose of stacking more layers of dies or devices on the package structure to form a multi-layer stacked chip-on-wafer structure (para. 0069).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) and Yu et al. (US 20210066254) as applied to claim 1 above, and further in view of Budd et al. (US 10,217,637).
Regarding claim 12, Budd discloses the following claim limitations not explicitly disclosed by Huang or Yu:
The die module of claim 1, wherein the first die Fig. 8B: 26 comprises first fiducial marks Fig. 8B: 26A, and wherein the second die Fig. 8B: 34A comprises second fiducial marks Fig. 8B: 34AA that are aligned with the first fiducial marks (col. 11, lines 2-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Huang’s teachings with Budd’s teachings to include fiducial marks in Huang’s die module for the purpose of facilitating proper alignment of these structures (col. 11, lines 2-5).
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053) and Yu et al. (US 20210066254), and further in view of Chen et al. (US 20210091064).
Regarding claim 24, Huang teaches an electronic system, comprising:
a board;
a package substrate Fig. 4: 404 coupled to the board; and
a die module Fig. 4: 400 coupled to the package substrate Fig. 4: 404,
wherein the die module comprises Fig. 4: 400:
a first die Fig. 4: 401 with a set of first pads Fig. 4: 401HR, a set of second pads Fig. 4: 401LS, and a set of third pads Fig. 4: 401HR’ with surfaces that are substantially coplanar with a surface of a first dielectric layer Fig. 4: 105,
the set of second pads Fig. 4: 401LS laterally between the set of first pads Fig. 4: 401HR and the set of third pads Fig. 4: 401HR’,
wherein the set of second pads Fig. 4: 401LS is a set of dummy pads that is not coupled to a die (para. 0043 teaches “supporters” not electrically connected);
a second die Fig. 4: 200 with a set of fourth pads Fig. 4: 203 with surfaces that are substantially coplanar with a surface of a second dielectric layer (underfill located beneath 200),
wherein the first pads Fig. 4: 401HR are bonded to the fourth pads Fig. 4: 203 and the first dielectric layer Fig. 4: 105 is bonded to the second dielectric layer (via Fig. 4: 403), and
wherein the second die has a lateral width entirely within a lateral width of the first die; and
a third die Fig. 4: 300 with a set of fifth pads Fig. 4: 303 with surfaces that are substantially coplanar with a surface of a third dielectric layer (underfill located beneath 300),
wherein the third pads Fig. 4: 401HR’ are bonded to the fifth pads Fig. 4: 303 and the first dielectric layer Fig. 4: 105 is bonded to the third dielectric layer (via Fig. 4: 403), and
wherein the third die has a lateral width entirely within a lateral width of the first die.
Chen discloses the following claim limitations not explicitly disclosed by Huang:
the electronic system Fig. 4B, comprising a board Fig. 4B: 400, a package substrate Fig. 4B: 100 coupled to the board Fig. 4B: 400, and
a die module Fig. 4B: W1 coupled to the package substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s teachings with Chen’s teachings for the purpose of grounding the dies and the package substrate (para 0056).
Yu discloses the following claim limitations not explicitly disclosed by Huang:
wherein the second die Fig. 1: 110 has a lateral width entirely within a lateral width of the first die Fig. 1: 100; and
wherein the third die Fig. 1: 120 has a lateral width entirely within the lateral width of the first die Fig. 1: 100.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Huang’s teachings with Yu’s teachings in order to eliminate issues such as crack and/or delamination from the corners of the first die, by encapsulating the body portion of the first die Fig. 1: 100b, including the top, corner and sides, in an encapsulant Fig. 1: 130.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20240250053), Yu et al. (US 20210066254), and Chen et al. (US 20210091064), and further in view of Uzoh et al. (US 20250266401).
Regarding claim 25, Uzoh discloses the following claim limitations not explicitly disclosed by Huang:
the electronic system of claim 24, wherein corners of the second die Fig. 12: 106 are rounded (para. 0074, “edges of the top die 106 may also be rounded”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Huang, Yu and Chen with Uzoh for the purpose of preventing point stress concentration during stack fabrication and avoiding cracking or chipping fragile dies (para. 0074).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 ,4, 8, 12-14 and 24-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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