DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the at least a portion of the third dielectric layer formed under the third protruding region includes an outside edge that terminates and is self-aligned at an outer edge of the third protruding region closest to the first current-carrying electrode, between the upper opening and the first current- carrying electrode (Re claim 1) and/or at least a portion of the third dielectric layer formed under the third protruding region includes an outside edge that terminates and is self-aligned at an outer edge of the third protruding region closest to the source electrode, between the upper opening and the source electrode (Re claim 11) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-4, 6-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Re claim 1, the phrase “at least a portion of the third dielectric layer formed under the third protruding region includes an outside edge that terminates and is self-aligned at an outer edge of the third protruding region closest to the first current-carrying electrode, between the upper opening and the first current- carrying electrode” was not described in the original specification.
Re claim 11, the phrase “at least a portion of the third dielectric layer formed under the third protruding region includes an outside edge that terminates and is self-aligned at an outer edge of the third protruding region closest to the source electrode, between the upper opening and the source electrode” was not described in the original specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, US 2021/0151592 A1.
Re claim 1. Lee discloses a semiconductor device comprising: a semiconductor substrate 102 comprising an upper surface and a channel (e.g., fig. 4 or 7); a first dielectric layer (e.g., the first layer of 116 that is in direct contact w/108) disposed over the upper surface of the semiconductor substrate (fig. 4 or 7); a second dielectric layer (e.g., the layer in direct contact w/ the first layer) disposed over the first dielectric layer (fig. 4 or 7); a third dielectric layer (e.g., the portion of the uppermost top layer in contact with 114 having the same side continuing profiles as the element 114) disposed over the second dielectric layer (fig. 4 or 7); a lower opening formed in the first dielectric layer (e.g., fig. 4 or 7); a first current- carrying electrode 110 formed over the semiconductor substrate (fig. 4) and electrically coupled to the channel within a first current-carrying opening in the first dielectric layer (fig. 4) and a second current- carrying electrode 112 formed within a second current-carrying opening in the first dielectric layer and electrically coupled to the channel (fig. 4), wherein the first current-carrying electrode and the second current-carrying electrode are configured to support current flow through the channel (fig. 4)an upper opening formed in the second dielectric layer and the third dielectric layer (e.g., fig. 4 or 7), wherein at least a portion of the upper opening overlaps a portion of the lower opening (e.g., fig. 4 or 7); and a control electrode 114 formed within at least a portion of the lower opening and within a portion of the upper opening (e.g., fig. 4 or 7), wherein the control electrode 114 is formed between the first current-carrying electrode 110 and the second current-carrying electrode 112, and wherein a portion of the control electrode is formed over the third dielectric layer (e.g., fig. 4 or 7), wherein the control electrode 114 includes: a first region formed within the lower opening (e.g., fig. 4 or 7), a second region formed above the first region (e.g., fig. 4 or 7), wherein the second region includes a first protruding region extending over the first dielectric layer between the lower opening and the first current-carrying electrode 110 (e.g., fig. 4 or 7) and a second protruding region extending over the first dielectric layer between the lower opening and the second current-carrying electrode 112 (e.g., fig. 4 or 7); and a third region formed above the second region (e.g., fig. 4 or 7), wherein the third region includes a third protruding region extending over the third dielectric layer between the upper opening and the first current-carrying electrode 110 (e.g., fig. 4 or 7), wherein at least a portion of the third dielectric layer formed under the third protruding region includes an outside edge that terminates (e.g., fig. 4 or 7, the portion of the uppermost top layer in contact with 114) and is self-aligned (e.g., fig. 4 or 7 ) at an outer edge of the third protruding region closest to the first current-carrying electrode 110, between the upper opening and the first current- carrying electrode (fig. 4), see figs. 1-13 and pages 1-13 for more details.
Re claim 3. The semiconductor device of claim 2, wherein the control electrode is configured as a gate electrode 114 (fig. 4), the first current-carrying electrode is configured as a source electrode 110, and the second current-carrying electrode is configured as a drain electrode 112 (fig. 4).
Re claim 4. The semiconductor device of claim 3, wherein a fourth dielectric layer 117 (fig. 4 and paragraph 115 etc.) is formed over the gate electrode and a field plate 132 is formed adjacent the gate electrode and over a at least portion of the fourth dielectric layer (fig. 4).
Re claim 6. The semiconductor device of claim 5, wherein the third region of the control electrode includes a fourth protruding region extending over the third dielectric layer between the upper opening and the second current-carrying electrode (i.e, fig. 4).
Re claim 7. The semiconductor device of claim 6, wherein a lateral length of the third protruding region is longer than a lateral length of the fourth protruding region (i.e, fig. 4 or 7).
Re claim 8. The semiconductor device of claim 6, wherein a lateral length of the second protruding region is shorter than a lateral length of the fourth protruding region (i.e, fig. 4 or 7).
Re claim 9. The semiconductor device of claim 1, wherein a dielectric constant of the first dielectric layer (i.e., SiN, see paragraph 114, 132-136) exceeds a dielectric constant of the second dielectric layer (i.e., Silicon dioxide, see paragraph 114, 132-136).
Re claim 10. The semiconductor device of claim 1, wherein the first dielectric layer includes silicon nitride (i.e., SiN, see paragraph 114, 132-136) and the second dielectric layer includes a material selected from the group consisting of silicon dioxide, tetraethyl orthosilicate, organo-silicate glass, and porous silicon dioxide (i.e., SiN, see paragraph 114, 132-136).
Re claim 11. Lee discloses a gallium nitride transistor device comprising: a semiconductor substrate 102 (i.e., fig. 4/7 and paragraph 106) comprising gallium nitride, further comprising an upper surface and a channel (i.e., fig. 4 or 7); a first dielectric layer (i.e., the first layer of 116 which is in direct contact w/108) disposed over the upper surface of the semiconductor substrate (fig. 4 or 7); a second dielectric layer (i.e., the layer in direct contact w/ the first layer) disposed over the first dielectric layer (fig. 4 or 7); a third dielectric layer (e.g., the portion of the uppermost top layer in contact with 114 having the same side continuing profiles as the element 114) disposed over the second dielectric layer (fig. 4 or 7); a source electrode 110 and a drain electrode 112 (fig. 4), configured to support current flow through the channel, formed over the semiconductor substrate within a source opening and a drain opening formed in the first dielectric layer (fig. 4) and electrically coupled to the channel (fig. 4); a lower opening (fig. 4 or 7) formed in the first dielectric layer between the source electrode 110 and the drain electrode 112 (fig. 4); an upper opening formed in the second dielectric layer and the third dielectric layer (fig. 4 or 7), wherein at least a portion of the upper opening overlaps a portion of the lower opening (fig. 4 or 7); and a gate electrode 114 formed over the semiconductor substrate between the source electrode and the drain electrode within at least a portion of the lower opening and within a portion of the upper opening (fig. 4/7), configured to control current flow through the channel, wherein the gate electrode 114 includes: a first gate region formed within the lower opening (fig. 4/7); a second gate region formed above the first gate region (fig. 4/7), wherein the second gate region includes a first protruding region extending laterally over the first dielectric layer between the lower opening and the source electrode (fig. 4) and a second protruding region extending laterally over the first dielectric layer between the lower opening and the drain electrode (fig. 4); and a third gate region formed above the second gate region (fig. 4/7), wherein the third gate region includes a third protruding region that extends over the third dielectric layer between the upper opening and the source electrode (fig. 4), wherein at least a portion of the third dielectric layer (e.g., the portion of the uppermost top layer in contact with 114 having the same side continuing profiles as the element 114) formed under the third protruding region includes an outside edge that terminates and is self-aligned at an outer edge of the third protruding region closest to the source electrode 110 (fig. 4), between the upper opening and the source electrode (e.g. fig. 4 and 7). See figs. 1-13 and pages 1-13 for more details.
Re claim 12. The gallium nitride transistor device of claim 11, wherein the third gate region includes a fourth protruding region extending over the third dielectric layer between the upper opening and the drain electrode (fig. 4).
Re claim 13. The gallium nitride transistor device of claim 11, wherein the second dielectric layer and the third dielectric layer terminate at an end of the third protruding region (fig. 4, i.e., the portion under the gate).
Re claim 14. The gallium nitride transistor device of claim 11, wherein a fourth dielectric layer117 (fig. 4) is formed over at least a portion of the gate electrode, and wherein a field plate 132 is formed over the fourth dielectric layer, adjacent the gate electrode, and between the gate electrode and the drain electrode (fig. 4 i.e., the S/D terminals are interchangeable).
Response to Arguments
Applicant's arguments filed 10/27/2025 have been fully considered but they are not persuasive for reasons herein above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK S CHEN/Primary Examiner, Art Unit 2893
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