Prosecution Insights
Last updated: October 02, 2026

Examiner: CHEN, JACK S J

Tech Center 2800 • Art Units: 2893

This examiner grants 77% of resolved cases

Analysis

Jack S. J. Chen, an examiner in Tech Center 2800, has overseen 576 resolved cases with an allowance rate of 76.7%. This rate in Art Unit 2893 indicates a high likelihood of success for patent applicants. The median time to allowance is 1077 days, providing a predictable timeframe for the prosecution process. Practitioners can use the 1077-day figure to plan their strategy and manage resources effectively over the course of the application's life.

The interview lift of 5.6% provides a measurable increase over the 76.7% base allowance rate. This suggests that while the examiner is already likely to allow a case, an interview can still provide a useful advantage. The 576 resolved cases offer a substantial foundation for these metrics, reinforcing the reliability of the 76.7% allowance rate. The 5.6% lift is a valuable tool for practitioners to consider when navigating the 1077-day median pendency in Tech Center 2800.

For those working in Art Unit 2893, the 76.7% allowance rate and the 1077-day median time to allowance point toward a steady prosecution path. The 576 resolved cases reflect a consistent approach by Examiner Chen. By utilizing the 5.6% interview lift, applicants can further improve their chances of success within the 1077-day window.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

76.7%
Allow Rate
+8.7% vs TC avg
623
Total Applications
+5.6%
Interview Lift
1077
Avg Prosecution Days
Based on 576 resolved cases, 2023–2026

Rejection Statute Breakdown

0.5%
§101 Eligibility
32.3%
§102 Novelty
31.9%
§103 Obviousness
27.3%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18054970 METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL LAYER DEFINING AIR-GAP, AND SEMICONDUCTOR DEVICE Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18463755 SEMICONDUCTOR DEVICE Non-Final OA Toshiba Electronic Devices & Storage Corporation
18466180 VERTICAL GAN POWER TRANSISTOR UNIT CELL, VERTICAL GAN POWER TRANSISTOR AND METHOD FOR PRODUCING A VERTICAL GAN POWER TRANSISTOR UNIT CELL Non-Final OA Robert Bosch GmbH
17919730 ORGANIC SPACER FOR INTEGRATED CIRCUITS Final Rejection Intel NDTM US LLC
17897688 IC FABRICATION FLOW WITH CONTINUOUS DYNAMIC SAMPLING FOR AUTO-VISUAL INSPECTION Non-Final OA TEXAS INSTRUMENTS INCORPORATED
18324897 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE Non-Final OA STMICROELECTRONICS S.r.l.
17941788 SIC-BASED ELECTRONIC DEVICE WITH ENHANCED ROBUSTNESS, AND METHOD FOR MANUFACTURING THE ELECTRONIC DEVICE Non-Final OA STMICROELECTRONICS S.r.l.
17592322 VERTICAL CONDUCTION ELECTRONIC DEVICE COMPRISING A JBS DIODE AND MANUFACTURING PROCESS THEREOF Final Rejection STMicroelectronics S.r.l.
18321239 FERROELECTRIC MEMORY DEVICE WITH SEMICONDUCTOR LAYER Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18316439 THIN FILM TRANSISTOR STRUCTURE Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
17808917 DEPOSITION METHOD FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURE Non-Final OA NANYA TECHNOLOGY CORPORATION
17951438 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING SYSTEM, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM Non-Final OA Kokusai Electric Corporation
18093343 GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED TRENCH SHIELDING REGIONS AND RELATED METHODS Non-Final OA Wolfspeed, Inc.
18613763 THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED WORD LINE CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME Non-Final OA SANDISK TECHNOLOGIES LLC
18798016 WIRING BOARD AND SEMICONDUCTOR DEVICE Non-Final OA SHINKO ELECTRIC INDUSTRIES CO., LTD.
17521076 TRANSISTOR WITH FACETED, RAISED SOURCE/DRAIN REGION Non-Final OA GLOBALFOUNDRIES U.S. Inc.
18222411 GaN TRENCH MOSFET AND FABRICATION METHOD Non-Final OA SixPoint Materials, Inc.

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