DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 20 October 2025 has been entered. Claims 1-21 remain pending in the application. Applicant’s amendments to the specification have overcome the Abstract and specification objections, and the amendments to the claims have overcome the 35 USC 112(b) rejections previously set forth in the Non-Final Office Action mailed 19 May 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites a limited 3-bit normalization “instead of a full normalization”. This is inferentially included and it is unclear if the applicant is positively reciting or functionally reciting performing a full normalization. If the “full normalization” is being functionally recited, it is suggested to use functional terms such as “adapted to be” or “configured for”. If the “full normalization” is being positively recited, it is suggested to first state the full normalization before a “limited 3-bit normalization” is used alternatively to the “full normalization” in the claim. Claims 2-8 inherit the same deficiency by reasons of dependence, and are similarly rejected.
Claim 9 similarly recites a limited 3-bit normalization “instead of a full normalization”. The claim 1 analysis similarly applies to claim 9. Claims 10-15 inherit the same deficiency by reasons of dependence, and are similarly rejected.
Claim 16 similarly recites a limited 3-bit normalization “instead of a full normalization”. The claim 1 analysis similarly applies to claim 16. Claims 17-21 inherit the same deficiency by reasons of dependence, and are similarly rejected.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., an abstract idea) without significantly more.
Regarding claim 1, under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: an apparatus.
Under the Alice Framework Step 2A Prong 1 analysis, claim 1 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“including multiplication of a first factor with a second factor to generate a product and addition of an addend to the product to generate a result;
determine a shift to be applied in the calculation for the FMA instruction;
determine whether a modified operation is applicable to the calculation for the FMA instruction, the determination being based at least in part on the determined shift to be applied in the calculation; and
upon determining that the modified operation is applicable to the calculation for the FMA instruction, perform the modified operation to generate the result for the FMA instruction, wherein to perform the modified operation includes to perform a limited 3-bit normalization instead of a full normalization.”
See specification ([0045-0046], [0373-0374]) describing multiplication of a first factor with a second factor and addition. See specification ([0380]) describing determining a shift. See specification ([0405-0406]) describing determining whether a modified operation is applicable. See specification ([0374], [0382], Fig. 29-30, [0407]) describing performing the modified operation. See specification ([0391]) describing performing the modified operation includes to perform a limited 3-bit normalization. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a cache, a processor coupled with the cache, the processor including circuitry to perform a floating point fused multiply-add (FMA) instruction, the FMA instruction requesting a calculation, and receiving the FMA instruction. A cache, a processor coupled with the cache, the processor including circuitry to perform a floating point fused multiply-add (FMA) instruction is recited at a high level of generality, and is an example of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The cache, a processor coupled with the cache, the processor including circuitry to perform a floating point fused multiply-add (FMA) instruction and the FMA instruction requesting a calculation are examples that merely result in “apply it” on a computer, as mere instructions to apply the abstract idea on a computer (see MPEP 2106.05(f): Mere Instructions to Apply an Exception). The receiving limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites a cache, a processor coupled with the cache, the processor including circuitry to perform a floating point fused multiply-add (FMA) instruction at a high level of generality. This limitation and the FMA instruction requesting a calculation limitation merely result in “apply it” on a computer. The receiving limitation described above as an insignificant extra-solution activity is also well-understood, routine, or conventional (see MPEP 2106.05(d)(II)(i): Receiving or transmitting data over a network). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 1 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 2 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“to perform the modified operation, is to:
mask the addend, the masking being based on the determined shift;
perform an integer multiply and add function to generate a function result;
shift a set of one or more most significant bits (MSBs) of the function result to align with the masked addend; and
perform an OR function with the masked addend and the shifted MSB s to generate an intermediate result.”
See specification ([0371], [0382-0383], [0385]) describing masking. See specification ([0373], [0388]) describing performing an integer multiply and add function. See specification ([0392-0398]) describing shifting. See specification ([0391], [0407]) describing performing an OR function. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis and the Alice Framework Step 2B Analysis, the claim contains no new additional elements that would require consideration. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 2 is ineligible.
Claims 3-7 merely further limits the mathematical concepts and/or mental processes. Claims 3-7 do not recite any new additional elements.
Under the Alice Framework Step 2A Prong 2 analysis, claim 8 recites the
combination of the following additional elements: the processor is a graphical processing unit. This additional element is an example of generic computing elements, and/or merely generally link the use of the abstract idea to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited
above, take alone or in combination, do not amount to significantly more than the
judicial exception. As discussed in the Step 2A Prong 2 analysis, the claim recites the processor is a graphical processing unit at a high level of generality and/or merely generally links the use of the abstract idea to a particular technological environment. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 8 is ineligible.
Claims 9-15 are directed to a method that would be performed by the apparatus of claims 1-7, respectively. The claims 1-7 analysis equally applies, claims 9-15 are similarly rejected.
Claims 16, 18-21 are directed to a system that recites similar limitations to the apparatus of claims 1, 4-7, respectively. The claims 1, 4-7 analysis equally applies, claims 16, 18-21 are similarly rejected.
Additionally, claim 16 includes the following which was not presented in claim 1:
Under the Alice Framework Step 2A Prong 2 analysis, claim 16 recites the
combination of the following additional elements: one or more processors including a graphical processing unit (GPU), and a memory to store data. These additional elements are examples of generic computing elements, and/or merely generally link the use of the abstract idea to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited
above, take alone or in combination, do not amount to significantly more than the
judicial exception. As discussed in the Step 2A Prong 2 analysis, the claim recites one or more processors including a graphical processing unit (GPU) and a memory to store data at a high level of generality and/or merely generally links the use of the abstract idea to a particular technological environment. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 16 is ineligible.
Claim 17 is directed to a system that recites similar limitations to the apparatus of both claims 2-3. The claims 2-3 analysis equally applies, claim 17 is similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 7-9, 12, 15-16, 18, 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0143564 A1 Tannenbaum et al. (hereinafter “Tannenbaum”) in view of US 5943249 A Handlogten (hereinafter “Handlogten”) in view of US 2014/0067895 A1 Wang (hereinafter “Wang”).
Regarding claim 1, Tannenbaum teaches an apparatus comprising:
a processor (Fig. 2, 230, [0030]; Fig. 8, 230, [0060]) including circuitry (Fig. 2, 208(0), 208(1)…208(C-1), [0030]; Fig. 8, 832, [0060]) to perform a floating point fused multiply-add (FMA) instruction ([0030-0031], [0060-0061]), the FMA instruction requesting a calculation including multiplication (Fig. 8, 800, [0067]; Fig. 7, 700, [0051]) of a first factor (Fig. 8, A, [0061]) with a second factor (Fig. 8, B, [0061]) to generate a product (Fig. 8, A*B, [0067]) and addition (Fig. 8, A*B+C) of an addend (Fig. 8, C, [0061]) to the product to generate a result (Fig. 8, A*B+C, [0069-0070]);
wherein, upon receiving the FMA instruction (Fig. 9, 910, [0075]), the processor is to:
determine a shift to be applied in the calculation for the FMA instruction ([0046-0047] shifts based on difference between product’s A*B and addend’s C exponents);
determine whether a modified operation is applicable to the calculation for the FMA instruction (Fig. 9, 915 modified with regards to compliance, [0076-0077]), the determination being based at least in part on the determined shift to be applied in the calculation ([0046] compliance leads to shifting for product or addend as to maintain internal precision); and
upon determining that the modified operation is applicable to the calculation for the FMA instruction (Fig. 9, “yes”, [0076]), perform the modified operation to generate the result for the FMA instruction (Fig. 9, 920, [0076]).
Tannenbaum is silent with disclosing a cache coupled to the processor, and performing a limited 3-bit normalization instead of a full normalization.
Handlogten teaches a cache (Fig. 2 ‘106’ ‘104’, co. 2 ln. 1-15) coupled to the processor (co. 5 ln. 1-37) and a full normalization (co. 8 ln. 45-46).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Tannenbaum’s floating point fused multiply-add apparatus with Handlogten’s cache and full normalization feature because they are in the claimed invention’s same field of endeavor of floating point fused multiply-add (co. 4 ln. 9-16). Tannenbaum generally discloses a memory to store data ([0026], [0038]), but appears to be silent with explicitly disclosing such memory as a cache. By implementing the memory storage as a cache, the modified invention would have better access at manipulating, regulating, and managing the content of data in the cache depending on the objectives of the invention’s design (co. 5 ln. 29-37). By implementing the full normalization, the modified invention would be capable of performing this adjustment on the entirety of the values instead of specific portions, thus ensuring the entirety of the values are being operated on and considered in the computations (co. 3 ln. 43-49; co. 8 ln. 45-46). Making this modification would be beneficial, as Tannenbaum’s apparatus now has support for better data access via the cache and performing on the entire data value via the full normalization feature.
Tannenbaum in view of Handlogten are silent with disclosing performing a limited 3-bit normalization instead.
Wang teaches performing a limited 3-bit normalization instead (Fig. 2, 224, [0045], [0070]; Fig. 9, 916, [0070]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Tannenbaum in view of Handlogten’s floating point fused multiply-add apparatus with Wang’s normalization feature because they are in the claimed invention’s same field of endeavor of floating point fused multiply-add ([Abstract]). Conventional implementations of fused operations typically result in a loss of precision ([0045]). It would have been obvious to one of ordinary skill in the art to implement the normalization feature as it allows Tannenbaum in view of Handlogten’s apparatus to perform calculations of floating-point values while maintaining proper precision as the normalization feature assists with alignment of operands for calculations ([0070], [0049]). Making this modification would be beneficial, as Tannenbaum in view of Handlogten’s apparatus now has support for varying lengths of operands and ensures via normalization that the computations are computed correctly without loss of precision.
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis,
the rejection of claim 1 is incorporated and Tannenbaum teaches wherein the processor (see claim 1 mapping) is further to:
upon determining that the modified operation is not applicable to the calculation for the FMA instruction (Fig. 9, “no”, [0077]), perform a normal FMA operation to generate the result for the FMA instruction (Fig. 9, 925-940, [0077-0080]) that is compliant with a floating-point standard (Fig. 9 ‘915’ [0006], [0075-0077]).
Tannenbaum is silent with disclosing to perform the normal FMA operation includes to perform the full normalization.
Handlogten teaches to perform the full normalization (co. 8 ln. 45-46).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 7, in addition to the teachings addressed in the claim 1 analysis,
the rejection of claim 1 is incorporated and Tannenbaum teaches wherein determining whether the modified operation is applicable to the calculation for the FMA instruction (see claim 1 mapping) is further based on
whether the modified operation is enabled ([0041], mode selector to support IEEE rounding-compliant mode and a non-compliant mode).
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis,
the rejection of claim 1 is incorporated and Tannenbaum teaches wherein the processor (see claim 1 mapping) is
a graphical processing unit (GPU) ([0041] GPU).
Claims 9, 12, 15 are directed to a method that would be performed by the apparatus of claim 1, 4, 7. The claims 1, 4, 7 analysis equally applies, and claims 9, 12, 15 are similarly rejected.
Claims 16, 18, 21 are directed to a system that recites similar limitations to claims 1, 4, 7. The claims 1, 4, 7 analysis equally applies, and claims 16, 18, 21 are similarly rejected. Additionally, in claim 16, Tannenbaum teaches: one or more processors ([0024]) including a graphical processing unit (GPU) ([0041] GPU), and a memory to store data ([0026], [0038]).
Claims 2-3, 5-6, 10-11, 13-14, 17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tannenbaum in view of Handlogten in view of Wang as applied to claims 1, 9, and 10 above, and further view of US 2015/0039662 A1 Iyer et al. (hereinafter “Iyer”).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis,
the rejection of claim 1 is incorporated and Tannenbaum teaches wherein the processor, to perform the modified operation (see claim 1 mapping) is to:
mask the addend (Fig. 4-6, significand C 412, significand C 512, significand C 612, [0047-0050]), the masking being based on the determined shift ([0046]);
perform an integer multiply and add function to generate a function result (Fig. 8, 800; Fig. 7, 700, [0051-0053])
shift a set of one or more most significant bits (MSBs) (Fig. 4-6, high-order bits 404, 504, 604, [0047-0050]) of the function result ([0052-0053] shifting while performing multiply and add function; [0046] shifting related to being compliant) to align with the masked addend (Fig. 4-6, significand C 412, significand C 512, significand C 612, [0047-0050]); and
perform an OR function with the masked addend (see above) and the shifted MSBs (see above) to generate an intermediate result.
Tannenbaum and Handlogten are silent with disclosing masking addend, basing the masking on the shift, and performing an OR function with the masked addend to generate an intermediate result.
Wang teaches masking addend, basing the masking on the shift ([0065] shifting/masking Mx, [0042] where Mx is the mantissa of addend Rx; Fig. 8, 832, 834, [0066]; Fig. 2, 218, [0070]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Tannenbaum in view of Handlogten’s floating point fused multiply-add apparatus with Wang’s masking feature because they are in the claimed invention’s same field of endeavor of floating point fused multiply-add ([Abstract]). Conventional implementations of fused operations typically result in a loss of precision ([0045]). It would have been obvious to one of ordinary skill in the art to implement the masking feature as it allows Tannenbaum in view of Handlogten’s apparatus to perform calculations of floating-point values while maintaining proper precision as the masking feature assists with alignment of operands for calculations ([0041], [0043], [0070]). Making this modification would be beneficial, as Tannenbaum in view of Handlogten’s apparatus now has support for varying lengths of operands and ensures via masking that the computations are computed correctly without loss of precision.
Tannenbaum in view of Handlogten in view of Wang are silent with disclosing performing an OR function with the masked addend to generate an intermediate result.
Iyer teaches performing an OR function (Fig. 3, 310(0), 310(1); Fig. 4, 310(0); Fig. 5, 310(0), 310(1); Fig. 6, 310(1), [0045-0046], [0048-0050]) with the masked addend to generate an intermediate result (Fig. 3, outputs of 310(0), 310(1) into 311; Fig. 4, 311 zeroes; Fig. 5, 311 zeroes; Fig. 6, 310(1) to zeroes; [0045-0046], [0048-0050]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Tannenbaum in view of Handlogten in view of Wang’s floating point fused multiply-add apparatus with Iyer’s OR function feature because they are in the claimed invention’s same field of endeavor of floating point fused multiply-add ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the OR function feature as it allows Tannenbaum in view of Handlogten in view of Wang’s apparatus to perform calculations of floating-point values while maintaining correct computations as the OR function feature assists with processing valid data only ([0048]). Making this modification would be beneficial, as Tannenbaum in view of Handlogten in view of Wang’s apparatus now has support for filtering out invalid data and processing only valid data via the OR function feature, thereby improving efficiency and correctness of computation.
Regarding claim 3, in addition to the teachings addressed in the claim 2 analysis,
the rejection of claim 2 is incorporated and Tannenbaum teaches wherein the processor, to perform the modified operation (see claim 1 mapping), is to:
perform a limited re-normalization of the intermediate result to generate the result for the FMA instruction (see claim 1 mapping).
Tannenbaum and Handlogten are silent with disclosing performing a limited re-normalization of the intermediate results.
Wang teaches performing a limited re-normalization (Fig. 2, 224, [0045], [0070]; Fig. 9, 916, [0070]).
The motivation to combine provided with respect to claim 1 equally applies.
Tannenbaum in view of Handlogten in view of Wang in view of Iyer disclose performing a limited re-normalization of the intermediate results.
Iyer teaches performing a limited re-normalization of the intermediate results (see claim 2 mapping).
The motivation to combine provided with respect to claim 2 equally applies.
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis,
the rejection of claim 1 is incorporated and Tannenbaum teaches wherein determining whether the modified operation is applicable to the calculation for the FMA instruction (see claim 1 mapping).
Tannenbaum and Handlogten are silent with disclosing comparing the determined shift to one or more threshold values.
Wang teaches comparing the determined shift to one or more threshold values (Fig. 3, “Case Description” column, 302, 304, 306, 306a, 306b, 308, Ex, Em, Rm, Rx compared with 3, 24, 47, [0048-0053]; Fig. 4, “Case Description” column, 402, 404, 406, Ex-Em>26 cases, [0054-0057]; Fig. 5, “Case Description” column, 502, 504a, 504b, 506, Ex-Em=26~4 or 3, [0059-0060]; Fig. 6, “Case Description” column, 602, 604a, 604b, [0061-0063]; [0064]) ([0041] where product Rm is referred to as Em, and [0037] Rm is a product of Rs and Rt; [0042] Ex is an exponent part of addend Rx).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Tannenbaum in view of Handlogten’s floating point fused multiply-add apparatus with Wang’s threshold comparison feature because they are in the claimed invention’s same field of endeavor of floating point fused multiply-add ([Abstract]). Conventional implementations of fused operations typically result in a loss of precision ([0045]). It would have been obvious to one of ordinary skill in the art to implement the threshold comparison feature as it allows Tannenbaum in view of Handlogten’s apparatus to perform calculations of floating-point values while maintaining proper precision as the threshold comparison feature assists with alignment of operands for calculations ([0043], [0048-0053], [0054-0057], [0059-0060], [0061-0063]). Making this modification would be beneficial, as Tannenbaum in view of Handlogten’s apparatus now has support for varying lengths of operands and ensures via threshold comparison that the computations are computed correctly without loss of precision.
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis,
the rejection of claim 1 is incorporated and Tannenbaum teaches wherein determining whether the modified operation is applicable to the calculation for the FMA instruction (see claim 1 mapping).
Tannenbuam and Handlogten are silent with disclosing determining that a product of the first factor and the second factor will overlap with a set of least significant bits (LSBs) of the addend.
Wang teaches determining (Fig. 3, “Case Description” column, 302, 304, 306, 306a, 306b, 308, Ex, Em, Rm, Rx compared with 3, 24, 47, [0048-0053]; Fig. 4, “Case Description” column, 402, 404, 406, Ex-Em>26 cases, [0054-0057]; Fig. 5, “Case Description” column, 502, 504a, 504b, 506, Ex-Em=26~4 or 3, [0059-0060]; Fig. 6, “Case Description” column, 602, 604a, 604b, [0061-0063]; [0064]) that a product of the first factor and the second factor will overlap with a set of least significant bits (LSBs) ([0048-0053], [0054-0057], [0059-0060], [0061-0063] using LSB of Ex and the MSB; [0042] Ex is exponent part of addend Rx) of the addend. ([0041] where product Rm is referred to as Em, and [0037] Rm is a product of Rs and Rt; [0042] Ex is an exponent part of addend Rx)
The motivation to combine provided with respect to claim 5 equally applies.
Although Wang is comparing the product and addend values, they are silent with disclosing explicitly determining if overlap occurs.
Tannenbaum in view of Handlogten in view of Wang are silent with disclosing determining if overlap occurs.
Iyer teaches overlaps ([0048-0050]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Tannenbaum in view of Handlogten in view of Wang’s floating point fused multiply-add apparatus with Iyer’s overlap feature because they are in the claimed invention’s same field of endeavor of floating point fused multiply-add ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the overlap feature as it allows Tannenbaum in view of Handlogten in view of Wang’s apparatus to perform calculations of larger length floating-point values while maintaining correct computations as the overlap feature assists with processing valid data only ([0048-0049]). Making this modification would be beneficial, as Tannenbaum in view of Handlogten in view of Wang’s apparatus now has support for filtering out invalid data and processing only valid data via the overlap feature, thereby improving efficiency and correctness of computation.
Claims 10-11, 13-14 are directed to a method that would be performed by the apparatus of claims 2-3, 5-6. The claims 2-3, 5-6 analysis equally applies, and claims 10-11, 13-14 are similarly rejected.
Claims 19-20 are directed to a system that recites similar limitations to claims 5-6. The claims 5-6 analysis equally applies, and claims 19-20 are similarly rejected.
Claim 17 is directed to a system that recites similar limitations to claims 2-3. The claims 2-3 analysis equally applies. Additionally, Tannenbaum teaches the modified operation (Fig. 9, 915 modified with regards to compliance, [0076-0077]) includes the GPU ([0041]).
Response to Arguments
Specification – Abstract. The objections to the abstract have been withdrawn based on the amendments to the abstract.
Specification – Incorporation by Reference. The objections to the specification have been withdrawn based on the submission of the IDS filed 10/21/2025.
35 USC 112(b). The 112(b) rejections have been withdrawn based on the amendments to the claims. A new grounds of rejection is made as necessitated by the amendment.
35 USC 101. Applicant argues the following in substance:
Applicant asserts that, claim 1 is therefore directed at a particular way for the processor to perform the FMA instruction. As described in the specification this particular way of the processor to perform the FMA instruction ( e.g., when the least significant bits of the addend c overlap with the product axb) may allow the processor to perform the FMA instruction with lower power consumption. See e.g., paragraphs [004], [0047], etc. Accordingly, claim 1 is directed at an improvement to the functioning of a computer itself (see Remarks p. 2 para. 2).
Examiner respectfully disagrees. The purported improvements are a direct result of applying the abstract idea, the mathematical concepts and/or mental processes, other than reciting “a cache”, “a processor coupled with the cache, the processor including circuitry to perform a floating point fused multiply-add (FMA) instruction”, “the FMA instruction requesting a calculation”, and “receiving the FMA instruction” there is nothing in the claims element that precludes the steps from practically being performed in the human mind, and/or using pen and paper.
No additional elements and/or combination of additional elements are claimed that result in the purported improvement beyond the mathematical concepts and/or mental processes.
With respect to “lower power consumption” it is the abstract idea, the manner of applying the mathematical relationships and/or mental processes to perform the modified operation for the FMA instruction. See specification para. ([0047]).
See MPEP 2106.05(a)(I). “Examples that the courts have indicated may not be sufficient to show an improvement in computer-functionality”.
See MPEP 2106.05(a)(II). “It is important to keep in mind that an improvement in
the abstract idea itself (e.g. a recited fundamental economic concept) is not an
improvement in technology.”
See also MPEP 2106.05. An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself."
Applicant asserts that, the present claims are not directed to a judicial exception because they also recite additional elements demonstrating that the claim as a whole integrates the exception into a practical application since the claimed invention represents an improvement to the functioning of a computer itself See e.g., MPEP 2106.04(d)(l) (see Remarks p. 2 para. 3).
Examiner respectfully disagrees. The additional elements recited in claims 1, 9, and 16 do not integrate the abstract idea into a practical application because they have been recited at a high level of generality and an example of generic computing elements that merely result in “apply it” on a computer (or equivalent), and/or merely generally linked to a particular technological environment, and/or are examples of insignificant extra-solution activity, mere data gathering.
See MPEP 2106.04(d)(I). “The courts have also identified limitations that did not integrate a judicial exception into a practical application”.
35 USC 102(a)(1) and (a)(2). Applicant’s arguments, see Remarks p. 3 bottom, filed 10/20/2025, with respect to the rejections of claims 1, 9, and 16 under 35 USC 102(a)(1) and (a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Handlogten, as necessitated by the amendment to the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182