Prosecution Insights
Last updated: April 19, 2026
Application No. 17/561,824

STRESS ARREST LIP ON COPPER PAD FOR LOW ROUGHNESS COPPER

Non-Final OA §102§103
Filed
Dec 24, 2021
Examiner
MCCOY, THOMAS WILSON
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Non-Final)
100%
Grant Probability
Favorable
2-3
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
10 granted / 10 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
44 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
55.2%
+15.2% vs TC avg
§102
20.4%
-19.6% vs TC avg
§112
12.4%
-27.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 10 resolved cases

Office Action

§102 §103
Attorney’s Docket Number: AD6429-US Filing Date: 12/24/2021 Inventors: Kong et al. Examiner: Thomas McCoy DETAILED ACTION This Office action responds to the amendments filed on 9/11/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Acknowledgement The Amendment filed on 9/11/2025, responding to the Office action mailed 6/11/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-15. Response to Arguments/Amendment Applicant’s amendments to the claims have failed to overcome the claim rejections under 35 U.S.C. 102 and 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 6/11/2025. The Applicant’s response filed 9/11/2025 argues that Chou fails to disclose a surface that is the same height as the contact surface to which a bond wire will be connected as a vertical lip that extends above the surface of the contact to which a trace will make electrical contact, but this specific arrangement of the contact surface above the metallic contact is not mentioned in the claims. The claim limitation instead recites the dielectric layer over the semiconductor circuit substrate and the metallic contact, which is disclosed within Chou (see, e.g., fig. 5). However, upon further consideration, new grounds of rejection are made in view of 35 U.S.C. 102 and 35 U.S.C. 103. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 8-9, and 14 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Chou (US 20210066225 A1). Regarding claim 1, Chou (see, e.g., fig. 5) shows all aspects of the instant invention including an electronic assembly (e.g., integrated chip 500) comprising: A semiconductor circuit substrate (e.g., carrier substrate 102); A metallic contact (e.g., bond pad 116) integrated onto the semiconductor circuit substrate (e.g., carrier substrate 102), the metallic contact (e.g., bond pad 116) having a contact surface (e.g., contact surface, see included figure) to make electrical contact with a trace through a dielectric layer (e.g., first dielectric layer 120) over the semiconductor circuit substrate (e.g., carrier substrate 102) and over (e.g., note that dielectric layer 120 is disposed over both the substrate and the contact) the metallic contact (e.g., bond pad 116), the metallic contact (e.g., bond pad 116) including a vertical lip (e.g., extended contact portion, see annotated fig. 1) extending vertically into the dielectric layer (e.g., first dielectric layer 120) above the contact surface (e.g., contact surface, see included figure), the vertical lip (e.g., extended contact portion, see annotated fig. 1) including a horizontal feature that extends toward (e.g., note that the horizontal layout of the contact portion extends toward the central portion of bond pad 116) a center of the metallic contact (e.g., bond pad 116). PNG media_image1.png 682 826 media_image1.png Greyscale Annotated Fig. 1 Regarding claim 2, Chou (see, e.g., fig. 5) shows the metallic contact (e.g., bond pad 116) comprises copper (see e.g., paragraph 17 “The bond pad 116 includes an upper conductive body 116a and conductive protrusions 116b underlying the upper conductive body 116a” + paragraph 18 “The upper conductive body 116a comprises … (e.g., aluminum copper)…”). Regarding claim 8, Chou (see, e.g., fig. 5) shows the vertical lip (e.g., extended contact portion) comprises a first vertical lip (e.g., extended contact portion 1, see included figure) and further comprising a second vertical lip (e.g., extended contact portion 2, see included figure) extending vertically into the dielectric layer (e.g., first dielectric layer 120) above the contact surface (e.g., contact surface, see included figure). Regarding claim 9, Chou (see, e.g., fig. 5) shows all aspects of the instant invention including a computer system (e.g., integrated chip 500) comprising: An integrated circuit (see, e.g., paragraph 29 “…application specific integrated circuit…”) processed (see, e.g., paragraph 29 “…the ASIC substrate 301 may be configured as the carrier substrate 102…”) onto a substrate (ASIC substrate 301); A metallic contact (e.g., bond pad 116) integrated onto the semiconductor circuit substrate (e.g., carrier substrate 102), the metallic contact (e.g., bond pad 116) having a contact surface (e.g., contact surface, see included figure) to make electrical contact with a trace through a dielectric layer (e.g., first dielectric layer 120) over the semiconductor circuit substrate (e.g., carrier substrate 102) and the metallic contact (e.g., bond pad 116), the metallic contact (e.g., bond pad 116) including a vertical lip (e.g., extended contact portion, see included figure) extending vertically into the dielectric layer (e.g., first dielectric layer 120) above the contact surface (e.g., contact surface, see included figure), and A trace (e.g., conductive wire 124) to connect (see, e.g., paragraph 18) a package pad (e.g., electrical connector pad 122) to the metallic contact (e.g., bond pad 116); Regarding claim 14, Chou (see, e.g., fig. 5) shows the vertical lip (e.g., extended contact portion) comprises a first vertical lip (e.g., extended contact portion 1, see annotated fig. 1) and further comprising a second vertical lip (e.g., extended contact portion 2, see annotated fig. 1) extending vertically into the dielectric layer (e.g., first dielectric layer 120) above the contact surface (e.g., contact surface, see annotated fig. 1). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3, 6, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Lin (US 9704818 B1). Regarding claim 3, Chou (see, e.g., fig. 5) fails to show the vertical lip comprises a vertical structure having a tapered edge, with the vertical lip becoming larger as the vertical lip extends farther away from the semiconductor circuit substrate. Lin (see, e.g., fig. 9), in a similar device to Chou, teaches a vertical lip (e.g., interconnect structure 106) comprises a vertical structure having a tapered edge, with the vertical lip becoming larger as the vertical lip extends farther away from the semiconductor circuit substrate (note that interconnect structure 106 grows at an angle, increasing in width as it extends away from bond pad 102 and substrate 101). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the bond pad of Chou to include the technical feature of the interconnect structure of Lin, for the purpose of extending the bond pad’s conductive properties and electrically connect the bond pad to other conductive layers (see paragraph 13 of Lin). Regarding claim 6, Chou (see, e.g., fig. 5) fails to show the vertical lip has a scalloped edge. Lin (see, e.g., fig. 9), in a similar device to Chou, teaches a vertical lip (e.g., interconnect structure 106) comprises a vertical structure having a tapered edge, with the vertical lip becoming larger as the vertical lip extends farther away from the semiconductor circuit substrate (note that interconnect structure 106 grows at an angle, increasing in width as it extends away from bond pad 102 and substrate 101). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the interconnect structure of Chou in view of Lin to include the technical feature of a scalloped edge, for the purpose of extending the bond pad’s conductive properties and electrically connect the bond pad to other conductive layers (see paragraph 13 of Lin). Furthermore, it has been held that a mere change in shape of an element is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04(IV)(B). One having ordinary skill in the art would have had success in making this modification because Lin further teaches that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure (see paragraph 25). Regarding claim 10, Chou (see, e.g., fig. 5) fails to show the vertical lip comprises a vertical structure having a tapered edge, with the vertical lip becoming larger as the vertical lip extends farther away from the semiconductor circuit substrate. Lin (see, e.g., fig. 9), in a similar device to Chou, teaches a vertical lip (e.g., interconnect structure 106) comprises a vertical structure having a tapered edge, with the vertical lip becoming larger as the vertical lip extends farther away from the semiconductor circuit substrate (note that interconnect structure 106 grows at an angle, increasing in width as it extends away from bond pad 102 and substrate 101). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the bond pad of Chou to include the technical feature of the interconnect structure of Lin, for the purpose of extending the bond pad’s conductive properties and electrically connect the bond pad to other conductive layers (see paragraph 13 of Lin). Regarding claim 12, Chou (see, e.g., fig. 5) fails to show the vertical lip has a scalloped edge. Lin (see, e.g., fig. 9), in a similar device to Chou, teaches a vertical lip (e.g., interconnect structure 106) comprises a vertical structure having a tapered edge, with the vertical lip becoming larger as the vertical lip extends farther away from the semiconductor circuit substrate (note that interconnect structure 106 grows at an angle, increasing in width as it extends away from bond pad 102 and substrate 101). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the interconnect structure of Chou in view of Lin to include the technical feature of a scalloped edge, for the purpose of extending the bond pad’s conductive properties and electrically connect the bond pad to other conductive layers (see paragraph 13 of Lin). Furthermore, it has been held that a mere change in shape of an element is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04(IV)(B). One having ordinary skill in the art would have had success in making this modification because Lin further teaches that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure (see paragraph 25). Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Lin further in view of Rinne (US 20050215045 A1). Regarding claim 5, Chou in view of Lin fails to teach wherein the vertical lip has a cutout from a photoresist exposed at an acute angle. Rinne (see, e.g., figs. 1-2), in a similar device to Chou in view of Lin, teaches forming a vertical lip (e.g., barrier metal 83 + bump metal 103) has a cutout from a photoresist (e.g., photoresist template 101 + paragraph 29) exposed at an acute angle (see, e.g., figs 1-2). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the photoresist cutout of Rinne within the device of Chou in view of Lin, in order to achieve the expected result of changing the slanted configuration as needed to form the extended protrusion portion of Chen within Lin. Regarding claim 11, Chou in view of Lin fails to teach wherein the vertical lip has an under-etch cutout between a top of the vertical lip and a bottom of the vertical lip or wherein the vertical lip has a cutout from a photoresist exposed at an acute angle. Rinne (see, e.g., figs. 1-2), in a similar device to Chou in view of Lin, teaches forming a vertical lip (e.g., barrier metal 83 + bump metal 103) has a cutout from a photoresist (e.g., photoresist template 101 + paragraph 29) exposed at an acute angle (see, e.g., figs 1-2). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the photoresist cutout of Rinne within the device of Chou in view of Lin, in order to achieve the expected result of changing the slanted configuration as needed to form the extended protrusion portion of Chen within Lin. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Krishnatreya (US 20220102305 A1). Regarding claim 15, Chou (see, e.g., fig. 5) fails to show a multicore host processor coupled to the integrated circuit, a display communicatively coupled to a processor, a network interface communicatively coupled to a processor, or a battery to power the computer system. Krishnatreya (see, e.g., fig. 38), in a similar device to Chou, teaches a multicore host processor (e.g., processing device 1802), a display (e.g., display device 1806) communicatively coupled to a processor, a network interface (e.g., communication chip 1812) communicatively coupled to a processor, and a battery (e.g., battery/power 1814) to power the computer system (e.g., electrical device 1800). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the battery of Krishnatreya to achieve the expected result of providing a power supply to the integrated chip of Chou. Allowable Subject Matter Claims 4, 7, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Dec 24, 2021
Application Filed
Nov 30, 2022
Response after Non-Final Action
Jun 07, 2025
Non-Final Rejection — §102, §103
Sep 11, 2025
Response Filed
Dec 19, 2025
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 10 resolved cases by this examiner. Grant probability derived from career allow rate.

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