Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Request for Continued Examination (RCE) filed on 04/17/2026. Currently, claims 1-15, 17-24 and 26-28 are pending in the application. Claims 1-11 are withdrawn from Consideration. Claim 16 and 25 have been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 and 17 are rejected under 35 U.S.C. 103 as being obvious over Matsumoto (US 5309026 A) in view of Warren et al (US 20120104591 A1).
Regarding claim 12, Figures 1-2 of Matsumoto disclose a method of packaging a semiconductor die (2), the method comprising:
performing a molding process that forms a package structure (1) to enclose the semiconductor die (2) and a bond wire (5), the package structure having a package side (upper side in the Figure 2); and
forming a recess (3) that extends inward from the package side toward a side of the semiconductor die (2), the recess (3) having a bottom that is spaced apart from the side of the semiconductor die (2) and from the bond wire (5), wherein the recess (3) is unfilled and the recess locates over a central portion of the semiconductor die (Figures 1 discloses that the recess 3 are over the central portion on a broadest reasonable interpretation).
Matsumoto does not explicitly teach ablating a portion of the package structure (1) to form the recess (3).
However, Warren is a pertinent art which teaches a method of packaging a semiconductor die, the method comprising: performing a molding process that forms a package structure (1500, [0047]) to enclose the semiconductor die (1502, [0047]) and a bond wire (shown between 1502 to 1510), the package structure having a package side (upper side in the Figure 15); and
ablating (Figure 10) a portion of the package structure to form a recess (1002, [0043]) that extends inward from the package side toward a side of the semiconductor die, the recess (at 1504, Figure 15) having a bottom that is spaced apart from the side of the semiconductor die and from the bond wire.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use a recessing process such as ablating in the method of Matsumoto according to the teaching of Warren for an improved method with lower coast, and further, it has been held that choosing from a finite number of identified, predictable solutions such as ablating method to form recess, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 17, Figure 2 of Matsumoto discloses a method of fabricating an electronic device (1), the method comprising:
attaching a semiconductor die (2) to a supporting structure (4);
coupling a bond wire (5) to a side of the semiconductor die;
performing a molding process that forms a package structure (1) to enclose the semiconductor die and the bond wire, the package structure having a package side (upper side in the Figure 2); and forming a recess (3) that extends inward from the package side toward the side of the semiconductor die (2), the recess having a bottom that is spaced apart from the side of the semiconductor die (2) and from the bond wire (5), wherein the recess is unfilled and the recess locates over a central portion of the semiconductor die (Figures 1 discloses that the recess 3 are over the central portion on a broadest reasonable interpretation).
Matsumoto does not explicitly teach ablating a portion of the package structure (1) to form the recess (3).
However, Warren is a pertinent art which teaches a method of packaging a semiconductor die, the method comprising: performing a molding process that forms a package structure (1500, [0047]) to enclose the semiconductor die (1502, [0047]) and a bond wire (shown between 1502 to 1510), the package structure having a package side (upper side in the Figure 15); and
ablating (Figure 10) a portion of the package structure to form a recess (1002, [0043]) that extends inward from the package side toward a side of the semiconductor die, the recess (at 1504, Figure 15) having a bottom that is spaced apart from the side of the semiconductor die and from the bond wire.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use a recessing process such as ablating in the method of Matsumoto according to the teaching of Warren for an improved method with lower coast, and further, it has been held that choosing from a finite number of identified, predictable solutions such as ablating method to form recess, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Claims 12-15, 17-24 and 26-28 are rejected under 35 U.S.C. 103 as being obvious over Warren et al (US 20120104591 A1) in view of Matsumoto (US 5309026 A).
Regarding claim 12, Figures 6-15 of Warren disclose a method of packaging a semiconductor die, the method comprising:
performing a molding process that forms a package structure (1500, [0047]) to enclose the semiconductor die (1502, [0047]) and a bond wire (shown between 1502 to 1510), the package structure having a package side (upper side in the Figure 15); and
ablating (Figure 10) a portion of the package structure to form a recess (1002, [0043]) that extends inward from the package side toward a side of the semiconductor die, the recess (at 1504, Figure 15) having a bottom that is spaced apart from the side of the semiconductor die and from the bond wire, and the recess locates over a central portion of the semiconductor die.
Warren does not explicitly teach that the recess is unfilled.
However, Matsumoto is a pertinent art which teaches an integrated circuit device having reduced stress concentration on the IC chip for prevention of package cracks in the device. Recessed portions (3, Figure 2) are formed in the package at positions corresponding to at least the corner portions of the IC chip to reduce the stress concentration generated at the corner portions of the IC chip (Abstract).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use some unfilled recess in the device of Warren according to the teaching of Matsumoto in order to reduce stress (Abstract of Matsumoto).
Regarding claim 14, Figures 6-15 of Warren disclose that the method of claim 12, wherein the recess has a depth from the package side to the bottom is 50 μm or more ([0034]).
Regarding claim 15, Figures 6-15 of Warren disclose that the method of claim 12, wherein the package structure has a second spacing thickness between the bottom and the bond wire of 25 um or more ([0034], based on Figure considering the depth of recess).
Regarding claim 17, Figures 6-10 of Warren disclose a method of fabricating an electronic device, the method comprising:
attaching a semiconductor die (602, Figure 6) to a supporting structure (606);
coupling a bond wire (802, Figure 8) to a side of the semiconductor die;
performing a molding process (Figure 9) that forms a package structure to enclose the semiconductor die and the bond wire, the package structure having a package side (upper side in the Figure); and
ablating (Figure 10) a portion of the package structure to form a recess (1002, [0043]) that extends inward from the package side toward the side of the semiconductor die, the recess having a bottom that is spaced apart from the side of the semiconductor die and from the bond wire (802), and the recess locates over a central portion of the semiconductor die.
Warren does not explicitly teach that the recess is unfilled.
However, Matsumoto is a pertinent art which teaches an integrated circuit device having reduced stress concentration on the IC chip for prevention of package cracks in the device. Recessed portions (3, Figure 2) are formed in the package at positions corresponding to at least the corner portions of the IC chip to reduce the stress concentration generated at the corner portions of the IC chip (Abstract).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use some unfilled recess in the device of Warren according to the teaching of Matsumoto in order to reduce stress (Abstract of Matsumoto).
Regarding claims 13 and 18, Figures 6-15 of Warren in view of Matsumoto does not explicitly teach that the method of claim 12, wherein the package structure has a spacing thickness between the bottom and the side of the semiconductor die of 25 um or more. Or
Figures 6-10 does not teach that the method of claim 17, wherein the package structure has a spacing thickness between the bottom and the side of the semiconductor die of 25 um or more.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to provide effective heat dissipation ([0004]-[0006]) since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 19, Figures 6-15 of Warren disclose that the method of claim 17, wherein the recess (1002) has a depth from the package side to the bottom of 50 μm or more ([0034]).
Regarding claim 20, Figures 6-15 of Warren disclose that the method of claim 17, wherein the package structure has a second spacing thickness between the bottom and the bond wire of 25 um or more ([0034], based on Figure considering the depth of recess).
Regarding claim 21, Figures 6-15 of Warren disclose that the method of claim 12, wherein the package structure further comprises a second recess having a second bottom that is spaced apart from the side of the semiconductor die and from the bond wire, the second recess having the first depth (Warren teaches plurality of recess with different depth wherein deeper trenches are formed on the middle portion of the semiconductor die).
Regarding claim 22, Figures 6-15 of Warren discloses that the method of claim 21, wherein the second recess extends over another portion the semiconductor die (Figure 15 of Warrant taches that the deeper trenches are formed on the middle portion of the semiconductor die but shallow one is formed on the peripheral region of the semiconductor die).
Regarding claim 23, Figures 6-15 of Warren disclose that the method of claim 21, wherein the second recess has a depth from the package side to the second bottom of 50 um or more ([0034] of Warren).
Regarding claim 24, Figures 6-15 of Warren discloses that the method of claim 17, wherein the package structure further comprises a second recess having a second bottom that is spaced apart from the side of the semiconductor die and from the bond wire (Warren teaches plurality of recess with different depth wherein deeper trenches are formed on the middle portion of the semiconductor die).
Regarding claim 26, Figures 6-15 of Warren disclose that the method of claim 24, wherein the first depth from the package side to the second bottom is 50 um or more ([0034] of Warren).
Regarding claim 27, Figures 6-15 of Warren discloses that the method of claim 24, wherein the second recess locates over another portion the semiconductor die (Warren teaches plurality of recess with different depth at different location over the die).
Regarding claim 28, Figures 6-15 of Warren do not explicitly teach that the method of claim 12, wherein the recess is configured to reduce stress on an active circuitry of the semiconductor die.
However, the above limitation does not distinguish the present invention over the prior art of Warren in view of Matsumoto which teaches the structure as claimed and the material as specified in the applicant specification, wherein the structure is capable of performing the above function. Moreover, it has been held that claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Further, The Examiner notes that where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. (In re Swinehart and Sfiligoj, 169 USPQ 226 (C.C.P.A. 1971)).
Response to Arguments
Applicant's arguments filed on 04/17/2026 have been fully considered but they are not persuasive.
Applicant’s main argument regarding claims 12 and 17 includes: The prior arts of record do not teach that the recess locates over a central portion of the semiconductor die.
In response, the Examiner respectfully points out that because applicant has the opportunity to amend the claims during prosecution, giving a claim its broadest reasonable interpretation will reduce the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989). (“During patent examination the pending claims must be interpreted as broadly as their terms reasonably allow.”); < In re Prater, 415 F.2d 1393, 1404-05, 162 USPQ 541, 550-51 (CCPA 1969). In this case the amended limitation “the recess locates over a central portion of the semiconductor die” is given to its broadest reasonable interpretation by considering that the recess being over the top surface of the semiconductor die meets the limitation since the claim does not explicitly recite that the recess has to be directly over the central portion of the semiconductor die, and also the central portion is not defined by its boundary too. Thus, the amended limitation does not overcome the current prior arts of records.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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