DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 14 January 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-11, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipates by Lim, US Patent 9,236,501 (as cited in previous Office Action)
Regarding claim 1, Lim teaches a semiconductor device comprising:
a substrate 101 including a cell array region “I” and a cell array edge region “ii”,
a device isolation layer 103 formed in the substrate;
a hard mask layer 105 former over the device isolation layer;
a plurality of bit line structures formed over the cell array region (Labeled “BL” in figure 2 and 122/131/133/132 in figure 3) and the cell array edge region (Labeled “DBL” in figure 2 and 150 in figure 3) of the substrate;
a multi-layered bit line spacer (two layers of 141a in figure 3 (i) or 136/141 in figure 3 (ii)) contacted to sidewalls of the bit line structures;
a stopper structure 118/ portions of 141a on surface or 118/145b formed over the hard mask layer in the cell array edge region of the substrate;
a plurality of storage node contact plugs 145a formed between the bit line structures of the cell array region; and
a plurality of dummy plugs 145b formed between sidewalls of the bit line structures on the stopper structure
wherein the stopper structure 105/118 is formed between the substrate and the dummy plug, wherein a bottom surface of the dummy plug 147/149 is disposed at a higher level than a bottom surface of the storage node contact plugs,
wherein the multi-layered bit line spacer includes a first spacer 141a contacting the sidewalls of the bit line structures,
wherein the stropper structure includes a first stopper 118 or portions of 141a on surface or 118 formed over the hard mask layer and a second stopper structure (portion of 141a that is on the surface of 118 or 145b) formed over the first stopper,
whereinthe first spacer and the first stopper have a same thickness (which is when both layers are made of 136 or first 141a. See figure 3(i)).
Regarding claim 3, Lim teaches the stopper structure includes silicon nitride, silicon oxide, or a combination thereof (column 4, lines 28-29).
Regarding claim 5, Lim teaches the multi- layered spacer and the stopper structure include a same material (which is nitride, see column 4, lines 28-29, which teaches stopper 125 made of silicon oxynitride and column 6, lines 12-13 teaches 136 as a nitride)
Regarding claim 6, Lin teaches the bit line structures include a stack structure of a bit line contact plug 122, a bit line 133 formed on the bit line contact plug, and a bit line hard mask 132 formed on the bit line (figure 3).
Regarding claims 7-8, Lim teaches the first spacer 136 or 141a (on sidewalls of 131/133/132) covers a sidewall of the bit line contact plug and a sidewall of the bit line; wherein the semiconductor device further includes; a gap-fill spacer (141a on sidewalls of 122) disposed on the first spacer over both sidewalls of the bit line contact plug; and a second spacer 141a disposed on the first spacer and covering both sidewalls of the bit line, and wherein the stopper structure and the gap-fill spacer include a same material wherein the gap-fill spacer and the stopper structure include silicon nitride (which is nitride, see column 4, lines 28-29, which teaches stopper 125 made of silicon oxynitride and column 6, lines 12-13 teaches 136 as a nitride)
Regarding claim 9, Lim teaches the storage node contact plugs and the dummy plug include polysilicon (column 6, lines 33-41).
Regarding claims 10 and 11, Lim teaches plug isolation layers 141a/141b between the bit line structures, wherein the storage node contact plug and the dummy plug are disposed between the plug isolation layers (figure 3), wherein the plug isolation layers include silicon nitride (column 6, line 21).
Regarding claim 20, Lim teaches the second stopper 145a is thicker than the first stopper portion of 141a that is on the surface of 118 (figure 3).
Allowable Subject Matter
Claims 12-17 and 19 are allowed. The following is an examiner’s statement of reasons for allowance:
Regarding claim 12, the prior art fails to anticipate or render obvious the claimed invention including “...filling a line pattern in each of the line-shaped openings over the stopper structure; forming a plurality of contact plugs and a plurality of isolation grooves by etching the line patterns; and filling a plug isolation layer in the isolation grooves, wherein the substrate includes a cell array region and a cell array edge region, wherein the contact plugs include a plurality of storage node contact plugs formed over the cell array region and a plurality of dummy plugs over the cell array edge region, and wherein the stopper structure is formed between the substrate and the plurality of dummy plug...” in combination with the remaining limitations. Claims 14-17 and 18 are dependent upon claim 12 and are therefore allowable.
Regarding claim 13, the prior art fails to anticipate or render obvious the claimed invention including “...filling a plug isolation layer in the isolation grooves, wherein the forming of the stopper structure includes: forming a spacer layer on the bit line structures; forming a mask layer covering the edges of the line-shaped openings on the spacer layer; and etching the spacer layer by using the mask layer for forming the stopper structure remaining on the edges of the line-shaped openings....” in combination with the remaining limitations.
With regards to independent claims 12 and 13, the cited prior art(s) of record teach all of the limitations presented, but fail to recite the limitation above. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 12-17 and 19 have been found to be allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 14 July 2026 have been fully considered but they are not persuasive.
In response to the argument on page 14 of Applicant’s remarks that states that the first storage node contact spacer 141a of Li does not contact the bit line structures 122/131/133/132, it is noted that figure 3(i) of Lim denotes two different sidewall spacer layers 141a, as shown in figure below. Lim also teaches that 136 is a spacer layer and is the same layer as 141a in figure 3(i). As shown in figure 3(i), in the memory cell area, 136(141a) does contact the bit-line structure 122/131/133/132. Further, in figure 3(ii), it is noted that spacer 136 does contact bitline structure 131/133/132. Therefore, the reference of Lim does meet the limitation “a mult-layered bit line spacer contacted to the sidewalls of the bitline structures” since 136 (first 141a) contacts the bitline structure 122/131/133/132 and second 141a contacts 136(141a)
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In response to the argument on page 14 of Applicant’s remarks that states the combination of 105/118 if Lim does not correspond to the first stopper structure, this rejection has been changed in view of the amendment. Lim does teach hard mask layer 105 (as referenced by Lim). In this instance, however, first stopper structure is capping nitride layer 118. Further, the second stopper structure is portion of 136 (or 141a) that is on the top surface of 118. Therefore, the reference of Lim still meets the limitation of this claim.
In response to arguments on pages 16-18 regarding the limitation of “the first spacer and the first stopper have a same thickness”, Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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QVJ
/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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