Prosecution Insights
Last updated: August 06, 2026
Application No. 17/563,493

PROGRAMMABLE ANALOG SIGNAL PROCESSING ARRAY FOR TIME-DISCRETE PROCESSING OF ANALOG SIGNALS

Non-Final OA §112
Filed
Dec 28, 2021
Priority
Dec 30, 2020 — EU 20217781.2 +1 more
Examiner
VILLANUEVA, MARKUS ANTHONY
Art Unit
2151
Tech Center
2100 — Computer Architecture & Software
Assignee
Ihp GmbH - Innovations For High Performance Microelectronics / Leibniz-Institut Fur Innovative Mikro
OA Round
3 (Non-Final)
58%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
31 granted / 53 resolved
+3.5% vs TC avg
Strong +37% interview lift
Without
With
+37.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 12m
Avg Prosecution
18 currently pending
Career history
83
Total Applications
across all art units

Statute-Specific Performance

§101
24.4%
-15.6% vs TC avg
§103
40.1%
+0.1% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
22.3%
-17.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 53 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The abstract of the disclosure is objected to because it exceeds the 150-word limit, at 191 words, and the 15 lines of text limit. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). The disclosure is objected to because it contains this informality: the analog multiplier element and memristor are both referred to as “804” in Pg. 26, lines 33-35; Pg. 27, lines 1-6. Appropriate correction is required. Claim Objections Claim 13 is objected to because of the following informalities: “macro cell” is recited in this claim, however, it was previously recited in claim 10 as “macrocell”. This inconsistency makes it uncertain whether they are separate elements or the same element. Appropriate correction is required. Claim Construction Regarding claim 1, the preamble is given patentable weight. Claim 1 contains the limitation “the analog input signals”, “the analog output signals”, and “the signal processing function” in the body, which is referring to the limitations as recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of a programmable analog processing array for programmable time-discrete processing. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight. Claim Interpretation As necessitated by the amendments to the claims, the interpretation provided by 35 USC 112(f) or pre-AIA 35 USC 112, sixth paragraph, is not invoked. The claims are interpreted under the broadest reasonable interpretation and given their plain meaning. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the respective delay elements”, “the respective multiplier element”, and “respective adder element”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the circuit-implemented delay element”, “the analog-circuit multiplier element”, “the analog-circuit adder element”, respectively, or a new component. Claims 2-17 inherit the same deficiency by reasons of dependence. Claim 2 recites the limitation "the delay element", “the analog multiplier element”, and “the analog adder element”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if these instances are meant to refer antecedently to “the circuit-implemented delay element”, “the analog-circuit multiplier element”, and “the analog-circuit adder element”, respectively, or if these instances are meant to refer to new circuit components. Claims 3 and 14 inherit the same deficiency by reasons of dependence. Claim 4 recites the limitation "configuration control unit". There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the processor-implemented configuration control unit”, or if this instance is meant to refer to new circuit components. Claims 8 and 15 inherit the same deficiency by reasons of dependence. Claim 6 recites the limitation “the multiplier element”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the analog-circuit multiplier element”, “the multiplier elements”, or refer to new circuit components. Claims 7 and 17 inherit the same deficiency by reasons of dependence. Claim 7 recites the limitation "configuration control unit", “multiplier elements”, “respective multiplier element”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the processor-implemented configuration control unit”, “analog-circuit multiplier element”, or if this instance is meant to refer to new circuit components. Claim 8 recites the limitation "configuration control unit", “multiplier elements”, and “respective multiplier elements”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the processor-implemented configuration control unit”, “analog-circuit multiplier element”, or if this instance is meant to refer to new circuit components. Claim 9 recites the limitation “the resample elements” and “respective multipliers”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the analog-circuit resample element”, “analog-circuit multiplier element”, or a new component. Claim 10 recites the limitation "configuration control unit". There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the processor-implemented configuration control unit”, or if this instance is meant to refer to new circuit components. Claim 12 recites the limitation “the delay element”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the circuit-implemented delay element” or a new component. Claim 13 recites the limitation “the delay element”. There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the circuit-implemented delay element” or a new component. Claim 14 recites the limitation "configuration control unit". There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the processor-implemented configuration control unit”, or if this instance is meant to refer to new circuit components. Claim 16 recites the limitation "multiplier element". There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the analog-circuit multiplier element”, or if this instance is meant to refer to new circuit components. Claim 17 recites the limitation "multiplier element", “respective multiplier elements”, and "configuration control unit". There is insufficient antecedent basis for this limitation in the claim. It is unclear if this instance is meant to refer antecedently to “the analog-circuit multiplier element”, “the processor-implemented configuration control unit”, or if this instance is meant to refer to new circuit components. Allowable Subject Matter In light of the amendments to the claims which no longer invoke the 112(f) interpretation, the reasons for allowance has been updated as previously stated in the Office Action filed 06/30/2025. Claims 1- 17 are rejected, but would be allowable if rewritten to overcome the 35 USC 112(b) rejection. Regarding claim 1, the prior art of record does not teach or suggest a combination of the entire claim limitations in combination with the dependent limitations. Aspects of the claimed invention were found in the prior art, however, not each limitation in combination as specified. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1, with respect to the circuit-implemented delay element, the processor-implemented configuration control unit, and the specific details of the bus, such as the pre-configurable analog signal bus and the configuration-signal bus. The closest prior art found is US 20210081175 A1 Song et al. (hereinafter “Song”). Song discloses an analog-circuit multiplier (Fig. 3, “Analog Multiplier”, [0052]) with a schematic representation (Fig. 15, [0085]; Fig. 16, [0089]; Fig. 17, [0091]; Fig. 18, [0097]; Fig. 19, [0105]; Fig. 20, [0113]; Fig. 21, [0116]; Fig. 22, [0118]) and an analog-circuit adder (Fig. 3, “Analog Adder”, [0052]). Song further teaches a bus for inputting and outputting (Fig. 3 and Fig. 5, D_IN_BUS, D_OUT_BUS, [0052-0053], [0055]). Song, however, is silent with disclosing the circuit-implemented delay element, the processor-implemented configuration control unit, and the specific details of the bus, such as the pre-configurable analog signal bus and the configuration-signal bus. It is the particular arrangement of the circuitry and the specific details of the circuitry which distinguishes from the prior art of record. US 20200410040 A1 Lee (hereinafter “Lee”) discloses a computing control circuit that configures the circuit based on the operation mode (Fig. 3, 500; [0028-0032]). Lee also teaches a sampling capacitor and sampling switch (Fig. 9, 411, [0096-0097]). Lee, however, is silent with disclosing the circuit-implemented delay element, the processor-implemented configuration control unit, and the specific details of the bus, such as the pre-configurable analog signal bus and the configuration-signal bus. US 20190042199 A1 Sumbul et al. (hereinafter “Sumbul”, as cited in the IDS filed 12/28/2021) discloses analog processors (Fig. 10A, 1002A, 1002B, [0054]) connected to ADC (Fig. 10A, 1006A, 1006B, [0054]). Sumbul generally teaches using a bus ([0029], [0080]). Sumbul, however, is silent with disclosing the circuit-implemented delay element, the processor-implemented configuration control unit, and the specific details of the bus, such as the pre-configurable analog signal bus and the configuration-signal bus. Response to Arguments Specification. The objections are maintained; however, Applicant has not addressed this matter. Claims Objections. The objections are maintained; however, Applicant has not addressed this matter. 35 USC 112(a). The rejection is withdrawn based on the amendment to the claims. 35 USC 112(b). The rejection is withdrawn based on the amendment to the claims. 35 USC 112(d). The rejection is withdrawn based on the amendment to the claims. 35 USC 112(f). As necessitated by the amendment to the claims, the interpretation given under the 35 USC 112(f) invocation is no longer provided. The claims are interpreted under the broadest reasonable interpretation and given their plain meaning. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151 /James Trujillo/Supervisory Patent Examiner, Art Unit 2151
Read full office action

Prosecution Timeline

Dec 28, 2021
Application Filed
Jun 30, 2025
Non-Final Rejection mailed — §112
Oct 22, 2025
Response Filed
Dec 04, 2025
Final Rejection mailed — §112
May 26, 2026
Request for Continued Examination
May 29, 2026
Response after Non-Final Action
Jun 18, 2026
Non-Final Rejection mailed — §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
58%
Grant Probability
96%
With Interview (+37.1%)
3y 12m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 53 resolved cases by this examiner. Grant probability derived from career allowance rate.

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