DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1-2 and 4 in the Applicant’s response dated 4 May 2026. The claim amendments have been addressed below.
The Examiner acknowledges the cancellation of claims 3 and 8-20 in the Applicant’s response dated 4 May 2026.
The Examiner acknowledges the addition of new claims 21-34 in the Applicant’s response dated 4 May 2026. The new claims have been addressed below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 28 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pei-Hsun Wang et al. (US 2021/0167218 A1; hereinafter “Wang”).
Regarding Claim 28, Wang teaches a gate-all-around device, comprising
a source/drain (250, Fig. 13A, para [0026] describes epitaxial S/D features 250) on a substrate (202, Fig. 13A, para [0016] describes a substrate 202);
an isolation liner wrapped around the source/drain, where the isolation liner separates the source/drain from the substrate (242, Fig. 13A, para [0042] describes an inner spacer 242 which can be seen wrapped around S/D features 250 and separating the S/D features from the substrate 202);
shallow trench isolation (STI) regions in the substrate (208, Fig. 13B, para [0018] describes isolation structures 208 which may be a shallow trench isolation (STI) structure), wherein the isolation liner covers the STI regions (242 and 208, Fig. 13B, para [0042] describes wherein the isolation liner 242 covers the STI regions 208); and
one or more nanosheet channel sections electrically connected to the source/drain (204A, Fig. 13A, para [0020] describes semiconductor layer 204A which is electrically connected to S/D features 250).
Regarding Claim 30, Wang teaches the gate-all-around device of claim 28, wherein the source/drain extends laterally over the STI regions (250 and 208, Fig. 13B, para [0042] describes source/drain regions 250 which can be seen laterally extending over the STI regions 208).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 21 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Zhenxing Bi et al. (2020/0119015 A1; hereinafter “Bi”) in view of Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”).
Regarding Claim 1, Bi teaches a gate-all-around device, comprising
a source/drain (290, Fig. 19, para [0097] describes source/drain layers 290);
an isolation liner wrapped around the source/drain (320, Fig. 19, para [0103] describes an interlayer dielectric layer 320 which can be seen wrapping around source/drain region 290 in Fig. 19), where the isolation liner separates the source/drain from the substrate (110, Fig. 19, para [0035] describes a substrate 110 which can be seen separated from source/drain regions 290 by isolation liner 320 in gap region 293); and
one or more nanosheet channel sections electrically connected to the source/drain (137 and 177, Fig. 19, para [0094] describes semiconductor channel sheets 137 and 177 which can be seen electrically connected to source/drain regions 290), wherein a surface of the isolation liner below the source/drain shares a vertical plane with the one or more nanosheet channel sections (VP, annotated Fig. 19 depicts wherein portions of the isolation liner ILB below the source/drain regions 290 share a vertical plane VP with nanosheet channel sections 137 and 177) and the isolation liner is disposed horizontally between more than one of the one or more nanosheet channel sections (ILB, annotated Fig. 19 depicts wherein portions of the isolation liner ILB are disposed horizontally between one or more adjacent nanosheet sections 137 and 177).
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Bi fails to explicitly disclose shallow trench isolation (STI) regions in the substrate, wherein the isolation liner covers the STI regions .
However, Yi teaches a similar gate-all-around device comprising shallow trench isolation (STI) regions in the substrate (105, Fig. 3F, para [0024] describes a device isolation layer 105 disposed on portions of a substrate 101), wherein the isolation liner covers the STI regions (105, Fig. 3F, para [0024] describes the shallow trench isolation regions 105 wherein upon combining the isolation liner 320 of Bi with the shallow trench isolation regions 105 of Yi, the isolation liner 320 of Bi can be seen covering surfaces of substrate 110 wherein the shallow trench isolation regions 105 of Yi would be disposed).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Bi with Yi to further disclose a gate-all-around device comprising shallow trench isolation regions in the substrate wherein an isolation liner covers the STI regions in order to provide the advantage of providing isolation regions which may define active regions (Yi, para [0024]) wherein multiple gate-all-around transistors may be formed adjacent to one another while preventing current leakage due to the presence of the STI regions resulting in increased throughput in the gate-all around device manufacturing process.
Regarding Claim 21, Bi teaches a gate-all-around device, comprising
a source/drain (290, Fig. 19, para [0097] describes source/drain layers 290);
an isolation liner wrapped around the source/drain (320, Fig. 19, para [0103] describes an interlayer dielectric layer 320 which can be seen wrapping around source/drain region 290 in Fig. 19), where the isolation liner separates the source/drain from the substrate (110, Fig. 19, para [0035] describes a substrate 110 which can be seen separated from source/drain regions 290 by isolation liner 320 in gap region 293); and
one or more nanosheet channel sections electrically connected to the source/drain (137 and 177, Fig. 19, para [0094] describes semiconductor channel sheets 137 and 177 which can be seen electrically connected to source/drain regions 290), wherein a surface of the isolation liner below the source/drain shares a vertical plane with the one or more nanosheet channel sections (VP, annotated Fig. 19 depicts wherein portions of the isolation liner ILB below the source/drain regions 290 share a vertical plane VP with nanosheet channel sections 137 and 177).
Bi fails to explicitly disclose shallow trench isolation (STI) regions in the substrate, wherein the isolation liner covers the STI regions .
However, Yi teaches a similar gate-all-around device comprising shallow trench isolation (STI) regions in the substrate (105, Fig. 3F, para [0024] describes a device isolation layer 105 disposed on portions of a substrate 101), wherein the isolation liner covers the STI regions (105, Fig. 3F, para [0024] describes the shallow trench isolation regions 105 wherein upon combining the isolation liner 320 of Bi with the shallow trench isolation regions 105 of Yi, the isolation liner 320 of Bi can be seen covering surfaces of substrate 110 wherein the shallow trench isolation regions 105 of Yi would be disposed).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Bi with Yi to further disclose a gate-all-around device comprising shallow trench isolation regions in the substrate wherein an isolation liner covers the STI regions in order to provide the advantage of providing isolation regions which may define active regions (Yi, para [0024]) wherein multiple gate-all-around transistors may be formed adjacent to one another while preventing current leakage due to the presence of the STI regions resulting in increased throughput in the gate-all around device manufacturing process.
Regarding Claim 34, the combination of Bi and Yi teach the gate-all-around device of claim 1, wherein the source/drain extends laterally over the STI regions (Yi, SD and 105, Fig. 3F, para [0026] describes source/drain regions SD that extend laterally over the STI regions 105 as shown in Fig. 3F).
Claims 2, 4-7 and 22-27 are rejected under 35 U.S.C. 103 as being unpatentable over Zhenxing Bi et al. (2020/0119015 A1; hereinafter “Bi”) in view of Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”) and in further view of Kangguo Cheng et al. (US 2020/0295198 A1; hereinafter “Cheng”).
Regarding Claim 2, the combination of Bi and Yi teaches the gate-all-around device of claim 1, further comprising:
an active gate structure on the one or more nanosheet channel sections (Bi, 330, 335 and 337, Fig. 19, para [0104] describes wherein an active gate structure can be formed on the nanosheet channel sections 137 and 177 including a gate dielectric 330, work function layer 335 and a conductive gate fill 337), wherein the active gate structure wraps around at least a portion of the one or more nanosheet channel sections (Bi, para [0109] describes wherein the active gate structure comprising the gate dielectric 330, work function layer 335 and conductive gate fill 337 can wrap around the nanosheet cannel sections 137 and 177).
Bi and Yi fail to teach a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain.
However, Cheng teaches a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain (134, Fig. 20, para [0106] describes forming source/drain contacts 134 that pass through a contact opening of the isolation layer 132).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bi and Yi with Cheng to further disclose a gate-all-around device comprising a source/drain contact passing through the isolation liner in order to provide the well-known advantage of providing electrical connections to the source/drain regions of a gate-all-around device so as to provide a path for electrons to flow into the source region and out of the drain region.
Regarding Claim 4, the combination of Bi, Yi and Cheng discloses all the limitations of claim 2.
Bi fails to disclose the gate-all-around device of claim 2, further comprising: a bottom insulating slab beneath the one or more nanosheet channel sections, wherein the bottom insulating slab separates the active gate structure from the substrate, and the bottom insulating slab is adjacent to at least a portion of the isolation liner.
However, Yi teaches a similar gate-all-around device further comprising:
a bottom insulating slab beneath the one or more nanosheet channel sections (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104 putting it beneath the nanosheet channel sections), wherein the bottom insulating slab separates the active gate structure from the substrate (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104, separating the active gate structure GE and GI, from the substrate 101), and the bottom insulating slab is adjacent to at least a portion of the isolation liner (upon modifying Bi with the bottom insulating slab of Yi, at least a portion of the isolation region of Bi would be adjacent, meaning next to or very near, the bottom insulating slab of Yi (see annotated Fig. 7 below)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the teachings of Bi and Cheng with Yi to disclose a semiconductor device which comprises a bottom insulation slab, to provide the further advantage of preventing leakage of current through a sub-region between adjacent transistors resulting in a more reliable gate-all-around transistor device (Yi, para [0037] and para [0069]).
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Regarding Claim 5, the combination of Bi, Yi and Cheng teach the gate-all-around device of claim 4, wherein the bottom insulating slab (Yi, 155B Fig. 7, para [0036] and para [0092] describes wherein the bottom insulating slab 155B may include the same insulating material as the internal spacers, which are comprised of at least one of SiN, SiCN, SiOCN, SiBCN, or SiBN) and the isolation liner are made of different electrically insulating dielectric materials (Bi, 320, Fig. 19, para [0103] describes wherein the isolation liner 320 may be comprised of a dielectric material such as SiO wherein a silicon oxide isolation liner is a different electrically insulating dielectric material than any of the silicon nitride bottom insulating slab materials of Yi).
Regarding Claim 6, the combination of Bi, Yi and Cheng teach the gate-all-around device of claim 5, wherein the source/drain imparts a compressive stress to the one or more nanosheet channel sections (Yi, para [0027] describes the source/drain region SD can be configured to provide compressive strain to the channel layers CH).
Regarding Claim 7, the combination of Bi, Yi and Cheng teach the gate-all-around device of claim 5, wherein the source/drain imparts a tensile stress to the one or more nanosheet channel sections (Yi, para [0027] describes the source/drain region SD can be configured to provide tensile strain to the channel layers CH).
Regarding Claim 22, the combination of Bi and Yi teaches the gate-all-around device of claim 21, further comprising:
an active gate structure on the one or more nanosheet channel sections (Bi, 330, 335 and 337, Fig. 19, para [0104] describes wherein an active gate structure can be formed on the nanosheet channel sections 137 and 177 including a gate dielectric 330, work function layer 335 and a conductive gate fill 337), wherein the active gate structure wraps around at least a portion of the one or more nanosheet channel sections (Bi, para [0109] describes wherein the active gate structure comprising the gate dielectric 330, work function layer 335 and conductive gate fill 337 can wrap around the nanosheet cannel sections 137 and 177).
Bi and Yi fail to teach a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain.
However, Cheng teaches a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain (134, Fig. 20, para [0106] describes forming source/drain contacts 134 that pass through a contact opening of the isolation layer 132).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bi and Yi with Cheng to further disclose a gate-all-around device comprising a source/drain contact passing through the isolation liner in order to provide the well-known advantage of providing electrical connections to the source/drain regions of a gate-all-around device so as to provide a path for electrons to flow into the source region and out of the drain region.
Regarding Claim 23, the combination of Bi, Yi and Cheng teach the gate-all-around device of claim 22, wherein the source/drain extends laterally over the STI regions (Yi, SD and 105, Fig. 3F, para [0026] describes source/drain regions SD that extend laterally over the STI regions 105 as shown in Fig. 3F).
Regarding Claim 24, the combination of Bi, Yi and Cheng discloses all the limitations of claim 22.
Bi fails to disclose the gate-all-around device of claim 22, further comprising: a bottom insulating slab beneath the one or more nanosheet channel sections, wherein the bottom insulating slab separates the active gate structure from the substrate, and the bottom insulating slab is adjacent to at least a portion of the isolation liner.
However, Yi teaches a similar gate-all-around device further comprising:
a bottom insulating slab beneath the one or more nanosheet channel sections (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104 putting it beneath the nanosheet channel sections), wherein the bottom insulating slab separates the active gate structure from the substrate (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104, separating the active gate structure GE and GI, from the substrate 101), and the bottom insulating slab is adjacent to at least a portion of the isolation liner (upon modifying Bi with the bottom insulating slab of Yi, at least a portion of the isolation region of Bi would be adjacent, meaning next to or very near, the bottom insulating slab of Yi (see annotated Fig. 7 below)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the teachings of Bi and Cheng with Yi to disclose a semiconductor device which comprises a bottom insulation slab, to provide the further advantage of preventing leakage of current through a sub-region between adjacent transistors resulting in a more reliable gate-all-around transistor device (Yi, para [0037] and para [0069]).
Regarding Claim 25, the combination of Bi, Yi and Cheng teach the gate-all-around device of claim 24, wherein the bottom insulating slab (Yi, 155B Fig. 7, para [0036] and para [0092] describes wherein the bottom insulating slab 155B may include the same insulating material as the internal spacers, which are comprised of at least one of SiN, SiCN, SiOCN, SiBCN, or SiBN) and the isolation liner are made of different electrically insulating dielectric materials (Bi, 320, Fig. 19, para [0103] describes wherein the isolation liner 320 may be comprised of a dielectric material such as SiO wherein a silicon oxide isolation liner is a different electrically insulating dielectric material than any of the silicon nitride bottom insulating slab materials of Yi).
Regarding Claim 26, the combination of Bi, Yi and Cheng teach the gate-all-around device of claim 25, wherein the source/drain imparts a compressive stress to the one or more nanosheet channel sections (Yi, para [0027] describes the source/drain region SD can be configured to provide compressive strain to the channel layers CH).
Regarding Claim 27, the combination of Bi, Yi and Cheng teach the gate-all-around device of claim 25, wherein the source/drain imparts a tensile stress to the one or more nanosheet channel sections (Yi, para [0027] describes the source/drain region SD can be configured to provide tensile strain to the channel layers CH).
Claims 29 is rejected under 35 U.S.C. 103 as being unpatentable over Pei-Hsun Wang et al. (US 2021/0167218 A1; hereinafter “Wang”) in further view of Kangguo Cheng et al. (US 2020/0295198 A1; hereinafter “Cheng”).
Regarding Claim 29, Wang teaches the gate-all-around device of claim 28, further comprising:
an active gate structure on the one or more nanosheet channel sections (276 and 274, Fig. 13A, para [0046] describes a gate electrode 276 and gate dielectric 274), wherein the active gate structure wraps around at least a portion of the one or more nanosheet channel sections (para [0046] describes gate dielectric layer 274 of the active gate structure wrapping channel layers 204A).
Wang fails to teach a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain.
However, Cheng teaches a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain (134, Fig. 20, para [0106] describes forming source/drain contacts 134 that pass through a contact opening of the isolation layer 132).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Wang and Cheng to further disclose a gate-all-around device comprising a source/drain contact passing through the isolation liner in order to provide the well-known advantage of providing electrical connections to the source/drain regions of a gate-all-around device so as to provide a path for electrons to flow into the source region and out of the drain region.
Claims 31-33 are rejected under 35 U.S.C. 103 as being unpatentable over Pei-Hsun Wang et al. (US 2021/0167218 A1; hereinafter “Wang”) in view of Kangguo Cheng et al. (US 2020/0295198 A1; hereinafter “Cheng”) and in further view of Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”).
Regarding Claim 31, the combination of Wang and Cheng discloses all the limitations of claim 29.
The combination of Wang and Cheng fails to disclose the gate-all-around device of claim 29, further comprising: a bottom insulating slab beneath the one or more nanosheet channel sections, wherein the bottom insulating slab separates the active gate structure from the substrate, and the bottom insulating slab is adjacent to at least a portion of the isolation liner.
However, Yi teaches a similar gate-all-around device as Wang and Cheng, further comprising:
a bottom insulating slab beneath the one or more nanosheet channel sections (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104 putting it beneath the nanosheet channel sections), wherein the bottom insulating slab separates the active gate structure from the substrate (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104, separating the active gate structure GE and GI, from the substrate 101), and the bottom insulating slab is adjacent to at least a portion of the isolation liner (upon modifying Wang with the bottom insulating slab of Yi, at least a portion of the isolation region of Wang would be adjacent, meaning next to or very near, the bottom insulating slab of Yi (see annotated Fig. 7 below)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the teachings of Wang and Cheng with Yi to disclose a semiconductor device which comprises a bottom insulation slab, to provide the further advantage of preventing leakage of current through a sub-region between adjacent transistors resulting in a more reliable gate-all-around transistor device (Yi, para [0037] and para [0069]).
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Regarding Claim 32, the combination of Wang and Cheng and Yi teach all the limitations of claim 31.
The combination of Wang, Cheng, and Yi fails to explicitly disclose wherein the bottom insulating slab and the isolation liner are made of different electrically insulating dielectric materials.
However, Wang teaches in para [0042] of the disclosure of their application wherein the isolation liner 242 may comprise low K dielectric material, silicon nitride, other dielectric material, or combinations thereof. Yi teaches in para [0036] and para [0092] of their disclosure, wherein the bottom insulating slab 155B may include the same insulating material as the internal spacers, which are comprised of at least one of SiN, SiCN, SiOCN, SiBCN, or SiBN.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different dielectric and insulating materials for the isolation liner 242 found in the disclosure of Wang, and the insulating slab 155B found in the disclosure of Yi, such as SiO for the isolation liner 242 and SiBCN for the insulating slab 155B to provide the advantage of better controlling leakage for each device component individually based on the composition of the electrically insulating dielectric materials (Wang, para [0042]).
Regarding Claim 33, the combination of Wang, Cheng and Yi teaches the limitations of claim 31, wherein the source/drain imparts a tensile stress to the one or more nanosheet channel sections (Yi, para [0027] describes the source/drain region SD can be configured to provide tensile strain to the channel layers CH).
Response to Arguments
Applicant’s arguments, see page 7, line 13-22, filed 4 May 2026, with respect to the rejection of claim 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of the prior art of record Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”). Yi teaches a similar gate-all-around device comprising shallow trench isolation (STI) regions in the substrate (105, Fig. 3F, para [0024] describes a device isolation layer 105 disposed on portions of a substrate 101), wherein the isolation liner covers the STI regions (105, Fig. 3F, para [0024] describes the shallow trench isolation regions 105 wherein upon combining the isolation liner 320 of Bi with the shallow trench isolation regions 105 of Yi, the isolation liner 320 of Bi can be seen covering surfaces of substrate 110 wherein the shallow trench isolation regions 105 of Yi would be disposed). Therefore, claim 1 now stands rejected under 35 U.S.C. 103 as being unpatentable over Zhenxing Bi et al. (2020/0119015 A1; hereinafter “Bi”) in view of Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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