DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 December 2025 has been entered.
Claim and Specification Status
The Examiner acknowledges the amendments to claim 1. The claim amendments and the Applicant’s accompanying comments have been addressed below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhenxing Bi et al. (2020/0119015 A1; hereinafter “Bi”).
Regarding Claim 1, Bi teaches a gate-all-around device, comprising
a source/drain (290, Fig. 19, para [0097] describes source/drain layers 290);
an isolation liner wrapped around the source/drain (320, Fig. 19, para [0103] describes an interlayer dielectric layer 320 which can be seen wrapping around source/drain region 290 in Fig. 19), where the isolation liner separates the source/drain from the substrate (110, Fig. 19, para [0035] describes a substrate 110 which can be seen separated from source/drain regions 290 by isolation liner 320 in gap region 293); and
one or more nanosheet channel sections electrically connected to the source/drain (137 and 177, Fig. 19, para [0094] describes semiconductor channel sheets 137 and 177 which can be seen electrically connected to source/drain regions 290);
wherein a surface of the isolation liner below the source/drain shares a vertical plane with the one or more nanosheet channel sections (VP, annotated Fig. 19 depicts wherein portions of the isolation liner ILB below the source/drain regions 290 share a vertical plane VP with nanosheet channel sections 137 and 177) and the isolation liner is disposed horizontally between more than one of the one or more nanosheet channel sections (ILB, annotated Fig. 19 depicts wherein portions of the isolation liner ILB are disposed horizontally between one or more adjacent nanosheet sections 137 and 177).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhenxing Bi et al. (2020/0119015 A1; hereinafter “Bi”) in view of Kangguo Cheng et al. (US 2020/0295198 A1; hereinafter “Cheng”).
Regarding Claim 2, Bi teaches the gate-all-around device of claim 1, further comprising an active gate structure on the one or more nanosheet channel sections (330, 335 and 337, Fig. 19, para [0104] describes wherein an active gate structure can be formed on the nanosheet channel sections 137 and 177 including a gate dielectric 330, work function layer 335 and a conductive gate fill 337), wherein the active gate structure wraps around at least a portion of the one or more nanosheet channel sections (para [0109] describes wherein the active gate structure comprising the gate dielectric 330, work function layer 335 and conductive gate fill 337 can wrap around the nanosheet cannel sections 137 and 177).
Bi fails to teach a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain.
However, Cheng teaches a source/drain contact that passes through the isolation liner and is in electrical contact with the source/drain (134, Fig. 20, para [0106] describes forming source/drain contacts 134 that pass through a contact opening of the isolation layer 132).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bi and Cheng to further disclose a gate-all-around device comprising a source/drain contact passing through the isolation liner in order to provide the well-known advantage of providing electrical connections to the source/drain regions of a gate-all-around device so as to provide a path for electrons to flow into the source region and out of the drain region.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhenxing Bi et al. (2020/0119015 A1; hereinafter “Bi”) in view of Kangguo Cheng et al. (US 2020/0295198 A1; hereinafter “Cheng”) and in further view of Jihye Yi et al. (US 2020/0373391 A1; hereinafter “Yi”).
Regarding Claim 4, the combination of Bi and Cheng discloses all the limitations of claim 2.
The combination of Bi and Cheng fails to disclose the gate-all-around device of claim 2, further comprising a bottom insulating slab beneath the one or more nanosheet channel sections, wherein the bottom insulating slab separates the active gate structure from the substrate, and the bottom insulating slab is adjacent to at least a portion of the isolation liner.
However, Yi teaches a similar gate-all-around device as Bi and Cheng, further comprising a bottom insulating slab beneath the one or more nanosheet channel sections (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104 putting it beneath the nanosheet channel sections), wherein the bottom insulating slab separates the active gate structure from the substrate (155B, Fig. 7, para [0037] describes an isolation film between a lowermost channel layer and the active region 104, separating the active gate structure GE and GI, from the substrate 101), and the bottom insulating slab is adjacent to at least a portion of the isolation liner (upon modifying Bi with the bottom insulating slab of Yi, at least a portion of the isolation region of Bi would be adjacent, meaning next to or very near, the bottom insulating slab of Yi (see annotated Fig. 7 below)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the teachings of Bi and Cheng with Yi to disclose a semiconductor device which comprises a bottom insulation slab, to provide the further advantage of preventing leakage of current through a sub-region between adjacent transistors resulting in a more reliable gate-all-around transistor device (Yi, para [0037] and para [0069]).
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Regarding Claim 5, the combination of Bi, Cheng and Yi teach the limitations of claim 4, wherein the bottom insulating slab (Yi, 155B Fig. 7, para [0036] and para [0092] describes wherein the bottom insulating slab 155B may include the same insulating material as the internal spacers, which are comprised of at least one of SiN, SiCN, SiOCN, SiBCN, or SiBN) and the isolation liner are made of different electrically insulating dielectric materials (Bi, 320, Fig. 19, para [0103] describes wherein the isolation liner 320 may be comprised of a dielectric material such as SiO wherein a silicon oxide isolation liner is a different electrically insulating dielectric material than any of the silicon nitride bottom insulating slab materials of Yi).
Regarding Claim 6, the combination of Bi, Cheng and Yi teach the limitations of claim 5, wherein the source/drain imparts a compressive stress to the one or more nanosheet channel sections (Yi, para [0027] describes the source/drain region SD can be configured to provide compressive strain to the channel layers CH).
Regarding Claim 7, the combination of Bi, Cheng and Yi teach the limitations of claim 5, wherein the source/drain imparts a tensile stress to the one or more nanosheet channel sections (Yi, para [0027] describes the source/drain region SD can be configured to provide tensile strain to the channel layers CH).
Response to Arguments
Applicant’s arguments with respect to claims 1-2 and 4-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898