DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response
See the new rejections below.
Claim Interpretation
Various claims now recite the term “defined by”. It is not clear how this is supposed to be different from “including”; does it mean that other elements are not permitted? Or that these are the only essential elements? Or does it mean basically the same thing as “including”? The examiner will interpret “defined by” to mean “must include” until this is clarified.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Xie, US 2019/0214482 A1, in view of US 2022/0223706 A1.
Claim 1: Xie discloses
a nano-channel (108) on a substrate, which has a first height, a first width (W1, e.g. 15 nm, [0056]), and a first length;
a plurality of vertical nanosheets (142) on opposite sides of the nano-channel, each of the plurality of vertical nanosheets being perpendicular to a major plane of the substrate, wherein an entirety of the nano-channel is laterally between the plurality of vertical nanosheets (FIG. 22), wherein each of the plurality of vertical nanosheets has a second height (T1, 30 nm, [0060]), a second width, and a second length, wherein that the second height of each of the plurality of vertical nanosheets is greater than the first width of the nano-channel, the nano-channel and the vertical nanosheets defining a transistor channel for the field effect device ([0045]);
a gate dielectric layer ([0079]) wrapped around at least a portion of each of the nano-channels and each of the plurality of vertical nanosheets;
and a conductive gate fill (210, [0179], FIG. 22) on the gate dielectric layer,
wherein the transistor channel is parallel to the major plane of the substrate. As seen in FIG. 21, the current of the channel between the source and drain 190, and thus the channel is horizontal.
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Note that Xie discloses at [0079] that the gate structure 210 surrounds the nano-channel 108 and the vertical nanosheets 142 includes a gate dielectric. Xie does not illustrate the gate dielectric, but those in the art would have recognized that the gate dielectric would surround the nano-channel and the vertical nanosheets because the gate surrounds them. The examiner takes official notice that a field effect transistor in which the channel directly contacts the gate electrode does not function as a field effect transistor.
Claim 1 recites “a vertical stack of nano-channels” rather than a single nanochannel. Xie discloses a gate all around (GAA) device, which in order to reduce short channel effects ([0004]), increases the contact area of the gate with the channel so that the channel can be shortened. See Yang, FIG. 18, which discloses a stack of nano-channels, with or without a vertical portion, as a GAA transistor. The total surface area of the channel contacting the gate (and thus protection against the short channel effect) is increased by having more horizontal nano-channels. It would have been obvious to have had multiple nano-channels in Xie in order to further reduce the short channel effect and allow for higher transistor density.
Xie discloses the claimed difference in height and width; additionally, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV).
Claim 2: Xie discloses a first source/drain and a second source/drain (190) on opposite sides of a gate structure including the conductive gate fill (FIG. 21), wherein the first source/drain and the second source/drain are connected to the transistor channel defined by the nano-channels and the plurality of vertical nanosheets ([0089]).
Claim 3: Xie discloses forming CFETs, in which one of the transistors is a PFET and has p type doping in the source and drain regions [0072].
Claim 4: the substrate, the nano-channels, and the plurality of vertical nanosheets are silicon ([0048], [0085]).
Claim 8: Xie discloses a gate all around (GAA) device with a single nanochannel 108, which in order to reduce short channel effects ([0004]), increases the contact area of the gate with the channel so that the channel can be shortened. See Yang, FIG. 18, which discloses a stack of nano-channels, with or without a vertical portion, as a GAA transistor. The total surface area of the channel contacting the gate (and thus protection against the short channel effect) is increased. It would have been obvious to have had multiple nano-channels in Xie in order to further reduce the short channel effect and allow for higher transistor density.
With this modification in view of Yang, Xie discloses a CFET ([0106])
a first stack of first nano-channels (108, bottom side, FIGS. 23-28) on a substrate, wherein each of the first nano-channels has a first height, a first width (W1, e.g. 15 nm, [0056]), and a first length;
a plurality of first vertical nanosheets (142, bottom side) on opposite sides of the first stack of first nano-channels, each of the plurality of first vertical nanosheets being perpendicular to a major plane of the substrate, wherein an entirety of the first stack of first nano-channels is laterally between the plurality of first vertical nanosheets (FIG. 28), wherein each of the plurality of first vertical nanosheets has a second height (T1, 30 nm, [0060]), a second width, and a second length, wherein the second height of each of the plurality of first vertical nanosheets is greater than the first width of each of the first nano-channels, the first nano-channels and the plurality of first vertical nanosheets defining a first transistor channel for a first field effect device ([0045]);
a first gate dielectric layer ([0079]) wrapped around at least a portion of each of the first nano-channels and each of the plurality of first vertical nanosheets;
a first conductive gate fill (210, [0179], FIG. 28) on the first gate dielectric layer;
a second stack of second nano-channels (108, top side) on the substrate, wherein each of the second nano-channels has a third height, a third width (W1, e.g. 40 nm, [0056]), and a third length;
a plurality of second vertical nanosheets (142, top side) on opposite sides of the second stack of second nano-channels, each of the plurality of second vertical nanosheets being perpendicular to the major plane of the substrate, wherein an entirety of the second stack of second nano-channels is laterally between the plurality of second vertical nanosheets (FIG. 28), wherein each of the plurality of second vertical nanosheets has a fourth height (T1, 30 nm, [0060]), a fourth width, and a fourth length, wherein the third width of each of the second nano-channels is greater than the fourth height of each of the plurality of second vertical nanosheets, the second nano-channels and the plurality of second vertical nanosheets defining a second transistor channel for a second field effect device;
a second gate dielectric layer ([0079]) wrapped around at least a portion of each of the second nano-channels and each of the plurality of second vertical nanosheets;
and a second conductive gate fill (210, [0179], FIG. 28) on the second gate dielectric layer.
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Note that Xie discloses at [0079] that the gate structure 210 surrounds the nano-channel 108 and the vertical nanosheets 142 includes a gate dielectric. Xie does not illustrate the gate dielectric, but those in the art would have recognized that the gate dielectric would surround the nano-channel and the vertical nanosheets because the gate surrounds them. The examiner takes official notice that a field effect transistor in which the channel directly contacts the gate electrode does not function as a field effect transistor.
It would have been within ordinary skill in the art to optimize the properties of each of the P and N sides of the CFET, given the extensive explanation of Ye of the properties of different configurations with e.g. different relative dimensions.
Xie discloses the claimed difference in height and width; additionally, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV). Yang shows that it was well-known in the art to CFETs side by side, in addition to the top-bottom configuration of Xie. It would have been within ordinary skill in the art to optimize the properties of each of the P and N sides of the CFET, given the extensive explanation of Ye of the properties of different configurations with e.g. different relative dimensions.
Claim 9: Xie discloses a first source/drain and a second source/drain (190 around the bottom transistor, [0103]) on opposite sides of a first gate structure including the first conductive gate fill (FIG. 16), wherein the first source/drain and the second source/drain are connected to the first transistor channel defined by the first nano-channels and the plurality of first vertical nanosheets ([0069]), and a third source/drain and a fourth source/drain (190 around the top transistor, [0103]) on opposite sides of a second gate structure including the second conductive gate fill, the third source/drain and the fourth source/drain are connected to the second transistor channel defined by the second nano-channels and the plurality of second vertical nanosheets ([0069]).
Claim 10: the first source/drain and the second source/drain are doped with a p-type dopant, and wherein the first field effect device is a p-type field effect transistor device ([0112]).
Claims 5, 6, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Yang and Cheng, US 2018/0040716. Claim 7 is are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Yang and Cheng, and Ye, US 2022/0310787 A1. Xie does not disclose what the crystal planes of the device. However, the claimed crystal planes were known in the art. See Cheng, [0074], which discloses that "the surface of the wafer can have a {001} crystal plane. The vertical fin sidewalls may be either {110} or {100} crystal planes". It would have been obvious to have the substrate with a {001} crystal plane as known in the art. It would have been obvious to have used a vertical nanosheet including a {110} crystal plane as a known crystal orientation for a vertical channel structure.
Claim 6: Ye discloses a fill layer (104) beneath at least a portion of the vertical nanosheets.
Claim 7: Xie does not disclose a plurality of inner spacers between the nano-channels. Ye discloses inner spacers (320, [0068], FIG. 17C) between the nano-channels. It would have been obvious to have applied these to Xie to maintain appropriate spacing between the nano-channels ([0069]).
Claim 12: the third source/drain and the fourth source/drain are doped with an n-type dopant, and wherein the second field effect device is an n-type field effect transistor device (Xie [0112]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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