DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amended claim 8 overcomes the previous objection.
See the new art rejections of the amended claims below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a) as being anticipated by Ye, US 2022/0310787 A1.
Claim 1: Ye discloses
a vertical stack of nano-channels (204) on a substrate (200), wherein each of the nano-channels has a first height, a first width, and a first length;
vertical nanosheets (205) perpendicular to a major plane of the substrate on opposite sides of the vertical stack of nano-channels, wherein each of the vertical nanosheets has a second height, a second width, and a second length, wherein the second height of the vertical nanosheets (HIB = 2nm, FIG. 6C) is greater than the first width of the nano-channels (WNS = 1nm), the nano-channels and the vertical nanosheets forming a transistor channel for the field effect device ([0025]);
a gate dielectric layer (212) wrapped around at least a portion of each of the nano-channels and the vertical nanosheets; and
a conductive gate fill (216) on the gate dielectric layer,
wherein the transistor channel is parallel to the major plane of the substrate (FIG. 2).
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Claim 2: Ye discloses a source/drain (208) on each of opposite sides of a gate structure formed with the conductive gate fill, the source/drains being connected to the transistor channel including the nano-channels and the vertical nanosheets (FIG. 2, [0028]-[0029]).
Claim 3: the source/drains are doped with a p-type dopant to form a p-type field effect transistor device ([0026]). Ye discloses this as a general property, which could be implemented with any of the embodiments.
Claim 4: the substrate, the nano-channels and the vertical nanosheets are silicon (Si) ([0049]-[0050]). Ye discloses that “the first and second semiconductor layers are made of different materials selected from the group consisting of Si, Ge, SiGe, GeSn, Si/SiGe/Ge/GeSn, SiGeSn, and combinations thereof.” The examiner interprets the recitation that “the vertical nanosheets are silicon” mean that they contain silicon; four of the six materials contain silicon, and thus any combination of those materials would read on claim 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over
Ye in evidence of Yang, US 2022/0223706 A1.
Claim 8: Ye discloses
a first stack of first nano-channels (204) on a substrate, wherein each of the first nano-channels has a first height, a first width, and a first length;
first vertical nanosheets (205) perpendicular to a major plane of the substrate on opposite sides of the first stack of first nano-channels, wherein each of the first vertical nanosheets has a second height, a second width, and a second length, wherein the second height of the first vertical
nanosheets (HIB = 2nm, FIG. 6C) is greater than the first width of the first nano-channels (WNS = 1nm), the first nano-channels and the first vertical nanosheets forming a first transistor channel for a first field effect device ([0025]);
a first gate dielectric layer (212) wrapped around at least a portion of each of the first nano-channels and the first vertical nanosheets (FIG. 2);
a first conductive gate fill (216) on the first gate dielectric layer:
a second slack of second nano-channels (204) on the substrate, wherein each of the second nano channels has a third height, a third width, and a third length,
second vertical nanosheets (205) perpendicular to a major plane of the substrate on opposite sides of the second stack of nano-channels, wherein each of the second vertical nanosheets has a fourth height, a fourth width, and a fourth length, wherein the third width of the second nano-channels (HIB = 1nm, FIG. 6B) is greater than the fourth height of the second vertical nanosheets (WNS = 2nm), the second nano-channels and the second vertical nanosheets forming a second transistor channel for a second field effect device ([0025]);
a second gate dielectric layer (212) wrapped around at least a portion of each of the second nano-channels and the second vertical nanosheets; and
a second conductive gate fill (216) on the second gate dielectric layer.
The preamble of claim 8 recites a “complementary field effect device”. Ye recites field effect devices ([0025]). Ye recites that “[t]he nanostructure 104 may include p-type nanostructures, n-type nanostructures, or a combination thereof.” Those in the art would recognize that a common kind of combination of p-type and n-type structures would be a complementary FET, as these were common in the art. As an example, see e.g. Yang, complementary FETS, [0030], FIG. 20.
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It would have been within ordinary skill in the art to optimize the properties of each of the P and N sides of the CFET, given the extensive explanation of Ye of the properties of different configurations with e.g. different relative dimensions.
Claim 9: Ye discloses first source/drains (208) on each of opposite sides of a first gate structure formed with the frat conductive gate fill, the first source/drains being connected to the first transistor channel including the first nano-channels and the first vertical nanosheets, and second source/drain (208) on each of opposite sides of a second gate structure formed with the second conductive gate fill, the second source/drains being connected to the second transistor channel including the second nano-channels and the second vertical nanosheets (FIG. 2).
Claim 10: the first source/drains are doped with a p-type dopant to form a p-type field effect transistor device. “The nanostructure 104 may include p-type nanostructures, n-type nanostructures, or a combination thereof.”
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ye in view of Luo and Cheng, US 2018/0040716. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ye in view of Luo and Cheng and in evidence of Yang. Ye does not disclose what the crystal planes of the device. However, the claimed crystal planes were known in the art. See Cheng, [0074], which discloses that "the surface of the wafer can have a {001} crystal plane. The vertical fin sidewalls may be either {110} or {100} crystal planes". It would have been obvious to have the substrate with a {001} crystal plane as known in the art. It would have been obvious to have used a vertical nanosheet including a {110} crystal plane as a known crystal orientation for a vertical channel structure.
Claim 6: Ye discloses a fill layer (214) beneath at least a portion of the vertical nanosheets.
Claim 7: Ye discloses inner spacers (320, [0068], FIG. 17C) between the nano-channels. Although this is a different embodiment, it would have been obvious to have applied this to the other embodiments “to separate the epitaxial source/drain structures 322 from portions of the interbridge layers 302B and 302C by an appropriate lateral distance” [0069].
Claim 12: the second source/drain are doped with an n-type dopant to form an n-type field effect transistor device. “The nanostructure 104 may include p-type nanostructures, n-type nanostructures, or a combination thereof.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited. See Doyle, US 2007/0231997 A1, FIG. 3, which illustrates a structure similar to Ye.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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