Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5-8, 14 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheah et al. (US 2021/0193616 A1).
Regarding independent claim 1: Cheah teaches (e.g., Fig. 1A) a chip for multi-die communications couplings using a single bridge die, comprising:
a plurality of dies ([0016] and [0020]-[0021]: 120 and 130) each comprising one or more functional circuit blocks ([0016] and [0020]-[0021]: 120 and 130 comprise one or more functional circuit blocks, such as memory die or field programmable gate array) and a first side (bottom side) mounted to back-end-of-line (BEOL) structures ([0018]-[0019]: upper surface conductive structure 117/118/125 and pads) and configured to be coupled to a substrate ([0016]-[0020]: 110);
a first bridge die ([0016]-[0017] and [0020]: 150) coupling two or more pairs of dies of the plurality of dies (120 and 130),
wherein the first bridge die (150) is mounted on a second opposite side (upper side) of the plurality of dies (120 and 130), opposite from the BEOL structures (117/118/125 and pads),
Regarding claim 3: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends, further comprising
a first stacked die ([0016]-[0020]: 140) positioned entirely on one die of the two or more pairs of dies (Fig. 1A; [0016]-[0020]) and next to the first bridge die (Fig. 1A; first bridge die 150).
Regarding claim 5: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends,
wherein a plurality of communication paths ([0016] and [0028]-[0030]: communication paths 152) in the first bridge die (150) are non-overlapping ([0016] and [0028]-[0030]: communication paths 152 in the region of device 160 is non-overlapping).
Regarding claim 6: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends,
wherein a plurality of communication paths ([0016] and [0028]-[0030]: communication paths 152) in the first bridge die (150) are overlapping ([0016] and [0028]-[0030]: communication paths 152 in the region above the devices 120 and 130 are overlapping).
Regarding claim 7: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends,
further comprising one or more other dies ([0016]-[0020]: 140) each bonded to a respective die (120) of the plurality of dies.
Regarding claim 8: Cheah teaches the claim limitation of the chip of claim 7, on which this claim depends,
wherein the plurality of dies comprises one or more through-silicon vias (TSVs) ([0016] and [0021]: 122) to the one or more other dies.
Regarding independent claim 14: Cheah teaches (e.g., Fig. 1A and Fig. 6) an apparatus for multi-die communications couplings using a single bridge die comprising:
computer memory ([0020] and [0061]-[0063]: 630); and
a system-on-chip ([0059]-[0060]: 610) operatively coupled to the computer memory (630), wherein the system-on-chip comprises:
a plurality of dies ([0016] and [0020]-[0021]: 120 and 130) each comprising one or more functional circuit blocks ([0016] and [0020]-[0021]: 120 and 130 comprise one or more functional circuit blocks, such as memory die or field programmable gate array) and a first side (bottom side) mounted to back-end-of-line (BEOL) structures ([0018]-[0019]: upper surface conductive structure 117/118/125 and pads) and configured to be coupled to a substrate ([0016]-[0020]: 110);
a first bridge die ([0016]-[0017] and [0020]: 150) coupling two or more pairs of dies of the plurality of dies (120 and 130),
wherein the first bridge die (150) is mounted on a second opposite side (upper side) of the plurality of dies (120 and 130), opposite from the BEOL structures (117/118/125 and pads).
Regarding claim 17: Cheah teaches the claim limitation of the apparatus of claim 14, on which this claim depends;
wherein a plurality of communication paths ([0016] and [0028]-[0030]: communication paths 152) in the first bridge die (150) are non-overlapping ([0016] and [0028]-[0030]: communication paths 152 in the region of device 160 is non-overlapping).
Regarding claim 18: Cheah teaches the claim limitation of the apparatus of claim 14, on which this claim depends;
wherein a plurality of communication paths ([0016] and [0028]-[0030]: communication paths 152) in the first bridge die (150) are overlapping ([0016] and [0028]-[0030]: communication paths 152 in the region above the devices 120 and 130 are overlapping).
Regarding claim 19: Cheah teaches the claim limitation of the apparatus of claim 14, on which this claim depends;
wherein the system-on-chip further comprises one or more other dies ([0016]-[0020]: 140) each bonded to a respective die of the plurality of dies.
Regarding claim 20: Cheah teaches the claim limitation of the apparatus of claim 19, on which this claim depends;
wherein the plurality of dies comprises one or more through-silicon vias (TSVs) ([0016] and [0021]: 122) to the one or more other dies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2021/0193616 A1) in view of Wang et al. (US 2018/0366436 A1).
Regarding claim 2: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends.
Cheah does not expressly teach that the chip further comprises
one or more redistribution layers (RDLs) positioned between the first bridge die and the two or more pairs of dies,
wherein the RDLs contact the second opposite side of the plurality of dies opposite from the BEOL structures.
Wang teaches (e.g., Figs. 11 through Figs. 1-14 and Fig 6, "[0009] FIG. 6 is a block diagram of a top-down view depicting an exemplary MCM of FIG. 1 or FIG. 4 having four integrated circuit dies bridged by a same bridge die") a chip for multi-die communications couplings using a single bridge die, comprising a plurality of dies ([0034] and [0036]; Fig. 6; [0079]: 126;127;226;227); a first bridge die ([0046]: 103) coupling two or more pairs of dies of the plurality of dies (Fig. 6; [0079]: 126;127; 226;227);
Wang further teaches that the device comprises one or more redistribution layers (RDLs) ([0061]: 201) positioned between the first bridge die ([0046]: 103) and the two or more pairs of dies ([0034] and [0036]; Fig. 6; [0079]: 126;127; 226;227).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the one or more redistribution layers (RDLs) positioned between the first bridge die and the two or more pairs of dies, wherein the RDLs contact the second opposite side of the plurality of dies opposite from the BEOL structures, as taught by Wang for the benefits of increasing the choices of input/output points, and thus, reducing the device interconnection constraints.
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2021/0193616 A1) in view of McHerron et al. (US 2021/0020529 A1).
Alternatively, if the communication path is meant for the whole interconnect, then this limitation is taught as shown below:
Regarding claim 5: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends,
wherein a plurality of communication paths ([0016] and [0028]-[0030]: communication paths 152) in the first bridge die (150) are overlapping ([0016] and [0028]-[0030]: communication paths 152 in the region of device 160 is non-overlapping).
Cheah does not expressly teach communication paths are non-overlapping
McHerron teaches (e.g., Fig. 1) a method comprising coupling a first pair of dies ([0033]: 110A and 110C) using a first bridge die ([0033]: 140AC);
McHerron further teaches that the plurality of communication paths ([0036] and [0038]: 120X) in the first bridge die (140AC) are non-overlapping (Fig. 1; [0044] communication paths in region 175 are non-overlapping).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the device wherein the plurality of communication paths are non-overlapping, as taught by McHerron, for the benefits of selectively interconnecting integrated circuits based on defined functions and tandem functions with direct interconnections, and thus, reducing the signal speed due to shorter wring length and at the same time isolating adjacent devices not required in the function.
Alternatively, if the communication path is meant for the whole interconnect, then this limitation is taught as shown below:
Regarding claim 17: Cheah teaches the claim limitation of the apparatus of claim 14, on which this claim depends;
wherein a plurality of communication paths ([0016] and [0028]-[0030]: communication paths 152) in the first bridge die (150) are overlapping ([0016] and [0028]-[0030]: communication paths 152 in the region of device 160 is non-overlapping).
Cheah does not expressly teach communication paths are non-overlapping
McHerron teaches (e.g., Fig. 1) a method comprising coupling a first pair of dies ([0033]: 110A and 110C) using a first bridge die ([0033]: 140AC);
McHerron further teaches that the plurality of communication paths ([0036] and [0038]: 120X) in the first bridge die (140AC) are non-overlapping (Fig. 1; [0044] communication paths in region 175 are non-overlapping).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the device wherein the plurality of communication paths are non-overlapping, as taught by McHerron, for the benefits of selectively interconnecting integrated circuits based on defined functions and tandem functions with direct interconnections, and thus, reducing the signal speed due to shorter wring length and at the same time isolating adjacent devices not required in the function.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2021/0193616 A1) in view of Wu et al. (US 2020/0176384 A1).
Regarding claim 9: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends,
Cheah does not teach that the plurality of dies comprises a plurality of system-on-chip dies.
Wu teaches (e.g., Fig. 1A-1J) a chip for multi-die communications couplings using a single bridge die, comprising a plurality of dies ([0046]: 110; 120);
Wu further teaches that the plurality of dies comprises a plurality of system-on-chip dies ([0014], [0017]: plurality of dies comprises a plurality of system-on-chip dies; see [0061]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the plurality of dies comprising a plurality of system-on-chip dies, as taught by Wu, for the benefits of increasing the device density and the integrated circuit functionalities by integrating a variety of chips with different functions.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2021/0193616 A1) in view of Chen et al. (US 2020/0006251 A1).
Regarding independent claim 10: Cheah teaches (e.g., Fig. 1A and Fig. 5) a method for multi-die communications couplings using a single bridge die, the method comprising:
coupling, via a first bridge die ([0016]-[0017] and [0020]: 150), two or more pairs of dies in a plurality of dies ([0016] and [0020]-[0021]: 120 and 130),
wherein each of the plurality of dies comprises one or more functional circuit blocks ([0016] and [0020]-[0021]: 120 and 130 comprise one or more functional circuit blocks, such as memory die or field programmable gate array) and a first side mounted to back-end-of-line (BEOL) structures ([0018]-[0019]: upper surface conductive structure 117/118/125 and pads) and configured to be coupled to a substrate ([0016]-[0020]: 110), and
wherein the first bridge die is mounted on a second opposite side (upper side) of the plurality of dies (120 and 130), opposite from the BEOL structures;
Cheah does not expressly teach that at least partially encapsulating the plurality of dies and the first bridge die to create an encapsulated component group; and
bonding the encapsulated component group to a carrier wafer.
Chen teaches (e.g., Figs. 1-7B) a method for multi-die communications couplings using a single bridge die, the method comprising a plurality of dies ([0019]-[0021]: 24A and 24B) and a first bridge die ([0030]-[0032]: 66);
Chen further teaches that at least partially encapsulating ([0021]: 40) the plurality of dies ([0019]-[0021]: 24A and 24B) and the first bridge die ([0030]-[0034]: 66) to create an encapsulated component group ([0030]-[0034]: 66); and
bonding the encapsulated component group to a carrier wafer ([0038]-[0039]: 80).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, method wherein at least partially encapsulating the plurality of dies and the first bridge die to create an encapsulated component group; and bonding the encapsulated component group to a carrier wafer, as taught by Chen, for the benefits of protecting the devices from external particles and humidity and strengthening the device structure, thereby increasing device reliability.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2021/0193616 A1) in view of Chen et al. (US 2020/0006251 A1) as applied above and further in view of Pietambaram et al. (US 2020/0258847 A1).
Regarding claim 4: Cheah teaches the claim limitation of the chip of claim 1, on which this claim depends:
Cheah does not expressly teach that a first pair of dies coupled by the first bridge die comprises a first die and a second die and
a second pair of dies coupled by the first bridge die comprises the first die and a third die.
Pietambaram teaches (e.g., Figs. 1A-1B) a device comprising
a first pair of dies ([0048]: 110A and 110B) coupled by a first bridge die ([0049]: 130) comprises a first die ([0048]: 110A comprises a first die) and a second die ([0048]: 110B comprises a second die) and
a second pair of dies ([0044]-[0046]: 107 on the side of 110A and 107 on the side of 110B) coupled by the first bridge die (130) comprises the first die (110A) and a third die ([0042] and [0046]: 112 on 110B side).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the first pair of dies coupled by the first bridge die comprises a first die and a second die and a second pair of dies coupled by the first bridge die comprises the first die and a third die, as taught by Pietambaram, for the benefits of increasing the device density, and thus increasing the integrated circuit functionalities.
Regarding claim 11: Cheah and Chen teach the claim limitation of the method of claim 10, on which this claim depends,
Cheah as modified by Chen does not expressly teach that the method further comprises bonding one or more other dies to a respective die of the plurality of dies, wherein the one or more other dies are included in the encapsulated component group.
Pietambaram teaches (Figs. 1A-4E) a method comprising
bonding one or more other dies ([0068] and [0079]-[0081]: 407 and 412) to a respective die of a plurality of dies ([0081]: 410A and 410B),
wherein the one or more other dies are included in an encapsulated component group ([0083], [0086] and [0088]: encapsulation layer 420 is used for forming the encapsulated component group).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the method further comprising bonding one or more other dies to a respective die of the plurality of dies, wherein the one or more other dies are included in the encapsulated component group, as taught by Pietambaram, for the benefits of protecting the devices from external particles and humidity and strengthening the device structure, thereby increasing device reliability.
Claims 12-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2021/0193616 A1) in view of Chen et al. (US 2020/0006251 A1) as applied above and further in view of McHerron et al. (US 2021/0020529 A1).
Regarding claim 12: Cheah and Chen teach the claim limitation of the method of claim 10, on which this claim depends,
Cheah as modified by Chen does not expressly teach that the method further comprises coupling a pair of dies using a second bridge die.
McHerron teaches (e.g., Fig. 1) a method comprising coupling a first pair of dies ([0033]: 110A and 110C) using a first bridge die ([0033]: 140AC);
McHerron further teaches coupling a pair of dies ([0033]: 110B and 110D) using a second bridge die ([0033]: 140BC).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the method further comprising coupling a pair of dies using a second bridge die, as taught by McHerron, for the benefits of selectively interconnecting integrated circuits based on defined functions and tandem functions with direct interconnections, and thus, reducing the signal speed due to shorter wring length.
Regarding claim 13: Cheah and Chen teach the claim limitation of the method of claim 10, on which this claim depends,
Cheah as modified by Chen does not expressly teach that the method further comprises that the first bridge die couples each die of the plurality of dies to each other die.
McHerron teaches (e.g., Fig. 2) a method comprising coupling a first pair of dies ([0038]: 110A and 110C) and a second pair of dies ([0038]: 110B and 110D) and a first bridge ([0038]: 250);
McHerron further teaches that the first bridge die ([0038]: 250) couples each die of the plurality of dies to each other die ([0038]: 110A, 110B, 110C and 110D are coupled to each other).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the method further comprising coupling a pair of dies using a second bridge die, as taught by McHerron, for the benefits of selectively interconnecting integrated circuit based on defined functions and tandem functions with direct interconnections, and thus, reducing the signal speed due to shorter wring length.
Regarding claim 15: Cheah teaches the claim limitation of the apparatus of claim 14, on which this claim depends;
Cheah as modified by Chen does not expressly teach that the system-on-chip further comprises
one or more second bridge dies each coupling one or more other pairs of dies.
McHerron teaches (e.g., Fig. 1) a method comprising coupling a first pair of dies ([0033]: 110A and 110C) using a first bridge die ([0033]: 140AC);
McHerron further teaches one or more second bridge dies ([0033]: 140BC) each coupling one or more other pairs of dies ([0033]: 110A, 110B, 110C and 110D)
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the system-on-chip of Cheah, the apparatus further comprising one or more second bridge dies each coupling one or more other pairs of dies, as taught by McHerron, for the benefits of selectively interconnecting integrated circuit based on defined functions and tandem functions with direct interconnections and thus reducing the signal speed due to shorter wring length.
Regarding claim 16: Cheah teaches the claim limitation of the apparatus of claim 14, on which this claim depends;
Cheah does not expressly teach that the system-on-chip further comprises that the first bridge die couples each die of the plurality of dies to each other die.
McHerron teaches (e.g., Fig. 2) a method comprising coupling a first pair of dies ([0038]: 110A and 110C) and a second pair of dies ([0038]: 110B and 110D) and a first bridge ([0038]: 250);
McHerron further teaches that the first bridge die ([0038]: 250) couples each die of the plurality of dies to each other die ([0038]: 110A, 110B, 110C and 110D are coupled to each other).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Cheah, the method further comprising coupling a pair of dies using a second bridge die, as taught by McHerron, for the benefits of selectively integrating the integrated circuit based on defined functions and tandem functions with direct interconnections, and thus, reducing the signal speed due to shorter wring length.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference or combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or for newly added limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812