DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 20 February 2026 has been entered.
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 16 April 2025.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., an abstract idea) without significantly more.
Regarding claim 1, under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: a method.
Under the Alice Framework Step 2A Prong 1 analysis, claim 1 recites Mental Processes and/or Mathematical Concepts. The claim recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas, and/or Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“providing an intermediate sum of the carry value and the sum value, wherein providing the intermediate sum generates a carry out bit;
incrementing the second value to create an incremented result, wherein the received second value is a non-incremented result;
determining a sign of the incremented result and a sign of the non-incremented result;
determining, whether to complement or pass through, responsive to the sign of the incremented result, the incremented result to provide a first output;
determining, whether to complement or pass through, responsive to the sign of the non-incremented result, the non-incremented result to provide a second output;
determining, whether to complement or pass through, responsive to the carry out bit, the sign of the incremented result, and the sign of the non-incremented result, the intermediate sum to provide a third output;
selecting one of the first and second outputs responsive to the carry out bit; and
providing a final sum comprising the third output and the selected one of the first and second outputs.”
See specification ([0087]) describing providing an intermediate sum. See specification ([0088]) describing incrementing the second value. See specification ([0089]) describing determining a sign. See specification ([0090], [0091], [0092]) describing complementing or passing through to provide a first output, a second output, a third output, respectively. See specification ([0093]) describing selecting one of the first and second outputs. See specification ([0094]) describing providing a final sum. For these reasons, the claim recites Mental Processes and/or Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: an adder, the adder configured to receive a carry-sum formatted value corresponding to a first portion of input bits to the adder, the carry-sum formatted value including a carry value and a sum value, the adder configured to receive a second value corresponding to a second portion of input bits to the adder that do not overlap the first portion of input bits, a first pre-compute circuit, a second pre-compute circuit, a third pre-compute circuit, and multiplexing circuitry. An adder, a first pre-compute circuit, a second pre-compute circuit, a third pre-compute circuit, and multiplexing circuitry are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The receive limitations are examples of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). The claim recites limitations which are examples of generic computing elements that result in “apply it” on a computer. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites an adder, a first pre-compute circuit, a second pre-compute circuit, a third pre-compute circuit, and multiplexing circuitry at a high level of generality, which merely result in “apply it” on a computer. The receive limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II)(i): Receiving or transmitting data over a network; MPEP 2106.05(d)(II)(iv): Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 1 is ineligible.
Claims 2-7 merely further limit the Mental Processes and/or Mathematical Concepts. Claims 2-7 do not recite any new additional elements.
Regarding claim 8, under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: a method.
Under the Alice Framework Step 2A Prong 1 analysis, claim 8 recites Mental Processes and/or Mathematical Concepts. The claim recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas, and/or Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“providing a first intermediate sum of a more-significant portion of the carry value and the sum value, wherein providing the first intermediate sum generates an upper carry out bit;
providing a second intermediate sum of a less-significant portion of the carry value and the sum value, wherein providing the second intermediate sum generates a lower carry out bit;
incrementing a more-significant portion of the second value to create a first incremented result, wherein the more-significant portion of the received second value is a first non-incremented result;
incrementing a less-significant portion of the second value to create a second incremented result, wherein the less-significant portion of the received second value is a second non-incremented result;
determining a sign of the first incremented result, a sign of the first non-incremented result, a sign of the second incremented result, and a sign of the second non-incremented result;
determining, whether to complement or pass through each of:
the first incremented result, responsive to the sign of the first incremented result, to provide a first output;
the first non-incremented result, responsive to the sign of the first non-incremented result, to provide a second output;
the second incremented result, responsive to the sign of the second incremented result, to provide a third output; and
the second non-incremented result, responsive to the sign of the second non- incremented result, to provide a fourth output;
determining, whether to complement or pass through, responsive to the upper carry out bit, the sign of the first incremented result, and the sign of the first non-incremented result, the first intermediate sum to provide a fifth output;
determining, whether to complement or pass through, responsive to the lower carry out bit, the sign of the second incremented result, and the sign of the second non-incremented result, the second intermediate sum to provide a sixth output;
selecting one of the first and second outputs responsive to the upper carry out bit; selecting one of the third and fourth outputs responsive to the lower carry out bit; and
providing a first final sum comprising the fifth output and the selected one of the first and second outputs; and
providing a second final sum comprising the sixth output and the selected one of the third and fourth outputs.”
See specification ([0087]) describing providing an intermediate sum of a more-significant portion and of a less-significant portion. See specification ([0088]) describing incrementing a more-significant portion of the second value and a less-significant portion of the second value. See specification ([0089]) describing determining a sign. See specification ([0090], [0091], [0092]) describing complementing or passing through to provide a first output, a second & fourth output, a third output, respectively. See specification ([0092]) describing complementing or passing through a fifth and sixth output. See specification ([0093]) describing selecting one of the first and second outputs. See specification ([0002]) describing providing a first final sum comprising the fifth output and second final sum comprising the sixth output. For these reasons, the claim recites Mental Processes and/or Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: an adder, the adder configured to receive a carry-sum formatted value corresponding to a first portion of input bits to the adder, the carry-sum formatted value including a carry value and a sum value, the adder configured to receive a second value corresponding to a second portion of input bits to the adder that do not overlap the first portion of input bits, pre-compute circuitry, a first multiplexer, and a second multiplexer. An adder, pre-compute circuitry, a first multiplexer, and a second multiplexer are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The receive limitations are examples of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). The claim recites limitations which are examples of generic computing elements that result in “apply it” on a computer. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites an adder, pre-compute circuitry, a first multiplexer, and a second multiplexer at a high level of generality, which merely result in “apply it” on a computer. The receive limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II)(i): Receiving or transmitting data over a network; MPEP 2106.05(d)(II)(iv): Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 8 is ineligible.
Claims 9-17 merely further limit the Mental Processes and/or Mathematical Concepts. Claims 9-17 do not recite any new additional elements.
Allowable Subject Matter
The statement of reasons for the indication of allowable subject matter can be found in the Non-Final Office Action filed 19 May 2025.
Response to Arguments
35 USC 101. Applicant argues the following in substance:
Applicant asserts that, claim 1 is similar in that it recites specific circuit components: an adder, pre-compute circuits, and a multiplexer. Claim 1 also recites operations that provide context as to how these specific circuit components must be connected with each other to implement those operations. For example, the specific operations recited in claim 1 could not be performed by the recited circuit components if those components were arranged in any random, general-purpose manner. Rather, the recited operations can only be realized when the recited circuit components are arranged in a particular way. This is why the circuit components of claim 1 are not "general purpose," but rather are a specific hardware implementation specially configured to achieve a specific result with several technical benefits (see response to office action filed August 19, 2025 ("Prior Response") for examples of such technical benefits). And while claim 1 does not expressly recite how the circuit components are connected to each other, claim 1 does extensively recite the operations performed by these circuit components, which necessarily limits the ways in which the circuit components can be coupled. Thus, claim 1 does not recite general purpose components, but rather, when considered as a whole, it recites specific circuit components that must be coupled in a particular way if the recited operations are to be realized. The general presence of such components will not suffice to implement the recited operations (See Remarks, Pg. 10, Para. 4-Pg. 11, Para. 1).
Examiner respectfully disagrees. As noted by Applicant in their argument, “claim 1 does not expressly recite how the circuit components are connected to each other” and thus it is not apparent, and would be improper, based on the broadest reasonable interpretation of the claim language to import such input/output connections and particular arrangement as described by the specification or drawings for the components recited (an adder, a first pre-compute circuit, a second pre-compute circuit, a third pre-compute circuit, and multiplexing circuitry). Further, claim 1 recites limitations such as “providing an intermediate sum of the carry value…a carry out bit; incrementing the second value…is a non-incremented result; determining a sign…non-incremented result; providing a final sum…second outputs” which are not performed by any recited component. Given that these limitations could be performed by any component recited or not and, in any arrangement of such recited or not components, the scope of arrangement is broadened and not arranged in a particular way as Applicant argues. In addition, there is no claim language recited which would further limit the input/output connections of the components or further describes the details of the components.
Applicant asserts that, Claim 1 recites specific circuit components that must be configured in a specific way for the recited operations to be achieved. Instead of a general purpose processor, which is essentially a "black box," the circuit components of claim 1 cannot achieve the recited operations if they are configured in a random, generic way. Rather, specific connections must be made between the circuit components and this must be done in a specific sequence. Thus, in contrast to the hypothetical claim's general purpose processor that does nothing more than "apply it" and achieves no improvements to the technical field, claim 1 recites components that must be configured in a specific way to achieve specific, complex operational outcomes that result in numerous improvements to the technical field (see Prior Response for a listing of such technical improvements) (See Remarks, Pg. 11, Para. 3-Pg. 12, Para. 1).
For at least these reasons, claim 1 recites "a particular machine" (i.e., the recited hardware circuit components, interconnected and sequentially positioned to achieve the recited operations) that implements the allegedly abstract idea (MPEP 2106.05(b)), and it does so in a way that results in improvements in the technical field (MPEP 2106.04(d)(1) and 2106.05(a); see also extensive descriptions of such technical improvements in the Prior Response). Accordingly, the circuitry represents a practical application of the allegedly abstract idea; step 2A, prong 2 of the Alice framework is satisfied; and claim 1 is patent- eligible. Because claim 1 is patent-eligible, the pending dependent claims are patent- eligible (See Remarks, Pg. 12, Para. 2).
Examiner respectfully disagrees. The claims do not recite a particular machine for at least the reasons stated in the response to Argument 1 above. The components identified as additional elements (an adder, a first pre-compute circuit, a second pre-compute circuit, a third pre-compute circuit, and multiplexing circuitry) are recited at a high level of generality which merely result in “apply it” on a computer, and/or merely generally link to a particular technological environment.
Further, Applicant argues that the components configured into a specific way integrate the abstract idea into a practical application by achieving an improvement to the technical field. Such improvements, as described in the Remarks filed 02/20/2026, are as follows:
Applicant asserts that such components “essentially combine a floating-point multiplication operation and a floating-point addition operation, which may be performed in a single instruction. Doing so, reduces execution time and increase throughput” and “enable a single rounding step, which improves precision, as well as efficiency”, however, these purported improvements are direct results of applying the mathematics and/or mental processes, the abstract idea, as opposed to the components cooperating together. No additional elements or combination of additional elements are claimed that result in the purported improvement beyond the mathematical concepts and/or mental steps.
With respect to “combining a floating-point multiplication operand and a floating-point addition operation which may be performed in a single instruction. Doing so, reduces execution time and increase throughput” it is the abstract idea, the manner of applying mathematical relationships and/or mental processes to compute a fused floating-point multiplication and addition that result in the purported improvement. See specification ([0021-0023]).
With respect to the “enable a single rounding step, which improves precision, as well as efficiency” it is the abstract idea, the manner of applying mathematical relationships and/or mental processes to floating point value parts that result in the purported improvement. See specification ([0080-0085]). See also specification ([0098], [0112], [0130], [0135], [0140]) which explicitly describes merging the 2’s complement and rounding operation.
See MPEP 2106.05(a)(II). “It is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology.” See also MPEP 2106.05. An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself."
Further, the additional elements do not integrate the abstract ideas into a practical application; thus, the claims are ineligible. See MPEP 2106.04(d)(I).
The courts have also identified limitations that did not integrate a judicial exception into a practical application: Merely reciting the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f); Adding insignificant extra-solution activity to the judicial exception, as discussed in MPEP § 2106.05(g); and Generally linking the use of a judicial exception to a particular technological environment or field of use, as discussed in MPEP § 2106.05(h).
Applicant asserts that, even if claim 1 were to fail step 2A, prong 2 of the Alice framework, claim 1 still satisfies step 2B because it recites additional claim elements that amount of significantly more than the allegedly abstract idea. In particular, Applicant urges the Examiner to consider the fact that while the recited circuit components may or may not be well-known, their particular arrangement-as defined by the operations the circuit components perform together, as a group-amounts to an inventive concept. MPEP 2106.05(d) ("a microprocessor that performs mathematical calculations and a clock that produces time data may individually be generic computer components that perform merely generic computer functions, but when combined may perform functions that are not generic computer functions and thus be an inventive concept"). As explained above, the recited circuit components are hardware components that have a particular arrangement (e.g., interconnections and sequence) that is dictated by the operations they must perform together, and thus, they form a specific circuit. That specific circuit amounts to significantly more than the allegedly abstract idea (See Remarks, Pg. 12, Para. 3).
Examiner respectfully disagrees. Examiner maintains that such “particular arrangement-as defined by the operations” is not reflected in the claims in such a manner that Applicant argues. See response to Argument 1. The specific circuit does not amount to significantly more than the abstract idea because the recited circuit components are merely used as tools to accomplish the claimed functionality that result in “apply it” (or an equivalent) on a computer. Integral use of a machine to achieve performance of a method may integrate the recited judicial exception into a practical application. See MPEP 2106.05(b)(II).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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