DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/23/2025 has been entered.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 8, 15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., an abstract idea) without significantly more.
Regarding claim 15, under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: a machine.
Under the Alice Framework Step 2A Prong 1 analysis, claim 1 recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“compute a sum of the first portions of the first and second addends and provide a first carry out bit associated with the first sum, wherein each of the first and second addends has a number of bits not expressible as an integer power of two;
compute a first non-incremented sum of the second portions of the first and second addends;
provide a non-incremented carry out bit associated with the first non-incremented sum;
compute a first incremented sum of the second portions of the first and second addends; and
provide an incremented carry out bit associated with the first incremented sum;
select one of the first non-incremented sum and the first incremented sum, responsive to the first carry out bit, as a second sum;
compute a second non-incremented sum of the third portions of the first and second addends; and
compute a second incremented sum of the third portions of the first and second addends;
select one of the second non-incremented sum and the second incremented sum, responsive to the non-incremented carry out bit, the incremented carry out bit, and the first carry out bit, as a third sum;
wherein a final sum comprises the third sum concatenated with the second sum, concatenated with the first sum, and
wherein each of the first portions is a first number of bits, each of the second portions is a second number of bits that is less than the first number of bits, and each of the third portions is a third number of bits that is less than the second number of bits, each of the first number of bits, the second number of bits, and the third number of bits being expressible as an integer power of two.”
See specification describing computing a first sum ([0018]) and providing a first carry output bit ([0020], [0022]). See specification describing addends not expressible as an integer power of two ([0014], [0017]). See specification describing computing a first non-incremented sum ([0021]) and providing a non-incremented carry out bit ([0055]). See specification describing computing a first incremented sum ([0018]) and providing an incremented carry out bit ([0055]). See specification describing selecting ([0055]). See specification describing computing a second non-incremented sum and providing a second incremented sum ([0057]). See specification describing selecting and final sum ([0057]). See specification describing the first, second, and third portions of the number of bits ([0003], [0059-0061]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a first adder, a second adder, a third adder, a device, a first multiplexing circuitry, a second multiplexing circuitry, receive a first portion of each of a first and second addends, receive a second portion of each of the first and second addends, receive a third portion of each of the first and second addends, having a first architecture, and having a second architecture that is different than the first architecture. A first adder, a second adder, a third adder, a device, a first multiplexing circuitry, a second multiplexing circuitry, a first architecture, and a second architecture that is different than the first architecture are recited at a high level of generality, and are examples of generic computing elements, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The claim recites limitations which are examples of generic computing elements that result in “apply it” on a computer. The receive limitations are examples of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate this judicial exception into a particular application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claim recites a first adder, a second adder, a third adder, a device, a first multiplexing circuitry, a second multiplexing circuitry, a first architecture, and a second architecture that is different than the first architecture at a high-level of generality, and/or merely generally links the use of the abstract idea to a particular technological environment. The claim recites limitations which are examples of generic computing element that result in “apply it” on a computer. The receive limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II)(i): Receiving or transmitting data over a network). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 15 is ineligible.
Claim 1 is directed to a method that would be performed by the device of claim 15. All limitations recited in claim 1 are practiced by the device of claim 15. The claim 15 analysis equally applies to claim 1.
Claim 8 is directed to a device of which all limitations are recited by the device of claim 15. The claim 15 analysis equally applies to claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20030115237 A1 Fletcher (hereinafter “Fletcher”) in view of Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective (4th. ed.). Addison-Wesley Publishing Company, USA. (hereinafter “Weste”) in view of US 20050177611 A1 Awaka et al. (hereinafter “Awaka”) and further in view of US 6832235 B1 Muramatsu et al. (hereinafter “Muramatsu”).
Claims 15-20 will be addressed first, followed by claims 8-14, and finally followed by claims 1-7.
Regarding claim 15, Fletcher teaches the device (Fig. 1, 100, [0015]), comprising:
a first adder circuit (Fig. 1, 1st Group, [0004], [0014-0015]) having a first architecture (Fig. 1, 1st Group comprises (2) Prop/Gen Block 111 and 110, (1) Group 1 Carry Generation Block 131, (3) Final XNOR Block 160, 161, and 162; [0015]) and configured to receive (Fig. 6, 601, [0039] Group 1) a first portion of each of first and second addends (Fig. 1, first – A-1 and A0, second – B1 and B0, [0014], [0020]), compute a sum (Fig. 1, Sum-0 or Sum-1, [0019-0020]) -of the first portions of first and second addends (Fig. 1, first – A-1 and A0, second – B1 and B0, [0014], [0020]) and provide a first carry out bit (Fig. 1, C2: C2a and C2b, [0017-0018]) associated with the first sum, wherein each of the first and second addends has a number of bits not expressible as an integer power of two (3-bits from the second portion of the first/second addends as 3 is not expressible as an integer power of two // Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]);
a second adder circuit (Fig. 1, 2nd Group, [0004], [0014-0015]) having a second architecture that is different than the first architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]), the second adder circuit configured to:
receive (Fig. 6, 601, [0039] Group 2) a second portion of each of the first and second addends (Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]);
compute a first non-incremented sum (Fig. 1, A4 xor B4, A3 xor B3, A2 xor B2, [0019]) of the second portions of the first and second addends (Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]);
provide a non-incremented carry out bit associated with the first non-incremented sum (Fig. 1, C5: C5a and C5b, [0018]); and a second sum (Fig. 1, Sum-4 or Sum-3 or Sum-2, [0020]); and
a third adder circuit (Fig. 1, 3rd Group, [0004], [0014-0015]) configured to:
receive (Fig. 6, 601, [0039] Group 3) a third portion of each of the first and second addends (Fig. 1, first – A-10, A9, A-8, A7, A6, and A5, second – B10, B9, B8, B7, B6, and B5, [0014]);
compute a second non-incremented sum (Fig. 1, A10 xor B10, A9 xor B9, A8 xor B8, A7 xor B7, A6 xor B6, A5 xor B5, [0018-0019]) of the third portion of the first and second addends (Fig. 1, first – A-10, A9, A-8, A7, A6, and A5, second – B10, B9, B8, B7, B6, and B5, [0014]); and
the third adder circuitry (Fig. 1, 3rd Group, [0004], [0014-0015]) a third sum (Fig. 1, Sum-10 or Sum-9 or Sum-8 or Sum-7 or Sum-6 or Sum-5, [0020]);
wherein a final sum comprises the third sum concatenated with the second sum, concatenated with the first sum (Fig. 1, 3rd group - Sum10-5, 2nd group - Sum4-2, 1st group - Sum1-0, [0014], [0004]), and
wherein each of the first portions (Fig. 1, first – A-1 and A0, second – B1 and B0, [0014], [0020]) is a first number of bits (Fig. 1, A – 2 bits, B – 2 bits, [0014]), each of the second portions (Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]) is a second number of bits (Fig. 1, A – 3 bits, B – 3 bits, [0014]), and each of the third portions (Fig. 1, first – A-10, A9, A-8, A7, A6, and A5, second – B10, B9, B8, B7, B6, and B5, [0014]) is a third number of bits (Fig. 1, A – 6 bits, B – 6 bits, [0014]), each of the first number of bits being expressible as an integer power of two (2 bits which is expressible as a integer power of 2 (
2
1
) // Fig. 1, A – 2 bits, B – 2 bits, [0014]).
Although Fletcher teaches non-incremented sums, they are silent with specifying incremented sums and incremented carry out bit. They are silent in detail to disclosing compute a first incremented sum; provide an incremented carry out bit associated with the first incremented sum; including first multiplexing circuitry select one of the first non-incremented sum and the first incremented sum, responsive to the first carry out bit, as a second sum; compute a second incremented sum; and including second multiplexing circuitry select one of the second non-incremented sum and the second incremented sum, responsive to the non-incremented carry out bit, the incremented carry out bit, and the first carry out bit, as a third sum; a second number of bits that is less than the first number of bits and a third number of bits that is less than the second number of bits. Further, Fletcher is silent with disclosing the second number of bits and the third number of bits being expressible as an integer power of two.
Weste teaches compute a first incremented sum (Fig. 11.25, output of black cell 7:4); provide an incremented carry out bit (Pg. 445, Para. 1, assuming a carry-in of 1) associated with the first incremented sum; first multiplexing circuitry (Fig. 11.25, gray cells from 7 to 4, Pg. 445, Para. 1) select one of the first non-incremented sum and the first incremented sum, responsive (Fig. 11.25, gray cells from 7 to 4; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell), to the first carry out bit, as a second sum; compute a second incremented sum (Fig. 11.25, output of black cell 15:12); and second multiplexing circuitry (Fig. 11.25, gray cells from 15 to 12, Pg. 445, Para. 1) select one of the second non-incremented sum and the second incremented sum, responsive (Fig. 11.25, gray cells from 15 to 12; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) to the non-incremented carry out bit, the incremented carry out bit (Pg. 445, Para. 1, assuming a carry-in of 1), and the first carry out bit, as a third sum.
Regarding claim 1, the preamble is given patentable weight. The body of claim 1 contains the limitation “the device”, as first recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the limitations recited in the claims. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher’s adder with Weste’s incremented sums and carry output bits because they are in the claimed invention’s same field of endeavor of adders with PG logic (Pg. 445, Para. 2). It would have been obvious to one of ordinary skill in the art to implement the incremented sums and carry output bits, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). Making this modification would be beneficial, as Fletcher’s adder can accelerate its computations by using its critical path to make appropriate optimizations.
Fletcher in view of Weste’s are silent with disclosing a second number of bits that is less than the first number of bits and a third number of bits that is less than the second number of bits. Further, Weste and Fletcher in view of Weste are silent with disclosing the second number of bits and the third number of bits being expressible as an integer power of two.
Awaka teaches a second number of bits that is less than (Fig. 3, a16:30, b16:30 contain (15 bits) which is less than a0:15, b0:15 that contain (16 bits), [0096]) the first number of bits and a third number of bits that is less than (Fig. 3, a31:39, b31:39 contain (9 bits) which is less than a16:30, b16:30 contain (15 bits), [0096]) the second number of bits.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher in view of Weste’s modified adder with Awaka’s bit sizing feature because they are in the claimed invention’s same field of endeavor of adders with propagate logic ([abstract]). It would have been obvious to one of ordinary skill in the art to implement the specific bit sizing, as it allows the system to advance the timing of computing at different ranges: lower, intermediate, upper ([0197]). Making this modification would be beneficial, as Fletcher in view of Weste’s modified adder can accelerate its computations by performing the addition at a high speed while the circuit scale and power consumption are reduced ([0198]).
Fletcher in view of Weste in view of Awaka are silent with disclosing the second number of bits and the third number of bits being expressible as an integer power of two.
Muramatsu discloses the second number of bits and the third number of bits being expressible as an integer power of two (Fig. 4 “23” with bits A[11:8], B[11:8] for the ‘second number of bits’ where A,B have each four bits (
2
2
); Fig. 4 “24” with bits A[15:12], B[15:12] for the ‘third number of bits’ where A,B have each four bits (
2
2
); co. 1 ln. 40-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher in view of Weste in view of Awaka’s modified adder with Muramatsu’s second and third number of bits expressible as an integer power of two feature because they are in the claimed invention’s same field of endeavor of adders ([abstract]). It would have been obvious to one of ordinary skill in the art to implement the expressible as an integer power of two representation, as it would have been obvious to try different number of bit widths per portions with predictable results yielded given that the bit widths could vary based on the original bit widths of the operands and given the finite number of bits to represent the portions in practicality. Making this modification would be beneficial, as Fletcher in view of Weste in view of Awaka’s modified adder can have beneficial improvements by providing greater control to circuit configuration and optimization based on these bit widths (co. 1 ln. 45-52), thus enhancing performance of the modified circuitry to suit the particular design objective.
Regarding claim 16, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein:
the first adder circuit includes (see claim 15 mapping) a first group propagate-generate (PG) circuit (Fig. 1, 131, [0015], [0017]) configured to determine first carry bits for the first portion of the first and second addends (see claim 15 mapping),
wherein the second adder circuit includes (see claim 15 mapping) a second group PG circuit (Fig. 1, 132, [0015], [0018]) configured to determine second carry bits for the first non-incremented sum (see claim 15 mapping),
wherein the second adder circuit includes (see claim 15 mapping) a third group PG circuit (Fig. 1, 133, [0015], [0018]) configured to determine third carry bits (Fig. 1, C11: C11a and C11b, [0014], [0018]), and
wherein the second and third group PG circuits do depend on the first group PG circuit ([0025]).
Although Fletcher teaches the first, second, and third group PG circuits, they are silent with disclosing the first incremented sum and the second and third group do not depend on the first group.
Weste teaches: the first incremented sum (Fig. 11.25, output of black cell 7:4);
do not depend (Fig. 11.25, third group – black cells from 15 to 13, second group – black cells from 11 to 9, first group – black cells from 7 to 5; Pg. 445, Para. 2, ripple chains).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher’s adder with Weste’s incremented sums because they are in the claimed invention’s same field of endeavor of adders with PG logic (Pg. 445, Para. 2). It would have been obvious to one of ordinary skill in the art to implement the incremented sums and does not depend limitations, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). Currently, Fletcher has the second group depend on the first group’s carry input to continue performing the addition, and subsequently the third group depend on the second group ([0018], [0025]). However, enabling these groups to be independent and having computations precomputed further supports accelerating the critical path and optimizing effectively. Making this modification would be beneficial, as Fletcher’s adder can accelerate its computations by using its critical path to make appropriate optimizations.
Regarding claim 17, in addition to the teachings addressed in the claim 16 analysis, the rejection of claim 16 is incorporated and Fletcher teaches the device wherein:
the third group PG circuit depends on the second group PG circuit ([0018]).
Regarding claim 18, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein: the third adder circuit, the second non-incremented sum, third sum, first carry out bit (see claim 15 mapping).
Fletcher is silent to disclosing the second multiplexing circuitry; select one of the second non-incremented sum and the second incremented sum as a first intermediate sum responsive to the non-incremented carry out bit; select one of the second non-incremented sum and the second incremented sum as a second intermediate sum responsive to the incremented carry out bit; and select one of the first and second intermediate sums as the third sum responsive to the first carry out bit.
Weste teaches: the second multiplexing circuitry (Fig. 11.25, gray cells from 15 to 12, Pg. 445, Para. 1); select one of the second non-incremented sum and the second incremented sum (Fig. 11.25, gray cells from 15 to 12; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) as a first intermediate sum responsive (Fig. 11.25, output of gray cell at 13) to the non-incremented carry out bit; select one of the second non-incremented sum and the second incremented sum (Fig. 11.25, gray cells from 15 to 12; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) as a second intermediate sum responsive (Fig. 11.25, output of gray cell at 14) to the incremented carry out bit (Pg. 445, Para. 1, assuming a carry-in of 1); and select one of the first and second intermediate sums as the third sum responsive (Fig. 11.25, gray cells from 15 to 13; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) to the first carry out bit.
The motivation to combine provided with respect to claim 15 equally applies to claim 18.
Regarding claim 19, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein:
the first portion includes
2
n
bits, the second portion includes at most
2
n
-
2
bits, and the third portion includes at most
2
n
-
4
bits (Fig. 1, first - bits A1-, A0 and B1, B0, second – bits A-4, A3, A2, and B4, B3, B2, third – bits A-10, A9, A-8, A7, A6, A5, and B10, B9, B8, B7, B6, B5, [0014]), wherein n is an integer ([0014] indices from 0 to 10).
Regarding claim 20, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein:
the first portion is less significant than the second portion, which is less significant than the third portion (Fig. 1, 3rd group - Sum10-5, 2nd group - Sum4-2, 1st group - Sum1-0, [0014], [0003-0004]).
Claims 8-10, 14 are directed to a device that is similarly recited in claim 15. Claims 8-10, 14 recites the same limitations as those in claims 15-17, 19, respectively. The claims 15-17, 19 analysis equally applies, and claims 8-10, 14 are similarly rejected.
Regarding claim 11, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Fletcher teaches the device wherein:
the first adder circuit includes a tree adder (Fig. 3, 316, 312, 317, 318, 319, 320 group, [0025]) having the first architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]),
the second adder circuit includes a carry select adder (Fig. 4, 434, 426, 435, 430, 431, 432, 433, 437 group, [0028-0030]) having the second architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]).
Although Fletcher teaches the second adder circuit includes a carry adder, they are silent with disclosing the carry adder as a carry select adder.
Weste teaches a carry select adder (Fig. 11.24, Carry-select adder, Pg. 444, 11.2.2.7; Pg. 445, Para. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher’s adder with Weste’s carry select adder because they are in the claimed invention’s same field of endeavor of adders with PG logic (Pg. 445, Para. 2). It would have been obvious to one of ordinary skill in the art to implement the carry select adder, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). It would have been obvious to implement this simple substitution of the carry select adder design as the results of doing so are predictable. Furhter, Weste teaches that it is a standard logic design technique to accelerate the critical path by precomputing the outputs for both possible inputs, which is what the carry select adder does (Pg. 444, 11.2.2.6). Making this modification would be beneficial, as Fletcher’s adder can accelerate its computations by using its critical path to make appropriate optimizations.
Regarding claim 12, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Fletcher teaches the device wherein:
the first sum, the non-incremented sum and the incremented sum are computed concurrently ([0040]).
Regarding claim 13, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Fletcher teaches the device wherein:
the first portion includes eight bits (Fig. 1, A-1 A0, and B1,B0, [0014], [0020]) and the second portion includes two bits (Fig. 1, A-4, A3, A2, and B4, B3, and B2, [0014])
Fletcher teaches the first portion including two bits, but is silent to disclosing it as eight bits.
Weste teaches first portion includes eight bits (Fig. 11.25, 7 to 0).
The motivation to combine provided with respect to claim 15 equally applies to claim 13.
Claim 1 is directed to a method that would be performed by the device of claim 15. The claim 15 analysis equally applies. Additionally, Fletcher teaches:
an x-bit adder (Fig. 1, 100, [0014] 12-bit adder).
Claims 2-3, 4-5, 7 are directed to a method that would be performed by the device of claim 15 and the device of claim 8. The claims 16-17, 11-12, 19 analysis equally applies, respectively, claims 2-3, 4-5, 7 are similarly rejected.
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Fletcher teaches the device wherein:
x=10 and the second portion includes two bits (Fig. 1, A-4, A3, A2, and B4, B3, and B2, [0014])
Fletcher teaches a 12-bit and 23-bit adder ([0014]), but is silent to specifying a 10-bit adder.
Weste teaches a 10-bit adder (Pg. 436, Sec. 11.2.2.1, N-bit adder; Fig. 11.25 includes 10-bits in its 16-bit adder).
The motivation to combine provided with respect to claim 15 equally applies to claim 6.
Response to Arguments
35 USC 101. Applicant argues the following in substance:
1) Applicant asserts that, the arrangements captured in claims 1, 8 and 15 recognize an inefficiency with tree-adders for non-power-of-2 width additions. In the case in which the addends are divided into two portions, one of which includes the lower (less-significant) bits and the other includes the upper (more significant) bits, the upper bits beyond the power-of-2 break point do not contain a full tree structure. As a result, the tree structure for the upper bits would finish its computations before the tree structure for the lower (less-significant) bits completes its computations. The arrangements of independent claims 1 and 8 solve the problem by using a different type of adder architecture, e.g., a carry select adder, on the upper bits, and a multiplexer that receives a carry out bit from a tree adder that operates on the lower bits. With this arrangement, outputs from computations on the upper bits can be provided in less time than if those outputs were computed by extending the logic of the adder used on the lower bits. Specification, e.g., para. [0021]. This inventive hybrid approach, using two different addition architectures, provides improvements in addition computations, particularly for non-power-of-2 width additions, and even more so for such additions that occur on a critical path in a processor where timing is even more important (see Remarks p. 7).
Examiner respectfully disagrees. The architecture for the first, second, and third adders recited varies from claims 1, 8, and 15.
In claim 1, there does not appear to be significantly more recited that distinguishes between the first and second adder architectures other than nominally reciting “first adder” and “second adder”.
In claim 8, there does not appear to be significantly more recited that distinguishes between the first and second adder architectures other than nominally reciting “first adder”, “second adder”, “a first architecture”, and “a second architecture that is different than the first architecture”.
In claim 15, there does not appear to be significantly more recited that distinguishes between the first and second adder architectures other than nominally reciting “first adder circuit”, “second adder circuit”, “a first architecture”, “a second architecture that is different than the first architecture”, “the second adder circuit including first multiplexing circuitry”, “third adder circuit”, and “the third adder circuit including second multiplexing circuitry”.
The claims do not appear to recite significant architectural differences in the adders that aligns with Applicant’s arguments of “the particular arrangements” of a “hybrid approach using two different addition architectures, provid[ing] improvement in addition,” that would meaningfully result in the particular arrangements of the adders determined as a particular machine. See MPEP 2106.05(b). The claims primarily recite functionality the adders perform, but not necessarily the specific components in those respective adders that carry out those functions and in an integral manner.
With respect to “improvements in addition computations” it is the abstract idea, the manner of applying the mathematical relationships to perform the computation of values in portions which yields this purported improvement. See specification ([0057]).
See MPEP 2106.05(a)(I). “Examples that the courts have indicated may not be
sufficient to show an improvement in computer-functionality”.
See MPEP 2106.05(a)(II). “It is important to keep in mind that an improvement in
the abstract idea itself (e.g. a recited fundamental economic concept) is not an
improvement in technology.”
See also MPEP 2106.05. An inventive concept "cannot be furnished by the
unpatentable law of nature (or natural phenomenon or abstract idea) itself."
2) Applicant asserts that, each of claims 1, 8 and 15 recite structure and functionality to realize the above-described improvements. Thus, these claims are not directed to mathematical concepts. Moreover, even assuming arguendo that the claims are directed to a judicial exception, each of claims 1, 8 and 15 recites elements and functionality ( or operations) that integrate the exception into a practical application. Using first and second adders (or adder circuits) having different architectures, e.g., one is a tree adder and the other is a carry select adder, improve the efficiency and/or performance of addition operations where the addends are not of a power-of-2 width. See, e.g., specification, para. [0014] (See Remarks p. 8).
Examiner respectfully disagrees. The differences in architectures of the adders does not integrate the abstract idea into a particular application because the adders are recited at high-level of generality or a generic computer component and as discussed in the response to argument 1 above. Merely adding a generic computer, generic computer components, or a programmed computer to perform generic computer functions does not automatically overcome an eligibility rejection. See MPEP 2106.05(b)(I).
35 USC 103. Applicant’s arguments, see Remarks p. 8, bottom, filed 10/23/2025, with respect to the rejection(s) of claim(s) 1, 8, and 15 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Muramatsu, as necessitated by the amendment.
Applicant asserts that, the cited references do not teach the arrangement of claim 15. Fletcher's look-ahead carry adder circuit 100 does not include any multiplexing circuitry. There is no disclosure in Fletcher that any two of the carry generation blocks 131, 132, 133 are of different architectures. Moreover, there is no disclosure in Fletcher that each of the different portions of the addends has a different number of bits than each of the other portions (see Remarks p. 9 top).
Examiner respectfully disagrees. Weste is relied on to teach the second multiplexing circuitry as incorporated by the modification of Fletcher’s third adder circuitry.
Regarding the limitation of “different architectures”, Fletcher’s Fig. 1 depicts a 1st, 2nd, and 3rd group for the first, second, and third adder circuitry, respectively. Each group contains different number of prop/gen blocks and XNOR blocks connected before/after the carry generation block, and therefore each adder has ‘different architectures’.
The 1st group processes bits [1:0], the 2nd group processes bits [4:2], and the 3rd group processes bits [10:5] of both operands A and B.
Applicant asserts that, Weste does not offset these deficiencies in Fletcher. The adders in FIGs. 11.24 and 11.25 of Weste each process the same number of bits, and the third adder, which processes bits 16: 13, does not select, as a sum, one of a second non-incremented sum and a second incremented sum, responsive to non-incremented and incremented carry out bits from the second adder and a carry out bit from a first adder. In Weste, there is no selection signal generated by the first adder and used by the third adder to select a particular sum.
Moreover, there is no indication in Weste that the first two adders are of different architectures. Awaka, which is applied for the different numbers of the bits, does not remedy the shortcomings of the Fletcher/Weste combination (see Remarks p. 9 middle).
Examiner respectfully disagrees. Weste is not relied upon for this part of the rejection as Fletcher previously disclosed the limitations “number of bits”, “third adder”, “different architectures”. Weste discloses selecting and the incremented and non-incremented carry out bits as the ‘selection signal’.
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151