DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 12 May 2026 has been entered. The amendments to the claims have overcome the 35 USC 101 rejections. Claims 1-4, 6-11, 13-22 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “the first adder circuit includes a tree adder having the first architecture, and the second adder circuit includes a carry select adder having the select architecture”. However, the metes and bounds of this limitation are indefinite. It is indefinite as to whether the instances of “a tree adder” and “a carry select adder” in claim 4 are meant to antecedently refer back to the same adders in claim 1 for which the claim depends on, or if these instances are meant to be new, separate additional adders. Corresponding claim 11, which depends on claim 8, recites a similar limitation and the analysis for claim 4 similarly applies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11, 13-22 are rejected under 35 U.S.C. 103 as being unpatentable over US 20030115237 A1 Fletcher (hereinafter “Fletcher”) in view of Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective (4th. ed.). Addison-Wesley Publishing Company, USA. (hereinafter “Weste”) in view of US 20050177611 A1 Awaka et al. (hereinafter “Awaka”) and further in view of US 6832235 B1 Muramatsu et al. (hereinafter “Muramatsu”).
Claims 15-20 will be addressed first, followed by claims 1-4, 6-7, 21, and finally followed by claims 8-10, 11-14, 22.
Regarding claim 15, Fletcher teaches the device (Fig. 1, 100, [0015]), comprising:
a first adder circuit (Fig. 1, 1st Group, [0004], [0014-0015]) including a tree adder (Fig. 3, 316, 312, 317, 318, 319, 320 group, [0025]) having a first architecture (Fig. 1, 1st Group comprises (2) Prop/Gen Block 111 and 110, (1) Group 1 Carry Generation Block 131, (3) Final XNOR Block 160, 161, and 162; [0015]) and configured to receive (Fig. 6, 601, [0039] Group 1) a first portion of each of first and second addends (Fig. 1, first – A-1 and A0, second – B1 and B0, [0014], [0020]), compute a sum (Fig. 1, Sum-0 or Sum-1, [0019-0020]) -of the first portions of first and second addends (Fig. 1, first – A-1 and A0, second – B1 and B0, [0014], [0020]) and provide a first carry out bit (Fig. 1, C2: C2a and C2b, [0017-0018]) associated with the first sum, wherein each of the first and second addends has a number of bits not expressible as an integer power of two (3-bits from the second portion of the first/second addends as 3 is not expressible as an integer power of two // Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]);
a second adder circuit (Fig. 1, 2nd Group, [0004], [0014-0015]) including a carry select adder (Fig. 4, 434, 426, 435, 430, 431, 432, 433, 437 group, [0028-0030]) having a second architecture that is different than the first architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]), the second adder circuit configured to:
receive (Fig. 6, 601, [0039] Group 2) a second portion of each of the first and second addends (Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]);
compute a first non-incremented sum (Fig. 1, A4 xor B4, A3 xor B3, A2 xor B2, [0019]) of the second portions of the first and second addends (Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]);
provide a non-incremented carry out bit associated with the first non-incremented sum (Fig. 1, C5: C5a and C5b, [0018]); and a second sum (Fig. 1, Sum-4 or Sum-3 or Sum-2, [0020]); and
in parallel ([0040]) with the compute of the first non-incremented sum (Fig. 1, C5: C5a and C5b, [0018]),
a third adder circuit (Fig. 1, 3rd Group, [0004], [0014-0015]) configured to:
receive (Fig. 6, 601, [0039] Group 3) a third portion of each of the first and second addends (Fig. 1, first – A-10, A9, A-8, A7, A6, and A5, second – B10, B9, B8, B7, B6, and B5, [0014]);
compute a second non-incremented sum (Fig. 1, A10 xor B10, A9 xor B9, A8 xor B8, A7 xor B7, A6 xor B6, A5 xor B5, [0018-0019]) of the third portion of the first and second addends (Fig. 1, first – A-10, A9, A-8, A7, A6, and A5, second – B10, B9, B8, B7, B6, and B5, [0014]); and
the third adder circuitry (Fig. 1, 3rd Group, [0004], [0014-0015]) a third sum (Fig. 1, Sum-10 or Sum-9 or Sum-8 or Sum-7 or Sum-6 or Sum-5, [0020]);
wherein a final sum comprises the third sum concatenated with the second sum, concatenated with the first sum (Fig. 1, 3rd group - Sum10-5, 2nd group - Sum4-2, 1st group - Sum1-0, [0014], [0004]), and
wherein each of the first portions (Fig. 1, first – A-1 and A0, second – B1 and B0, [0014], [0020]) is a first number of bits (Fig. 1, A – 2 bits, B – 2 bits, [0014]), each of the second portions (Fig. 1, first – A-4, A3, and A2, second – B4, B3, and B2, [0014]) is a second number of bits (Fig. 1, A – 3 bits, B – 3 bits, [0014]), and each of the third portions (Fig. 1, first – A-10, A9, A-8, A7, A6, and A5, second – B10, B9, B8, B7, B6, and B5, [0014]) is a third number of bits (Fig. 1, A – 6 bits, B – 6 bits, [0014]), each of the first number of bits being expressible as an integer power of two (2 bits which is expressible as a integer power of 2 (
2
1
) // Fig. 1, A – 2 bits, B – 2 bits, [0014]).
Although Fletcher teaches non-incremented sums, they are silent with specifying incremented sums and incremented carry out bit. They are silent in detail to disclosing compute a first incremented sum; provide an incremented carry out bit associated with the first incremented sum; including first multiplexing circuitry select one of the first non-incremented sum and the first incremented sum, responsive to the first carry out bit, as a second sum; compute a second incremented sum; and including second multiplexing circuitry select one of the second non-incremented sum and the second incremented sum, responsive to the non-incremented carry out bit, the incremented carry out bit, and the first carry out bit, as a third sum; a second number of bits that is less than the first number of bits and a third number of bits that is less than the second number of bits. Further, Fletcher is silent with disclosing the second number of bits and the third number of bits being expressible as an integer power of two. Further, Fletcher appears to be silent to explicitly disclosing a carry select adder.
Weste teaches compute a first incremented sum (Fig. 11.25, output of black cell 7:4); provide an incremented carry out bit (Pg. 445, Para. 1, assuming a carry-in of 1) associated with the first incremented sum; first multiplexing circuitry (Fig. 11.25, gray cells from 7 to 4, Pg. 445, Para. 1) select one of the first non-incremented sum and the first incremented sum, responsive (Fig. 11.25, gray cells from 7 to 4; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell), to the first carry out bit, as a second sum; compute a second incremented sum (Fig. 11.25, output of black cell 15:12); and second multiplexing circuitry (Fig. 11.25, gray cells from 15 to 12, Pg. 445, Para. 1) select one of the second non-incremented sum and the second incremented sum, responsive (Fig. 11.25, gray cells from 15 to 12; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) to the non-incremented carry out bit, the incremented carry out bit (Pg. 445, Para. 1, assuming a carry-in of 1), and the first carry out bit, as a third sum. Weste further discloses a carry select adder (Fig. 11.24, Carry-select adder, Pg. 444, 11.2.2.7; Pg. 445, Para. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher’s adder with Weste’s incremented sums and carry output bits because they are in the claimed invention’s same field of endeavor of adders with PG logic (Pg. 445, Para. 2). It would have been obvious to one of ordinary skill in the art to implement the incremented sums and carry output bits, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). It would have been obvious to one of ordinary skill in the art to implement the carry select adder, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). It would have been obvious to implement this simple substitution of the carry select adder design as the results of doing so are predictable. Further, Weste teaches that it is a standard logic design technique to accelerate the critical path by precomputing the outputs for both possible inputs, which is what the carry select adder does (Pg. 444, 11.2.2.6). Making this modification would be beneficial, as Fletcher’s adder can accelerate its computations by using its critical path to make appropriate optimizations.
Fletcher in view of Weste’s are silent with disclosing a second number of bits that is less than the first number of bits and a third number of bits that is less than the second number of bits. Further, Weste and Fletcher in view of Weste are silent with disclosing the second number of bits and the third number of bits being expressible as an integer power of two.
Awaka teaches a second number of bits that is less than (Fig. 3, a16:30, b16:30 contain (15 bits) which is less than a0:15, b0:15 that contain (16 bits), [0096]) the first number of bits and a third number of bits that is less than (Fig. 3, a31:39, b31:39 contain (9 bits) which is less than a16:30, b16:30 contain (15 bits), [0096]) the second number of bits.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher in view of Weste’s modified adder with Awaka’s bit sizing feature because they are in the claimed invention’s same field of endeavor of adders with propagate logic ([abstract]). It would have been obvious to one of ordinary skill in the art to implement the specific bit sizing, as it allows the system to advance the timing of computing at different ranges: lower, intermediate, upper ([0197]). Making this modification would be beneficial, as Fletcher in view of Weste’s modified adder can accelerate its computations by performing the addition at a high speed while the circuit scale and power consumption are reduced ([0198]).
Fletcher in view of Weste in view of Awaka are silent with disclosing the second number of bits and the third number of bits being expressible as an integer power of two.
Muramatsu discloses the second number of bits and the third number of bits being expressible as an integer power of two (Fig. 4 “23” with bits A[11:8], B[11:8] for the ‘second number of bits’ where A,B have each four bits (
2
2
); Fig. 4 “24” with bits A[15:12], B[15:12] for the ‘third number of bits’ where A,B have each four bits (
2
2
); co. 1 ln. 40-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher in view of Weste in view of Awaka’s modified adder with Muramatsu’s second and third number of bits expressible as an integer power of two feature because they are in the claimed invention’s same field of endeavor of adders ([abstract]). It would have been obvious to one of ordinary skill in the art to implement the expressible as an integer power of two representation, as it would have been obvious to try different number of bit widths per portions with predictable results yielded given that the bit widths could vary based on the original bit widths of the operands and given the finite number of bits to represent the portions in practicality. Making this modification would be beneficial, as Fletcher in view of Weste in view of Awaka’s modified adder can have beneficial improvements by providing greater control to circuit configuration and optimization based on these bit widths (co. 1 ln. 45-52), thus enhancing performance of the modified circuitry to suit the particular design objective.
Regarding claim 16, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein:
the first adder circuit includes (see claim 15 mapping) a first group propagate-generate (PG) circuit (Fig. 1, 131, [0015], [0017]) configured to determine first carry bits for the first portion of the first and second addends (see claim 15 mapping),
wherein the second adder circuit includes (see claim 15 mapping) a second group PG circuit (Fig. 1, 132, [0015], [0018]) configured to determine second carry bits for the first non-incremented sum (see claim 15 mapping),
wherein the second adder circuit includes (see claim 15 mapping) a third group PG circuit (Fig. 1, 133, [0015], [0018]) configured to determine third carry bits (Fig. 1, C11: C11a and C11b, [0014], [0018]), and
wherein the second and third group PG circuits do depend on the first group PG circuit ([0025]).
Although Fletcher teaches the first, second, and third group PG circuits, they are silent with disclosing the first incremented sum and the second and third group do not depend on the first group.
Weste teaches: the first incremented sum (Fig. 11.25, output of black cell 7:4);
do not depend (Fig. 11.25, third group – black cells from 15 to 13, second group – black cells from 11 to 9, first group – black cells from 7 to 5; Pg. 445, Para. 2, ripple chains).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher’s adder with Weste’s incremented sums because they are in the claimed invention’s same field of endeavor of adders with PG logic (Pg. 445, Para. 2). It would have been obvious to one of ordinary skill in the art to implement the incremented sums and does not depend limitations, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). Currently, Fletcher has the second group depend on the first group’s carry input to continue performing the addition, and subsequently the third group depend on the second group ([0018], [0025]). However, enabling these groups to be independent and having computations precomputed further supports accelerating the critical path and optimizing effectively. Making this modification would be beneficial, as Fletcher’s adder can accelerate its computations by using its critical path to make appropriate optimizations.
Regarding claim 17, in addition to the teachings addressed in the claim 16 analysis, the rejection of claim 16 is incorporated and Fletcher teaches the device wherein:
the third group PG circuit depends on the second group PG circuit ([0018]).
Regarding claim 18, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein: the third adder circuit, the second non-incremented sum, third sum, first carry out bit (see claim 15 mapping).
Fletcher is silent to disclosing the second multiplexing circuitry; select one of the second non-incremented sum and the second incremented sum as a first intermediate sum responsive to the non-incremented carry out bit; select one of the second non-incremented sum and the second incremented sum as a second intermediate sum responsive to the incremented carry out bit; and select one of the first and second intermediate sums as the third sum responsive to the first carry out bit.
Weste teaches: the second multiplexing circuitry (Fig. 11.25, gray cells from 15 to 12, Pg. 445, Para. 1); select one of the second non-incremented sum and the second incremented sum (Fig. 11.25, gray cells from 15 to 12; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) as a first intermediate sum responsive (Fig. 11.25, output of gray cell at 13) to the non-incremented carry out bit; select one of the second non-incremented sum and the second incremented sum (Fig. 11.25, gray cells from 15 to 12; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) as a second intermediate sum responsive (Fig. 11.25, output of gray cell at 14) to the incremented carry out bit (Pg. 445, Para. 1, assuming a carry-in of 1); and select one of the first and second intermediate sums as the third sum responsive (Fig. 11.25, gray cells from 15 to 13; Pg. 445, Para. 1, multiplexer chooses, Para. 2, simplifying the multiplexer to a gray cell) to the first carry out bit.
The motivation to combine provided with respect to claim 15 equally applies to claim 18.
Regarding claim 19, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein:
the first portion includes
2
n
bits, the second portion includes at most
2
n
-
2
bits, and the third portion includes at most
2
n
-
4
bits (Fig. 1, first - bits A1-, A0 and B1, B0, second – bits A-4, A3, A2, and B4, B3, B2, third – bits A-10, A9, A-8, A7, A6, A5, and B10, B9, B8, B7, B6, B5, [0014]), wherein n is an integer ([0014] indices from 0 to 10).
Regarding claim 20, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Fletcher teaches the device wherein:
the first portion is less significant than the second portion, which is less significant than the third portion (Fig. 1, 3rd group - Sum10-5, 2nd group - Sum4-2, 1st group - Sum1-0, [0014], [0003-0004]).
Claim 1 is directed to a method that would be performed by the device of claim 15. The claim 15 analysis equally applies. Additionally, Fletcher teaches:
performed by a digital logic circuit ([0002], [0013]), an x-bit adder (Fig. 1, 100, [0014] 12-bit adder),
wherein the first portion of the first addend (Fig. 1, A-1 and A0, [0014], [0020]) represents least significant bits of the first addend ([0014] furthest right bit positioning of A), the second portion of the first addend (Fig. 1, A-4, A3, and A2, [0014]) represents most significant bits of the first addend ([0014] furthest left bit positioning of A), the first portion of the second addend (Fig. 1, B1 and B0, [0014], [0020]) represents least significant bits of the second addend ([0014] furthest right bit positioning of B), and the second portion of the second addend (Fig. 1, B4, B3, and B2, [0014]) represents most significant bits of the second addend ([0014] furthest left bit positioning of B), and
wherein the non-incremented sum (Fig. 1, A4 xor B4, A3 xor B3, A2 xor B2, [0019]) and the incremented sum are computed in parallel ([0040]).
Although Fletcher teaches non-incremented sums, they are silent with specifying incremented sums.
Weste discloses incremented sums (Fig. 11.25, output of black cell 7:4).
The motivation to combine provided with respect to claim 15 similarly applies.
Claims 2-3, 7 are directed to a method that would be performed by the device of claim 15. The claims 16-17, 19 analysis equally applies, respectively, claims 2-3, 7 are similarly rejected.
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Fletcher teaches the device wherein:
the first adder circuit includes a tree adder (Fig. 3, 316, 312, 317, 318, 319, 320 group, [0025]) and
the second adder circuit includes a carry select adder (Fig. 4, 434, 426, 435, 430, 431, 432, 433, 437 group, [0028-0030]) which has a different architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]) than the tree architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]).
Although Fletcher teaches the second adder circuit includes a carry adder, they are silent with disclosing the carry adder as a carry select adder.
Weste teaches a carry select adder (Fig. 11.24, Carry-select adder, Pg. 444, 11.2.2.7; Pg. 445, Para. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher’s adder with Weste’s carry select adder because they are in the claimed invention’s same field of endeavor of adders with PG logic (Pg. 445, Para. 2). It would have been obvious to one of ordinary skill in the art to implement the carry select adder, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). It would have been obvious to implement this simple substitution of the carry select adder design as the results of doing so are predictable. Further, Weste teaches that it is a standard logic design technique to accelerate the critical path by precomputing the outputs for both possible inputs, which is what the carry select adder does (Pg. 444, 11.2.2.6). Making this modification would be beneficial, as Fletcher’s adder can accelerate its computations by using its critical path to make appropriate optimizations.
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Fletcher teaches the device wherein:
x=10 and the second portion includes two bits (Fig. 1, A-4, A3, A2, and B4, B3, and B2, [0014])
Fletcher teaches a 12-bit and 23-bit adder ([0014]), but is silent to specifying a 10-bit adder.
Weste teaches a 10-bit adder (Pg. 436, Sec. 11.2.2.1, N-bit adder; Fig. 11.25 includes 10-bits in its 16-bit adder).
The motivation to combine provided with respect to claim 15 equally applies to claim 6.
Regarding claim 21, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Fletcher teaches the device wherein:
the first adder (Fig. 1, 1st Group, [0004], [0014-0015]) computes the first sum (Fig. 1, 1st group - Sum1-0, [0014], [0004]) and the second adder (Fig. 1, 2nd Group, [0004], [0014-0015]) computes the non-incremented sum (Fig. 1, A4 xor B4, A3 xor B3, A2 xor B2, [0019]) and the incremented sum in a same clock ([0040], [0051]).
Although Fletcher teaches non-incremented sums, they are silent with specifying incremented sums.
Weste discloses incremented sums (Fig. 11.25, output of black cell 7:4).
The motivation to combine provided with respect to claim 15 similarly applies.
Claims 8-10, 14, 22 are directed to a device that is similarly recited in claim 1-3, 7, 21. Claims 8-10, 14, 22 recites the same limitations as those in claims 1-3, 7, 21, respectively. The claims 1-3, 7, 21 analysis equally applies, and claims 8-10, 14, 22 are similarly rejected.
Regarding claim 11, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Fletcher teaches the device wherein:
the first adder circuit includes a tree adder (Fig. 3, 316, 312, 317, 318, 319, 320 group, [0025]) having the first architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]),
the second adder circuit includes a carry select adder (Fig. 4, 434, 426, 435, 430, 431, 432, 433, 437 group, [0028-0030]) having the second architecture (Fig. 1, 2nd Group comprises (3) Prop/Gen Block 114, 113, and 112, (1) Group 2 Carry Generation Block 132, (4) Final XNOR Block 162, 163, 164, and 165; [0015]).
Although Fletcher teaches the second adder circuit includes a carry adder, they are silent with disclosing the carry adder as a carry select adder.
Weste teaches a carry select adder (Fig. 11.24, Carry-select adder, Pg. 444, 11.2.2.7; Pg. 445, Para. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Fletcher’s adder with Weste’s carry select adder because they are in the claimed invention’s same field of endeavor of adders with PG logic (Pg. 445, Para. 2). It would have been obvious to one of ordinary skill in the art to implement the carry select adder, as it allows the system to accelerate the critical path by performing precomputations (Pg. 444, Sec. 11.2.2.7). It would have been obvious to implement this simple substitution of the carry select adder design as the results of doing so are predictable. Furhter, Weste teaches that it is a standard logic design technique to accelerate the critical path by precomputing the outputs for both possible inputs, which is what the carry select adder does (Pg. 444, 11.2.2.6). Making this modification would be beneficial, as Fletcher’s adder can accelerate its computations by using its critical path to make appropriate optimizations.
Regarding claim 13, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Fletcher teaches the device wherein:
the first portion includes eight bits (Fig. 1, A-1 A0, and B1,B0, [0014], [0020]) and the second portion includes two bits (Fig. 1, A-4, A3, A2, and B4, B3, and B2, [0014])
Fletcher teaches the first portion including two bits, but is silent to disclosing it as eight bits.
Weste teaches first portion includes eight bits (Fig. 11.25, 7 to 0).
The motivation to combine provided with respect to claim 15 equally applies to claim 13.
Response to Arguments
35 USC 101. The rejections are withdrawn based on the amendment to the claims.
35 USC 112(b). A new rejection is made as necessitated by the amendment to the claims.
35 USC 103. Applicant’s argues the following in substance:
Applicant asserts that, Fletcher's look-ahead carry adder circuit 100 does not include any multiplexing circuitry. There is no disclosure in Fletcher that any two of the carry generation blocks 131, 132, 133 are of different architectures. Moreover, there is no disclosure in Fletcher that each of the different portions of the addends has a different number of bits than each of the other portions.
To the contrary, carry generation blocks 131 and 132 each process the same number of bits, i.e., 2. There is no teaching in Fletcher of incremented and non-incremented sums being computed in parallel. By computing those two sums in parallel, the arrangement of claim 15 advantageously allows selection to occur as soon as the first carry out bit is ready as the selection to the multiplexing circuitry, thus reducing latency (See Remarks p. 9 ⁋2).
Examiner respectfully disagrees. The multiplexing limitations are disclosed by Weste through the combination of Fletcher in view of Weste in view of Awaka in view of Muramatsu. Regarding the limitation of “different architectures”, Fletcher’s Fig. 1 depicts a 1st, 2nd, and 3rd group for the first, second, and third adder circuitry, respectively. Each group contains different number of prop/gen blocks and XNOR blocks connected before/after the carry generation block, and therefore each adder has ‘different architectures’. It appears as if the Applicant has a stricter interpretation of “different architectures” than what is currently claimed. Moreover, the 1st group processes bits [1:0], the 2nd group processes bits [4:2], and the 3rd group processes bits [10:5] of both operands A and B.
Carry generation block 131 processes A1 B1, A0 B0, and Cin through P1G1, P0G0, and Cin, respectively, while carry generation block 132 processes A4 B4, A3 B3, A2 B2 through P4G4, P3G3, and P2G2, respectively. Therefore, blocks 131 and 132 do not process the same number of bits (i.e. 2 bits as Applicant asserted). Weste is relied on to disclose the non-incremented sum, it is through the combination of Fletcher in view of Weste in view of Awaka in view of Muramatsu that discloses incremented and non-incremented sums being computed in parallel. Examiner remarks that the limitation of “multiplexing” although recited in all three independent claims, is interpreted with varying scopes per claim due to the manner and extent it is recited.
Applicant asserts that, Weste does not offset these deficiencies in Fletcher. The adders in FIGs. 11.24 and 11.25 of Weste each process the same number of bits, and the third adder, which processes bits 16:13, does not select, as a sum, one of a second non-incremented sum and a second incremented sum, responsive to non-incremented and incremented carry out bits from the second adder and a carry out bit from a first adder. In Weste, there is no selection signal generated by the first adder and used by the third adder to select a particular sum. Moreover, there is no indication in Weste that the first two adders are of different architectures (See Remarks p. 9 ⁋3).
Examiner respectfully disagrees. Applicant’s argument is directed to claim 15 solely as the other independent claims and their dependent claims do not recite “second non-incremented sum and second incremented sum”. It is through the combination of Fletcher in view of Weste in view of Awaka in view of Muramatsu that discloses selecting, as a sum, one of a second non-incremented and a second incremented sum, responsive to non-incremented and incremented carry out bits from the second adder and a carry out bit from the first adder. A selection signal is not explicitly recited, merely the functionality of selecting. Fletcher is relied upon to disclose the two adders are of different architectures.
Applicant asserts that, independent claim 8 is directed to a device and is likewise allowable over the cited references. Specifically, the combination of references do not teach first and second adder circuits having different architectures, nor does the combination teach a first adder circuit that produces a carry out bit from most significant bit portions the first and second addends, which carry out bit is then used to select, via multiplexing circuitry, between a non-incremented sum and an incremented sum computed in parallel by the second adder circuit (See Remarks p. 9 ⁋4 – p. 10 ⁋1).
Examiner respectfully disagrees. As similarly discussed above, claim 8 recites the limitation of first and second adder circuits having different architectures of which is disclosed by the combination of Fletcher in view of Weste in view of Awaka in view of Muramatsu. Further, the combination discloses a first adder circuit that produces a carry out bit from most significant bit portions the first and second addends, which carry out bit is then used to select, via multiplexing circuitry, between a non-incremented sum and an incremented sum computed in parallel by the second adder circuit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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