DETAILED ACTION
The amendment submitted with an RCE on 06/06/2025 was found to be non-compliant and was not entered, see notice mailed on 06/17/2025.
This action is responsive to the compliant amendment submitted on 08/12/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 07/12/2024 is acknowledged. Claims 1-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Objections
Claim(s) 12 and 18-20 is/are objected to because of the following informalities where proposed corrections are bolded and underlined:
Claim 12, lines 2-3, “configured selectively to operate further in a readout mode” as claim is otherwise grammatically improper;
Claim 18, lines 3-4, “in the doped well during [[the]] an integration time window” as this is the first recitation of an integration time window;
Claim 18, lines 7-11, “subsequent to [[the]] a transfer time window by re-setting the transfer gate of the imaging pixel to form [[the]] a potential barrier between the doped well of the imaging pixel and the FD region of the imaging pixel while continuing the setting of the WCA gate of the imaging pixel to [[the]] a second biasing”, as these are the first recitations of a transfer time window, a potential barrier, and a second biasing;
Claim 20, lines 3-4, “setting the WCA gate to [[the]] a second biasing”, as this is the first recitation of a second biasing as claim 20 does not depend on claim 18.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 8-13 and 16 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Amended claim 8 recites the limitation of “a WCA gate terminal configured to receive a first signal from a controller in the integration mode . . . the WCA gate terminal directly connected to a controller”. It is unclear if the second recitation of “a controller” is the same controller as the first recitation, or if the second recitation should be “[[a]] the controller”. Therefore, claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for unclear antecedent basis and claims 9-13 and 16 are rejected at least for their dependencies. For the purposes of this examination, claim 8 will be interpreted to read as “a WCA gate terminal configured to receive a first signal from a controller in the integration mode . . . the WCA gate terminal directly connected to [[a]] the controller”.
Claim Interpretation
Regarding the language “configured to operate in integration, transfer, spill-back suppression, and readout modes” (along with corresponding applied potentials) as it is used throughout the claims to describe operational characteristics of the device, the Examiner notes this language constitutes functional language and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus/product must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). As best can be determined by the Examiner from the specification of the present application, the structure which performs the claimed function(s) includes the WCA gate which is capacitively coupled to the photodiode region and the controller directly coupled to the WCA gate and the transfer gate for controlling the motion of charges in the device through appropriately applied potentials (see applied potentials and timings detailed in Figures 4, 5, 7, and 8 of the instant application being examined), a structure which is clearly present in the device of US 2021/0185251 A1; Yonemoto, Kazuya; 06/2021; (“Yonemoto”) considered in the 35 U.S.C. 102 rejections below. Therefore, it appears the structure of Yonemoto is capable of performing the function required by the claim language – the Examiner further notes the fact that the structure of Yonemoto can perform additional functions not relevant to the ability to perform the claimed function.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-13 and 16-21 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2021/0185251 A1; Yonemoto, Kazuya; 06/2021; (“Yonemoto”).
Regarding Claim 8. Yonemoto discloses An imaging sensor pixel (#2, Figure 3, pixel) comprising:
a well-capacity-adjustment (WCA) gate photo-sensor block (Figure 3, cross-section of a pixel imager) configured selectively to operate in at least an integration mode ([0106], charge generation and storage time period) and a transfer mode ([0106], stored electrons are transferred via a transfer transistor), the WCA gate photo- sensor block comprising:
a photodiode region (#PD, Figure 3, photodiode) having a doped well (#63, Figure 3, n-type semiconductor region) implanted into a semiconductor substrate (#12, Figure 3, semiconductor substrate which #63 is in) to accumulate photocharge responsive to exposure of the WCA gate photo-sensor block to incident illumination ([0106], charges generated by photoelectric conversion are stored in #63), the doped well having a well capacity defined at least by a well potential (Figure 3, [0158], charge storage capacity of the device is defined by an applied potential);
a WCA gate (#61, Figure 3, trench electrode) integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well (Figure 3, #61 is in #12 and at least partially surrounds and capacitively couples with #63), such that the well potential is based at least on biasing of the WCA gate ([0158], potential and storage of the well is dependent on the potential applied to the capacitor #C1), the WCA gate comprising a single contiguous deep-trench structure that is integrated with the semiconductor substrate and forms the walls that at least partially surround and capacitively couple with the doped well (Figure 3, #61 is a single contiguous deep-trench structure which is integrated with #12 and at least partially surrounds and capacitively couples with #63 through #C1);
a floating diffusion (FD) region (#65, Figure 3, n-type semiconductor region functioning as FD region according to [0089]) implanted into the semiconductor substrate to have a FD potential (Figure 3, #65 is in #12 and may have a potential depending on applied voltages from the controlling lines);
a WCA gate terminal (electrical line between #V1 and #61, Figure 3) configured to receive a first signal from a controller in the integration mode (Figure 1, the electrical line is directly connected to the controller comprising all of the above voltage lines which may apply a voltage signal) and a second signal from the controller in the transfer mode ([0059], voltage at V1 may be set as necessary for operation including negative, zero, or positive voltages), the WCA gate terminal electrically coupled with the deep-trench structure (Figure 3, the electrical line is directly electrically coupled to #61), the first signal setting the well potential to a first well potential corresponding to a full well capacity, the second signal setting the well potential to a second well potential that is less than the first well potential and corresponds to a reduced well capacity ([0059], voltage at V1 may be set as necessary for operation including negative, zero, or positive voltages), the WCA gate terminal directly connected to [[a]] the controller (Figure 3, the electrical line is directly connected to the controller electrical lines); and
a transfer gate (#MT, Figure 3, transfer transistor which necessarily includes a gate) to selectively form a current channel between the doped well and the floating diffusion region ([0065], #MT controls the current channel for charge transfer between the photodiode and the FD region), the current channel having a channel potential less than the FD potential ([0065], a necessary potential may be applied to the transfer gate and channel by the transfer signal to control operation of the device with the channel having an applied potential relative to the FD region for intended operation), the transfer gate directly connected to the controller (Figure 3, the gate of #MT is directly connected to the transfer signal line φT of the controller) and isolated from the semiconductor substrate by an oxide layer.
Regarding Claim 9. Yonemoto discloses The imaging sensor pixel of claim 8, wherein the first well potential ([0106], the maximum amount of charge is stored in the photodiode well, i.e. the highest potential) is configured to be greater than the channel potential ([0106], the channel potential will necessarily be lower as charges are transferred through the channel but not all at once, i.e. a lower potential).
Regarding Claim 10. Yonemoto discloses The imaging sensor pixel of claim 8, wherein the first well potential is configured to be greater than the FD potential ([0106], the maximum amount of charges are stored in the photodiode well, highest potential, and eventually transferred to the FD region in part such that the FD may have a lower potential towards which charges will flow).
Regarding Claim 11. Yonemoto discloses The imaging sensor pixel of claim 8, wherein:
the WCA gate photo-sensor block is configured selectively to operate further in a spill-back suppression mode ([0059], [0105]-[0158], Figure 5, voltage signals may be set as necessary for operational modes including negative, zero, or positive voltages);
in the integration mode, the transfer gate is configured to be OFF to form a potential barrier between the doped well and the floating diffusion region with the WCA gate set to be first-biased during accumulation of photocharge in the photodiode region ([0106], charge generation and storage time period during which voltages or potentials may be set as necessary for operation);
in the transfer mode, the transfer gate is configured to be ON to form the current channel between the doped well and the floating diffusion region with the WCA gate set to be second- biased, such that accumulated photocharge transfers from the doped well to the floating diffusion region via the current channel as transferred photocharge ([0106], charge transfer time period during which voltages or potentials may be set as necessary for operation); and
in the spill-back suppression mode, the transfer gate is configured to be OFF to form the potential barrier between the doped well and the floating diffusion region with the WCA gate set to be second-biased ([0106], time period during which charges are read out by the controller instead of spilled back into the PD region, during which voltages or potentials may be set as necessary for operation).
Regarding Claim 12. Yonemoto discloses The imaging sensor pixel of claim 11, wherein:
the WCA gate photo-sensor block is configured selectively to operate further in a readout mode, the transfer gate is configured to be OFF to form the potential barrier between the doped well and the floating diffusion region during readout of the transferred photocharge from the floating diffusion region ([0106], time period during which charges are read out by the controller instead of spilled back into the PD region, during which voltages or potentials may be set as necessary for operation).
Regarding Claim 13. Yonemoto discloses The imaging sensor pixel of claim 8, wherein:
each of the first signal and the second signal provides a bias to the deep-trench structure (Figure 3, the signal V1 applies a bias directly to the deep trench capacitor structure).
Regarding Claim 16. Yonemoto discloses The imaging sensor pixel of claim 8, wherein: the photodiode region is configured as a pinned photodiode, and the well potential is the pinning voltage of the pinned photodiode (Figure 3, [0158], charge storage capacity of the device is defined by an applied potential which acts as the pinning voltage of the photodiode).
Regarding Claim 17. Yonemoto discloses A complementary metal-oxide semiconductor (CMOS) imaging sensor (CIS) [0053], CMOS image sensor) comprising:
an array of imaging pixels (#2s, Figure 1, array of pixels), each imaging pixel comprising a well-capacity- adjustment (WCA) gate photo-sensor block (Figure 3, cross-section of a pixel imager), each WCA gate photo-sensor block comprising:
a photodiode region (#PD, Figure 3, photodiode) having a doped well (#63, Figure 3, n-type semiconductor region) implanted into a semiconductor substrate (#12, Figure 3, semiconductor substrate which #63 is in) to accumulate photocharge responsive to exposure of the WCA gate photo-sensor block to incident illumination ([0106], charges generated by photoelectric conversion are stored in #63), the doped well having a well capacity defined at least by a well potential (Figure 3, [0158], charge storage capacity of the device is defined by an applied potential);
a WCA gate (#61, Figure 3, trench electrode) integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well (Figure 3, #61 is in #12 and at least partially surrounds and capacitively couples with #63), such that the well potential is based at least on biasing of the WCA gate ([0158], potential and storage of the well is dependent on the potential applied to the capacitor #C1), the WCA gate comprising a single contiguous deep-trench structure that is integrated with the semiconductor substrate and forms the walls that at least partially surround and capacitively couple with the doped well (Figure 3, #61 is a single contiguous deep-trench structure which is integrated with #12 and at least partially surrounds and capacitively couples with #63 through #C1);
a floating diffusion (FD) region (#65, Figure 3, n-type semiconductor region functioning as FD region according to [0089]) implanted into the semiconductor substrate to have a FD potential (Figure 3, #65 is in #12 and may have a potential depending on applied voltages from the controlling lines);
a WCA gate terminal (electrical line between #V1 and #61, Figure 3), the WCA gate terminal electrically coupled with the deep-trench structure (Figure 3, the electrical line is directly electrically coupled to #61); and
a transfer gate (#MT, Figure 3, transfer transistor which necessarily includes a gate) to selectively form a current channel between the doped well and the floating diffusion region ([0065], #MT controls the current channel for charge transfer between the photodiode and the FD region), the current channel having a channel potential less than the FD potential ([0065], a necessary potential may be applied to the transfer gate and channel by the transfer signal to control operation of the device with the channel having an applied potential relative to the FD region for intended operation), the transfer gate isolated from the semiconductor substrate by an oxide layer (Figure 3, #MT is a transistor which necessarily includes a transfer gate structure isolated from the substrate by an oxide layer as the standard transistor structure; [0091], “a gate insulator interposed between the gate electrodes”); and
a controller (Figure 3, grouping of electrical lines used to control operation of the device as part of the control circuit in Figure 1) coupled with the array of imaging pixels (Figure 1, control circuit directly coupled with the array of imaging pixels) to selectively configure each imaging pixel to operate in at least an integration mode ([0106], charge generation and storage time period) and a transfer mode ([0106], stored electrons are transferred via a transfer transistor), the controller directly connected to the transfer gate and the WCA gate terminal (Figure 3, the electrical lines are directly connected to both #61 and the gate of #MT), wherein the controller is configured to provide a first signal to the WCA gate terminal in the integration mode (Figure 1, the electrical line is directly connected to the controller comprising all of the above voltage lines which may apply a voltage signal) and provides a second signal to the WCA gate terminal in the transfer mode ([0059], voltage at V1 may be set as necessary for operation including negative, zero, or positive voltages), the first signal setting the well potential of the imaging pixel to a first well potential corresponding to a full well capacity, the second signal setting the well potential of the imaging pixel to a second well potential that is less than the first well potential and corresponds to a reduced well capacity in the integration mode ([0059], voltage at V1 may be set as necessary for operation including negative, zero, or positive voltages).
Regarding Claim 18. Yonemoto discloses The CIS of claim 17, wherein:
the controller is configured to, in the transfer mode, cause the photocharge accumulated in the doped well during [[the]] an integration time window to transfer to the FD region via the current channel as transferred photocharge ([0106], charge transfer time period during which voltages or potentials may be set as necessary for operation of transferring charges from the PD to the FD region, the charges having been generated during the charge storage time); and
each imaging pixel is configured to operate in a spill-back suppression mode for a spill-back suppression time window subsequent to [[the]] a transfer time window by re-setting the transfer gate of the imaging pixel to form [[the]] a potential barrier between the doped well of the imaging pixel and the FD region of the imaging pixel while continuing the setting of the WCA gate of the imaging pixel to [[the]] a second biasing ([0106], time period during which charges are read out by the controller instead of spilled back into the PD region, during which voltages or potentials may be set as necessary for operation).
Regarding Claim 19. Yonemoto discloses The CIS of claim 18, wherein:
each imaging pixel is configured to operate in a readout mode for a readout time window subsequent to the spill-back suppression time window by directing readout of the transferred photocharge from the FD region by readout circuitry coupled with the FD region with the transfer gate set to form the potential barrier ([0106], time period during which charges are read out by the controller after fully transferring to the FD region and preventing spillback into the PD region, during which voltages or potentials may be set as necessary for operation).
Regarding Claim 20. Yonemoto discloses The CIS of claim 17, wherein:
a plurality of imaging pixels is configured to concurrently operate in the transfer mode by setting the WCA gate to [[the]] a second biasing to concurrently pull the well potentials of the plurality of imaging pixels to the second well potential (Figures 1 and 3, the control circuit may apply the appropriate potentials to #V1 to concurrently operate the plurality of imaging pixels in the array as necessary for operation of the device); and
the controller is further configured to direct readout of the array of imaging pixels according to a global shutter readout routine (Figures 1 and 3, the horizontal and vertical drivers of the controller may set the readout order of the device as required by applying the appropriate signals either concurrently or to each individual pixel as required for the readout routine).
Regarding Claim 21. Yonemoto discloses The CIS of claim 17, wherein: the controller is further configured to direct readout of the array of imaging pixels according to a rolling shutter readout routine that defines a readout sequence (Figures 1 and 3, the horizontal and vertical drivers of the controller may set the readout order of the device as required by applying the appropriate signals either concurrently or to each individual pixel as required for the sequence of the readout routine).
Response to Arguments/Amendments
Applicant’s amendment(s) to claims 8-13 and 16-21, see page 11 of the remarks, filed 08/12/2025, with respect to the original 35 U.S.C. 112(b) rejections of the claims has/have been fully considered. The original 35 U.S.C. 112(b) rejections of claims 8-13 and 16-21 have been withdrawn. However, the amendments to claim 8 have resulted in a new 35 U.S.C. 112(b) rejection as described above. Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for unclear antecedent basis and claims 9-13 and 16 are rejected at least for their dependencies.
Applicant’s amendment(s) to claims 8-13 and 16-21 and corresponding arguments, see pages 11-14 of the remarks, filed 08/12/2025, with respect to the original 35 U.S.C. 102 rejections of the claims in view of US 2017/0186806 A1; Lalanne et al.; 06/2017 and US 2022/0199672 A1; Jin et al.; 06/2022, respectively, has/have been fully considered and are persuasive. The originally cited prior art does not disclose all of the limitations in the amended claims. The original 35 U.S.C. 102 rejections of claims 8-13 and 16-21 have been withdrawn. However, the amendments to the claims have resulted in a new 35 U.S.C. 102 rejection as described above. Claim(s) 8-13 and 16-21 stand rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2021/0185251 A1; Yonemoto, Kazuya; 06/2021; (“Yonemoto”). Yonemoto discloses all of the limitations of the amended claims as described above.
Conclusion
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/TYLER J WIEGAND/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812