Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 13, 2026 has been entered.
Response to Amendment
Amendment to claims 1, 2, 9, 14 and 17 submitted on April 13, 2026 are acknowledged and have since been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (US 20210057280 A1).
Regarding Claim 9, Wu teaches a method of forming a semiconductor device (100), the method comprising:
forming a transistor (see Fig. 3) comprising a gate stack (306) on a semiconductor substrate (107) by at least:
forming a high-k dielectric constant layer (303, see [0045]) on the semiconductor substrate, forming a pretreatment layer (PL) (305, see [0046]) on the high-k dielectric constant layer, determining a thickness for a conductive work function layer (WFL) (307, see [0047]) based on a target effective work function of the transistor (see [0016]), forming the WFL on the pretreatment layer (shown Fig. 3), wherein the conductive work function layer has a WFL thickness substantially equal to the determined thickness, performing an in-situ silane soak (see [0049]) on the WFL, and forming a soak layer (309) having a soak layer thickness directly on the conductive work function layer upon performing the in-situ silane soak wherein the soak layer thickness is determined based at least in part on the WFL thickness (see [0016] which describes varying threshold voltage of the gate stack depending on a thickness of the capping layer, which is directly related to a thickness of the underlying work function layer),
wherein the gate stack has a tuned effective work function according to the determined thickness (see [0016]).
Regarding Claim 13, Wu teaches the method of claim 9, wherein the transistor has a FinFET or a nanostructure transistor structure (see [0015]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 and 14-20 are rejected under 35 U.S.C. 103 as being obvious over Tsai (US 20190371675 A1) in further view of Wu (US 20210057280 A1).
Regarding Claims 1 and 14, Tsai teaches a method of forming a semiconductor device (see Fig. 13 and [0054-0064]), the method comprising:
forming a first transistor (shown Fig. 13) comprising a first gate stack in a first region (1302) of a semiconductor substrate (200) by at least:
forming a first high-k dielectric constant layer (1310, see also [0055]) on the semiconductor substrate, forming a first pretreatment layer (PL) (1308, see [0055] which lists TiAlC as a work-function tuning material) on the first high-k dielectric constant layer (shown Fig. 13), forming a first conductive work function layer (WFL) (TiN, see also [0028-0029] which describes a previous embodiment which incorporates multiple cycles of a TiAlC and TiN scheme as the work-function tuning layer) on the first pretreatment layer, wherein the first conductive work function layer has a first WFL thickness (further described in [0029] and [0065], wherein the number of deposition cycles enables tuning of thickness of the work-function tuning layer and thus the effective work function of the transistor), performing an in-situ silane soak on the first conductive work function layer and forming a first soak layer having a first soak layer thickness (261, also referred to as a “surface layer”, see also [0043] and [0063] which describes implementing the steps of Figs. 9-11 after deposition of the work-function tuning layer) upon performing the in-situ silane soak (see also [0036-0038] which describes in-situ silane soaking); and
forming a second transistor (shown Fig. 13) comprising a second gate stack in a second region (1304) of the semiconductor substrate by at least:
forming a second high-k dielectric constant layer (1310) on the semiconductor substrate, forming a second pretreatment layer (1308) on the second high-k dielectric constant layer, forming a second conductive work function layer (see as described above) on the second pretreatment layer, wherein the second conductive work function layer has a second WFL thickness (see Fig. 13 which shows examples of a first and second gate stack with varying thickness), and forming a second soak layer having a second soak layer thickness (263) upon performing the in-situ silane soak, wherein the first WFL thickness is greater than the second WFL thickness.
Furthermore, one of ordinary skill in the art prior to the effective filing date of the instant application would be motivated upon reading Tsai to implement the multilayer TiAlC/TiN work-function tuning layer 244 described in [0028] with a first thickness and a second thickness on a first transistor and second transistor respectively as this would enable tuning of the effective work function of the gate stacks on separate transistors disposed on a common substrate (see also [0053]). In addition, paragraph [0043] of Tsai describes implementing the in-situ silane soak to form a soak layer “until a desired thickness is reached.” As such, it would be obvious to one of ordinary skill in the art to implement a device wherein the second soak layer thickness is greater than the first soak layer thickness to further accommodate tuning of individual devices.
Tsai further teaches that “various embodiments include an in-situ pre-treatment or pre-deposition treatment process with includes soaking a barrier layer and/or a work-function tuning layer”, but does not explicitly show the first soak layer being directly on the first conductive work function layer and the second soak layer being directly on the second conductive work function layer.
Wu teaches a method of forming a semiconductor device (100), the method comprising:
forming a transistor (see Fig. 3) comprising a gate stack (306) on a semiconductor substrate (107) by at least:
forming a high-k dielectric constant layer (303, see [0045]) on the semiconductor substrate, forming a pretreatment layer (PL) (305, see [0046]) on the high-k dielectric constant layer, forming a WFL on the pretreatment layer (shown Fig. 3), performing an in-situ silane soak (see [0049]) on the WFL, and forming a soak layer (309) having a soak layer thickness directly on the conductive work function layer upon performing the in-situ silane soak.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method of Tsai with the method of Wu by performing the in-situ silane soak on the conductive work-function metal layer, thus forming the soak layer directly on the conductive work-function metal layer as this would further reduce a total thickness and increase the gap-fill window for lower costs to form subsequent layers while also allowing for a better threshold stability as fewer voids can be formed and the metal gate can completely fill the openings (see Wu: [0079]).
The device of claim 14 is taught as a result of the method steps described above.
Regarding Claims 2 and 17, Tsai as modified by Wu teaches the method of claim 1 and the device of claim 14, wherein the first gate stack has a first effective work function, the second gate stack has a second effective work function, and the first effective work function is greater than the second effective work function (see [0017] which describes “a desired multiple threshold voltage scheme” wherein the first gate stack and second gate stack may each be tuned to a corresponding desired effective work function).
Regarding Claims 3 and 16, Tsai as modified by Wu teaches the method of claim 1 and the device of claim 14, wherein the first and second pretreatment layers each comprise Aluminum (see [0055] which describes TiAlC).
Regarding Claim 4, Tsai as modified by Wu teaches the method of claim 3, wherein the first and second pretreatment layers each comprise Carbon (see [0055] which describes TiAlC).
Regarding Claim 5, Tsai as modified by Wu teaches the method of Claim 1, wherein forming the first pretreatment layer on the first high-k dielectric constant layer and forming the second pretreatment layer on the second high-k dielectric constant layer each comprise performing 2 or 3 atomic layer deposition (ALD) cycles (see [0029] which describes multiple deposition cycles), wherein at least one atomic layer deposition (ALD) cycle is performed with one or more precursors selected from a group containing Triethlyaluminum (TEA), Trimethlyaluminium (TMA), AlCl3, Titanium Chloride (TiClx), and Tantalum Chloride (TaClx) (see [0064] which describes that the pre-deposition soaking treatment may be performed on any appropriate next metal layer, such as a work-function tuning layer, a barrier layer, or a capping layer. See also [0038] which describes that the pre-treatment reactant agent may include aluminum based precursors, for example TEA or TMA).
Regarding Claims 6 and 18, Tsai teaches the method of claim 1 and the device of claim 14, wherein the first pretreatment layer has a first PL thickness, wherein the second pretreatment layer has a second PL thickness, and wherein the first PL thickness is about equal to the second PL thickness (see layer 1208 and [0053], wherein the layer 1208 corresponds to the TiAlC pretreatment layer and is shown in Fig. 12 having substantially uniform thickness across multiple devices, while the TiN layer corresponding to the conductive work function layer has variable thickness).
Regarding Claim 15, Tsai as modified by Wu teaches the semiconductor device of claim 14, wherein at least one of the first and second transistors has a FinFET or a nanostructure transistor structure.
Regarding Claims 7, 8, 19 and 20, Tsai as modified by Wu teaches the method of claim 1 and the device of claim 14, but is silent regarding explicit ratios of work-function layer thickness to pre-treatment layer thickness and first work-function layer thickness to second work-function layer thickness.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Tsai shows that thickness of the TiAlC pre-treatment layer and TiN work function metal layers are result-effective variables because the thickness results in predictability of effective work function for each transistor on the semiconductor device (see [0053] and [0029]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness range and ratio of work-function layer to pre-treatment layer for each transistor on the semiconductor device to optimally tune the effective work function of each transistor to meet the performance needs of the product. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.” (see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, a ratio of the first WFL thickness to the first PL thickness, a ratio of a second WFL thickness to a second PL thickness, and a ratio of the first WFL thickness to the second WFL thickness would be obvious to implement through routine optimization.
Claim(s) 10-11 are rejected under 35 U.S.C. 103 as being obvious over Wu (US 20210057280 A1).
Regarding Claim 10, Wu teaches the method of claim 9 wherein a thickness of the soak layer depends on a thickness of the WFL thickness, but does not explicitly teach that the soak layer thickness is inversely related to the WFL thickness.
Wu further describes optimizing a combined thickness (T4 and T5) of the soak layer and work-function layer to accommodate a desired threshold voltage while enhancing the critical dimension window for forming the metal fill (see [0016]). It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to tune the combined thickness of the soak layer and work-function layer to optimize the critical dimension window for forming the metal fill, such that a higher work-function layer thickness T4 would result in a relatively lower soak layer thickness T5 and vice versa, thus creating an inverse relationship between WFL thickness and soak layer thickness. This would further reduce a total thickness and increase the gap-fill window for lower costs to form subsequent layers while also allowing for a better threshold stability as fewer voids can be formed and the metal gate can completely fill the openings (see [0079]).
Regarding Claim 11, Wu teaches the method of claim 10, wherein performing the in-situ silane soak is performed at a temperature in a range from about 350°C to about 475°C (see [0050]).
Claim(s) 12 is rejected under 35 U.S.C. 103 as being obvious over Wu (US 20210057280 A1) in further view of Tsai (US 20190371675 A1).
Regarding Claim 12, Wu teaches the method of claim 11, but is silent regarding a pressure of the in-situ silane soak.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Tsai shows that variables like number of deposition cycles, number of pulses of precursors, pulse frequency, substrate temperature, pressure, and the like alter a thickness of the work-function tuning layer (see [0029]). Further, it is understood that these variables would have a physical effect on any layer deposited using an ALD process (i.e., the soak layer).
A person having ordinary skill in the art using this prior art teaching, therefore, would predict the optimal pressure range to implement the in-situ silane soak so as to successful deposit a soak layer at a desirable thickness (see also [0043]). Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.” (see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, a pressure range between 12 torr and 25 torr would be obvious to implement through routine optimization.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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