Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment to claims 1, 9-12 and 14 submitted on November 9, 2025 are acknowledged and have since been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 9-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Tsai (US 20190371675 A1).
Regarding Claims 1 and 14, Tsai teaches a method of forming a semiconductor device (see Fig. 13 and [0054-0064]), the method comprising:
forming a first transistor (shown Fig. 13) comprising a first gate stack (see annotated below) in a first region (1302) of a semiconductor substrate (200) by at least:
forming a first high-k dielectric constant layer (1310, see also [0055]) on the semiconductor substrate, forming a first pretreatment layer (PL) (1308, see [0055] which lists TiAlC as a work-function tuning material) on the first high-k dielectric constant layer (shown Fig. 13), forming a first conductive work function layer (WFL) (TiN, see also [0028-0029] which describes a previous embodiment which incorporates multiple cycles of a TiAlC and TiN scheme as the work-function tuning layer) on the first pretreatment layer, wherein the first conductive work function layer has a first WFL thickness (further described in [0029] and [0065], wherein the number of deposition cycles enables tuning of thickness of the work-function tuning layer and thus the effective work function of the transistor), performing an in-situ silane soak on the first conductive work function layer and forming a first soak layer having a first soak layer thickness (261, also referred to as a “surface layer”, see also [0043] and [0063] which describes implementing the steps of Figs. 9-11 after deposition of the work-function tuning layer) upon performing the in-situ silane soak (see also [0036-0038] which describes in-situ silane soaking) on the first conductive work function layer, wherein the first gate stack has a first effective work function (see [0062]); and
forming a second transistor (shown Fig. 13) comprising a second gate stack (see annotated below) in a second region (1304) of the semiconductor substrate by at least:
forming a second high-k dielectric constant layer (1310) on the semiconductor substrate, forming a second pretreatment layer (1308) on the second high-k dielectric constant layer, forming a second conductive work function layer (see as described above) on the second pretreatment layer, wherein the second conductive work function layer has a second WFL thickness (see Fig. 13 which shows examples of a first and second gate stack with varying thickness), and forming a second soak layer having a second soak layer thickness (263) upon performing the in-situ silane soak on the second conductive work function layer, wherein the second gate stack has a second effective work function, wherein the first WFL thickness is greater than the second WFL thickness, and wherein the first effective work function is greater than the second effective work function (see layer 1208 and 1212 of the embodiment 1200 corresponding to Fig. 12, which are analogous to the work-function tuning layer 244 described in the first embodiment and layers 1308 and 1312 of the third embodiment, of which a first WFL thickness corresponds to T1 and a second WFL thickness corresponds to T2. See also [0053] which describes the advantages of implementing work-function tuning layers of the same composition being deposited at different thicknesses to tune the effective work function, see also [0064] which explains that advantageous features, like the variable thickness of the work-function tuning layers discussed, are not limited to any one specific embodiment).
Furthermore, one of ordinary skill in the art prior to the effective filing date of the instant application would be motivated upon reading Tsai to implement the multilayer TiAlC/TiN work-function tuning layer 244 described in [0028] with a first thickness and a second thickness on a first transistor and second transistor respectively as this would enable tuning of the effective work function of the gate stacks on separate transistors disposed on a common substrate (see also [0053]). In addition, paragraph [0043] of Tsai describes implementing the in-situ silane soak to form a soak layer “until a desired thickness is reached.” As such, it would be obvious to one of ordinary skill in the art to implement a device wherein the second soak layer thickness is greater than the first soak layer thickness to further accommodate tuning of individual devices.
The device of claim 14 is taught as a result of the method steps described above.
PNG
image1.png
100
100
image1.png
Greyscale
Regarding Claims 2 and 15, Tsai teaches the method of claim 1 and the device of claim 14, wherein at least one of the first and second transistors has a FinFET or a nanostructure transistor structure (see [0012] which describes these methods being implemented in FinFET and nanowire channel FETs).
Regarding Claims 3 and 16, Tsai teaches the method of claim 1 and the device of claim 14, wherein the first and second pretreatment layers each comprise Aluminum (see [0055] which describes TiAlC).
Regarding Claims 4 and 17, Tsai teaches the method of claim 3 and the device of claim 16, wherein the first and second pretreatment layers each comprise Carbon (see [0055] which describes TiAlC).
Regarding Claim 5, Tsai teaches the method of Claim 1, wherein forming the first pretreatment layer on the first high-k dielectric constant layer and forming the second pretreatment layer on the second high-k dielectric constant layer each comprise performing 2 or 3 atomic layer deposition (ALD) cycles (see [0029] which describes multiple deposition cycles), wherein at least one atomic layer deposition (ALD) cycle is performed with one or more precursors selected from a group containing Triethlyaluminum (TEA), Trimethlyaluminium (TMA), AlCl3, Titanium Chloride (TiClx), and Tantalum Chloride (TaClx) (see [0064] which describes that the pre-deposition soaking treatment may be performed on any appropriate next metal layer, such as a work-function tuning layer, a barrier layer, or a capping layer. See also [0038] which describes that the pre-treatment reactant agent may include aluminum based precursors, for example TEA or TMA).
Regarding Claims 6 and 18, Tsai teaches the method of claim 1 and the device of claim 14, wherein the first pretreatment layer has a first PL thickness, wherein the second pretreatment layer has a second PL thickness, and wherein the first PL thickness is about equal to the second PL thickness (see layer 1208 and [0053], wherein the layer 1208 corresponds to the TiAlC pretreatment layer and is shown in Fig. 12 having substantially uniform thickness across multiple devices, while the TiN layer corresponding to the conductive work function layer has variable thickness).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-13 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20190371675 A1).
Regarding Claims 7, 8, 19 and 20, Tsai teaches the method of claim 1 and the device of claim 14, but is silent regarding explicit ratios of work-function layer thickness to pre-treatment layer thickness and first work-function layer thickness to second work-function layer thickness.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Tsai shows that thickness of the TiAlC pre-treatment layer and TiN work function metal layers are result-effective variables because the thickness results in predictability of effective work function for each transistor on the semiconductor device (see [0053] and [0029]).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness range and ratio of work-function layer to pre-treatment layer for each transistor on the semiconductor device to optimally tune the effective work function of each transistor to meet the performance needs of the product. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.” (see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, a ratio of the first WFL thickness to the first PL thickness, a ratio of a second WFL thickness to a second PL thickness, and a ratio of the first WFL thickness to the second WFL thickness would be obvious to implement through routine optimization.
Regarding Claim 9, Tsai teaches a method of forming a semiconductor device (see steps in Figs. 5-11), the method comprising:
forming a transistor (250b) comprising a gate stack (see annotated Fig. 11 below) on a semiconductor substrate (200) by at least:
forming a high-k dielectric constant layer (242, see also [0026]) on the semiconductor substrate, forming a pretreatment layer (PL) (244, see [0028] which describes TiAlC used as the “work-function tuning layer”) on the high-k dielectric constant layer (shown Fig. 11), determining a thickness for a conductive work function layer (WFL) (see [0028-0029] which further describes a TiAlC and TiN scheme used for the work-function tuning layers, wherein the number of deposition cycles enables tuning of thickness of the work-function tuning layer and thus the effective work function of the transistor) based on a target effective work function of the transistor (see also [0065] which describes the advantage of tuning the thickness of the work-function tuning layer to change the work function value), forming the WFL (the TiN layer) on the pretreatment layer (the TiAlC layer), wherein the conductive work function layer has a WFL thickness substantially equal to the determined thickness, and forming a soak layer having a soak layer thickness (261, see [0039-0040] which describes a silicon monolayer, and [0043] describing the formed “surface layer”, see also Figs. 9-11) upon performing an in-situ silane soak (see [0036-0038]) on the conductive work function layer (shown Fig. 11), wherein the gate stack has a tuned effective work function
PNG
image3.png
100
100
image3.png
Greyscale
according to the determined thickness (see [0065]).
Tsai does not explicitly describe the soak layer thickness being determined based at least in part of the WFL thickness. However, Tsai teaches an effective work function of each device further being effected by a resulting thickness of the resultant soak layer (see [0043]). As such, one of ordinary skill in the art prior to the effective filing date of the instant application would further optimize both a thickness of the soak layer and a thickness of the work-function layer to accommodate a desirable effective work-function (see also [0043] and [0065]).
Regarding Claim 10, Tsai teaches the method of claim 9, but does not explicitly teach wherein the soak layer thickness is inversely related to the WFL thickness.
However, as applied to claim 9 above, one of ordinary skill in the art prior to the effective filing date of the instant application would expect an inverse relationship between soak layer thickness and WFL thickness when optimizing thickness to tune the transistor devices to a desirable effective work-function so as to achieve a relatively uniform thickness across different transistor devices within the semiconductor device (see Fig. 11 which shows differing layer sequences on devices 250a and 250b while maintaining a relatively uniform total thickness).
Regarding Claim 11, Tsai teaches the method of claim 10, wherein performing the in-situ silane soak is performed at a temperature in a range from about 200° C to about 500° C as cited in paragraph [0045] and further suggests an exemplary temperature being between about 350° C. to about 420° C in the specific example described in paragraph [0057].
Regarding Claim 12, Tsai teaches the method of claim 11, wherein an exemplary TiAlC deposition occurs in a chamber with between 1 and 20 Torr or pressure. Tsai is silent regarding a chamber pressure during the in-situ silane soak.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Tsai shows that variables like number of deposition cycles, number of pulses of precursors, pulse frequency, substrate temperature, pressure, and the like alter a thickness of the work-function tuning layer (see [0029]). Further, it is understood that these variables would have a physical effect on any layer deposited using an ALD process (i.e., the soak layer).
A person having ordinary skill in the art using this prior art teaching, therefore, would predict the optimal pressure range to implement the in-situ silane soak so as to successful deposit a soak layer at a desirable thickness (see also [0043]). Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.” (see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, a pressure range between 12 torr and 25 torr would be obvious to implement through routine optimization.
Regarding Claim 13, Tsai teaches the method of claim 9, wherein the transistor has a FinFET or a nanostructure transistor structure (see [0012] which explicitly describes this method being implemented with FinFET devices or nanowire channel FETs).
Response to Arguments
Applicant's arguments filed November 9, 2025 have been fully considered but they are not persuasive.
Regarding claims 1 and 14, applicant argues that Tsai fails to teach a first soak layer and a second soak layer, wherein the second soak layer has a second thickness greater than a first thickness of the first soak layer. Examiner respectfully disagrees and notes that soak layers 261 and 263 are formed on respective devices 250a and 250b to a “desired thickness” as cited in paragraph [0043] of Tsai.
Regarding claim 9, applicant argues that Tsai teaches a “one-size-fits-all” soak layer with uniform thickness on both devices. Examiner respectfully disagrees, and notes that Tsai implicitly teaches two separate soak layers (261 and 263, shown Figs. 8A-8B) wherein growing each surface layer “monolayer by monolayer until a desired thickness is reached” is implemented (see [0043]). One of ordinary skill in the art prior to the effective filing date would expect a relationship between a thickness of the soak layer and thickness of the work-function tuning layer toward the effort of device optimization.
Regarding claim 11, applicant argues that Tsai teaches an in-situ silane soak being performed at low temperature. Examiner notes that Tsai further teaches an in-situ silane soak being performed at a temperature range of 250-500 degrees Celsius (see [0044] which narrowly overlaps the claimed temperature range. Furthermore, variables like temperature and pressure during deposition of material layers is commonly understood in the art to have an effect on the quality and thickness on resultant material layers as detailed in claim 12 above. For these reasons, the claims stand rejected as detailed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893