DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 19, 20, 23, 27, 30 and 32 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liff et al. (US 20200279813).
As for claim 19 and 23, Liff et al. disclose in Figs. 4A-4B and the related text a method of forming an integrated chip structure, comprising:
processing a first substrate 110 according to a first fabrication process to form a first chiplet 102 predominantly having a first plurality of devices and a first plurality of interconnects over the first plurality of devices ([0029], [0087]-[0088]), wherein the first plurality of devices are a first type of integrated chip device ([0029], [0087]-[0088]), and wherein the first fabrication process is associated with a first technology node having a first minimum feature size (Fig. 1A-4B, [0051]-[0052]);
processing a second substrate according to a second fabrication process to form a second chiplet 130-1 predominantly having a second plurality of devices and a second plurality of interconnects over the second plurality of devices ([0029], [0087]-[0088]), wherein the second plurality of devices are a second type of integrated chip device that is different than the first type of integrated chip device ([0029], [0087]-[0088]), and wherein the second fabrication process is associated with a second technology node having a second minimum feature size that is different than the first minimum feature size (Fig. 1A-4B, [0051]-[0052]);
processing a third substrate according to a third fabrication process to form a third chiplet 130-2 predominantly having a third plurality of devices and a third plurality of interconnects over the third plurality of devices ([0029], [0087]-[0088]), wherein the third plurality of devices are a third type of integrated chip device that is different than the first type of integrated chip device and the second type of integrated chip device ([0087]-[0088]), and wherein the third fabrication process is associated with a third technology node having a third minimum feature size that is different than the second minimum feature size (Fig. 1A-4B, [0051]-[0052]);
processing a fourth substrate according to a fourth fabrication process to form a fourth chiplet 130-3 predominantly having a fourth plurality of devices and a fourth plurality of interconnects over the fourth substrate ([0029], [0087]-[0088]), wherein the fourth integrated chip structure 130-3 predominantly comprising one or more types of passive devices [0029]; and
bonding the second chiplet 130-1, and the third chiplet 130-2, and the fourth chiplet 130-3 to an upper surface of the first chiplet 102 by way of a plurality of inter-tier connectors or conductive bump structures 140-1/140-2/140-3 [0066] that continuously extend between the upper surface of the first integrated chip structure and lower surfaces of the second integrated chip structure, the third integrated chip structure, and the fourth integrated chip structure (Fig. 4B),
wherein the second chiplet 130-1, the third chiplet 130-2, and the fourth chiplet 130-4 have footprints that are entirely laterally outside of one another (Fig. 4B), and wherein the first plurality of interconnects 140-1 are between the first substrate 110 and the second substrate 139-1 and wherein the second plurality of interconnects 138-1 are arranged along a surface of the second substrate 139-1 facing away from the first substrate 110 (Fig. 4B),
wherein an imaginary horizontal line that is parallel to the upper surface of the first integrated chip structure 102 laterally extends through sidewalls of the second integrated chip structure 130-1, the third integrated chip structure 130-2, and the fourth integrated chip structure 130-3 (Fig. 4B).
As for claim 20, Liff et al. disclose the method of claim 19, wherein the first chiplet 102 laterally extends in opposing directions for non-zero distances past opposing outermost edges of the second chiplet 130-1 in a cross-sectional view (Fig. 4B).
As for claim 22, Liff et al. disclose the method of claim 19, wherein the fourth chiplet 130-3 consists of passive devices [0029].
As for claim 25, Liff et al. disclose the method of The method of wherein a first sidewall spacer having a first type of strain is formed along opposing sides of the first gate; and wherein a second sidewall spacer having a second type of strain is formed along opposing sides of the second gate, the first type of strain being different than the second type of strain ([0090]-[0092]).
As for claim 27, Liff et al. disclose the method of The method of wherein the first type of integrated chip device 102 is an NMOS transistor [0090] with a silicon carbide source/drain region ([0032]-[0033]); and wherein the second type of integrated chip device 130-1 is a PMOS transistor [0090] with a silicon germanium source/drain region ([0032]-[0033]).
As for claim 30, Liff et al. disclose the method of claim 23, wherein the upper surface of the first integrated chip structure 102 laterally extends past outermost edges of the second integrated chip structure 130-1, the third integrated chip structure 130-2.
As for claim 32, Liff et al. disclose the method of claim 23, wherein the second integrated chip structure 130-1 is laterally separated from the third integrated chip structure 130-2 by a non-zero distance (Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21 are rejected under 35 U.S.C. 103 as being unpatentable over Liff et al. in view of Young et al. (US 2021/0242240, as disclosed in previous office action).
As for claim 21, Liff et al. disclose the method of claim 19, except a contact etch stop layer is disposed on the first substrate and along opposing sides a gate structure of the first type of integrated chip device in a cross-sectional view, the contact etch stop layer having a first type of strain; and wherein a sidewall spacer is disposed on the second substrate and comprises discrete segments arranged along opposing sides of a gate structure of the second type of integrated chip device, sidewall spacer having a second type of strain that is different than the first type of strain.
Young et al. teach in Fig. 1 and the related text a contact etch stop layer (118 of LV1) is disposed on the first substrate 110 and along opposing sides a gate structure 114 of the first type of integrated chip device in a cross-sectional view (Fig. 1), the contact etch stop layer having a first type of strain [0049]; and wherein a sidewall spacer (118 of LV2) is disposed on the second substrate 150 and comprises discrete segments arranged along opposing sides of a gate structure of the second type of integrated chip device (fig. 1), sidewall spacer having a second type of strain that is different than the first type of strain [0049].
Liff et al. and Young et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liff et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Liff et al. to include the limitations as taught by Young et al., in order to prevent leakage current.
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Liff et al. in view of Martorell et al. (US 2021/0111113, as disclosed in previous office action).
As for claim 24, Liff et al. disclose the method of claim 23, except a first type of integrated chip device is a first type of transistor device having a first gate length; and wherein the second type of integrated chip device is a second type of transistor device having a second gate length is different than the first gate length.
Martorell et al. teach in Fig. 1-3 and the related text a first type of integrated chip device 170 is a first type of transistor device having a first gate with a first gate length; and wherein the second type of integrated chip device is a second type of transistor device 120A having a second gate with a second gate length is different than the first gate length [0043].
Liff et al. and Martorell et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liff et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Liff et al. to include the limitations as taught by Martorell et al., in order to improve performance of the device.
Claims 26, 29,31 and 33-38 are rejected under 35 U.S.C. 103 as being unpatentable over Liff et al. in view of Celaya et al. (US 2011/0298115, as disclosed in previous office action).
As for claim 26, 29 and 31, Liff et al. disclose the method of claim 23,
wherein the third type of integrated chip device is (electrically) connected to a gate of a PMOS transistor [0090] disposed on the second integrated chip structure 140-1 and further connected to a gate of an NMOS transistor (second type of integrated chip device 130-2) disposed on the first integrated chip structure ([0029], [0087]-[0090]).
Liff et al. do not disclose the third type of integrated chip device is a gate driver circuit.
Celaya et al. teach in Fig. 5 and the related text a (third type of) integrated chip device 18 is a gate driver circuit [0002].
Liff et al. and Celaya et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Liff et al. to include the limitations as taught by Celaya et al., in order to provide gate drive signal (Celaya et al. [0002]).
As for claim 33, Liff et al. disclose in Figs. 4A-4B and the related text a method of forming an integrated chip, comprising:
forming a first chiplet 102 predominantly comprising NMOS transistor devices disposed on a first substrate 110 ([0088]-[0090]);
forming a second chiplet 130-1 predominantly comprising PMOS transistor devices disposed on a second substrate 139-1 ([0088]-[0090]);
forming a third chiplet 130-2 predominantly comprising passive devices disposed on a third substrate 139-2 ([0086]-[0090]);
forming a fourth chiplet 130-3 predominantly comprising gate transistor[0086]; and
bonding the first chiplet 102 to the second chiplet 130-1, the third chiplet 130-2, and the fourth chiplet 130-3 by way of a plurality of conductive bump structures 140-1/140-2/140-3 contacting an upper surface of the first chiplet and lower surfaces of the second chiplet, the third chiplet, and the fourth chiplet (Fig. 4B), wherein the second chiplet, the third chiplet, and the fourth chiplet are at equal distances over the upper surface of the first chiplet (Fig. 4B).
Liff et al. do not disclose the third type of integrated chip device is a gate driver circuit.
Celaya et al. teach in Fig. 5 and the related text a (third type of) integrated chip device 18 is a gate driver circuit [0002].
Liff et al. and Celaya et al. are analogous art because they both are directed stacked wafer/dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Liff et al. to include the limitations as taught by Celaya et al., in order to provide gate drive signal (Celaya et al. [0002]).
As for claim 34, Liff et al. disclose the method of claim 33, further comprising: forming the first chiplet using a first fabrication process associated with a first technology node having a first minimum feature size; and forming the second chiplet using a second fabrication process associated with a second technology node having a second minimum feature size that is different than the first minimum feature size.
As for claim 35, Liff et al. disclose the method of claim 34, wherein the first chiplet is larger 102 than the second chiplet 130-1 and the third chiplet 130-2 (Fig. 4B).
As for claim 36, Liff et al. disclose the method of claim 34, wherein a front-side of the first substrate 110 and backsides of the second substrate 139-1 and the third substrate face the plurality of conductive bump structures (Fig. 4B).
As for claim 37, Liff et al. disclose the method of claim 33, further comprising: forming a plurality of interconnects 136-2 along a front-side of the second substrate facing away from the first substrate, the plurality of interconnects coupled to the PMOS transistor devices (Fig. 4B and 9); and forming a through substrate via (TSV) extending through the second substrate [0102], wherein the TSV is configured to be coupled between the plurality of interconnects and the plurality of conductive bump structures (Fig. 4 and 9).
As for claim 38, Liff et al. disclose the method of claim 33, wherein the third chiplet 130-3 consists essentially of the passive devices disposed on the third substrate 139-3 [0029].
Allowable Subject Matter
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the first integrated chip structure comprises a plurality of well regions disposed within a first substrate and separated from one another by isolation regions in a cross-sectional view, the plurality of well regions and the isolation regions collectively and continuously extending from directly below the second integrated chip structure to directly below the third integrated chip structure” as recited in claim 28.
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG Q TRAN/Primary Examiner, Art Unit 2811
